Philips Semiconductors

Product specification

TrenchMOS transistor
Logic level FET
GENERAL DESCRIPTION
N-channel enhancement mode logic
level field-effect power transistor in a
plastic envelope suitable for surface
mounting. The device features very
low on-state resistance and has
integral zener diodes giving ESD
protection. It is intended for use in
automotive and general purpose
switching applications.

PINNING - SOT223
PIN

BUK98150-55

QUICK REFERENCE DATA

SYMBOL

PARAMETER

VDS
ID
Ptot
Tj
RDS(ON)

Drain-source voltage
Drain current
Total power dissipation
Junction temperature
Drain-source on-state
resistance
VGS = 5 V

PIN CONFIGURATION

MAX.

UNIT

55
5.5
1.8
150
150

V
A
W
C
m

SYMBOL

DESCRIPTION

gate

drain

source

drain (tab)

LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL

PARAMETER

CONDITIONS

VDS
VDGR
VGS
ID
ID

Drain-source voltage
Drain-gate voltage
Gate-source voltage
Drain current (DC)
Drain current (DC)

ID

Drain current (DC)

IDM
Ptot
Ptot

Drain current (pulse peak value)

Total power dissipation
Total power dissipation

Tstg, Tj

Storage & operating temperature

RGS = 20 k
Tsp = 25 C
On PCB in Fig.19
Tamb = 25 C
On PCB in Fig.19
Tamb = 100 C
Tsp = 25 C
Tsp = 25 C
On PCB in Fig.19
Tamb = 25 C
-

MIN.

MAX.

UNIT

55
55
10
5.5
2.6

V
V
V
A
A

1.6

30
8.3
1.8

A
W
W

- 55

150

MIN.

MAX.

UNIT

kV

ESD LIMITING VALUE

SYMBOL

PARAMETER

CONDITIONS

VC

Electrostatic discharge capacitor

voltage

Human body model

(100 pF, 1.5 k)

February 1998

Rev 1.000

Philips Semiconductors

Product specification

TrenchMOS transistor
Logic level FET

BUK98150-55

THERMAL RESISTANCES
SYMBOL

PARAMETER

CONDITIONS

Rth j-sp
Rth j-amb

From junction to solder point

From junction to ambient

Mounted on any PCB

Mounted on PCB of Fig.18

TYP.

MAX.

UNIT

12
-

15
70

K/W
K/W

STATIC CHARACTERISTICS
Tj= 25C unless otherwise specified
SYMBOL

PARAMETER

CONDITIONS

V(BR)DSS

Drain-source breakdown
voltage
Gate threshold voltage

VGS = 0 V; ID = 0.25 mA

VGS(TO)

Tj = -55C
VDS = VGS; ID = 1 mA
Tj = 150C
Tj = -55C

IDSS

Zero gate voltage drain current

VDS = 55 V; VGS = 0 V;

IGSS

Gate source leakage current

VGS = 5 V

V(BR)GSS
RDS(ON)

Gate source breakdown voltage VGS = 1 mA

Drain-source on-state
VGS = 5 V; ID = 5 A
resistance

Tj = 150C
Tj = 150C
Tj = 150C

MIN.

TYP.

MAX.

UNIT

55
50
1.0
0.6
10
-

1.5
0.05
0.02
120
-

2.0
2.3
10
100
1
5
150
277

V
V
V
V
V
A
A
A
A
V
m
m

MIN.

TYP.

MAX.

UNIT

DYNAMIC CHARACTERISTICS
Tmb = 25C unless otherwise specified
SYMBOL

PARAMETER

CONDITIONS

gfs

Forward transconductance

VDS = 25 V; ID = 5 A; Tj = 25C

Ciss
Coss
Crss

Input capacitance
Output capacitance
Feedback capacitance

VGS = 0 V; VDS = 25 V; f = 1 MHz

250
65
35

330
80
50

pF
pF
pF

td on
tr
td off
tf

Turn-on delay time

Turn-on rise time
Turn-off delay time
Turn-off fall time

VDD = 30 V; ID = 5 A;
VGS = 5 V; RG = 10 ;

11
38
25
20

17
60
38
38

ns
ns
ns
ns

MIN.

TYP.

MAX.

UNIT

Tj = 25C

REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS

Tj = -55 to 175C unless otherwise specified
SYMBOL

PARAMETER

CONDITIONS

IDR

Tsp = 25C

5.5

IDRM
VSD

Continuous reverse drain

current
Pulsed reverse drain current
Diode forward voltage

Tsp = 25C
IF = 2 A; VGS = 0 V

0.85

30
1.1

A
V

trr
Qrr

Reverse recovery time

Reverse recovery charge

IF = 2 A; -dIF/dt = 100 A/s;

VGS = -10 V; VR = 30 V

43
0.16

ns
C

February 1998

Rev 1.000

Philips Semiconductors

Product specification

TrenchMOS transistor
Logic level FET

BUK98150-55

AVALANCHE LIMITING VALUE

SYMBOL

PARAMETER

CONDITIONS

WDSS

Drain-source non-repetitive
unclamped inductive turn-off
energy

ID = 1.9 A; VDD 25 V;
VGS = 5 V; RGS = 50 ; Tsp = 25 C

120

MIN.

TYP.

MAX.

UNIT

15

mJ

Normalised Power Derating

PD%

BUKX8150-55

100

110

ID/A

100
90

tp =
RDS(ON) = VDS/ID
10

80
70

1 us
10 us

60
50

100 us

40

DC

1 ms

30
10 ms

20
10

100 ms

0
0

20

40

60

80
100
Tmb / C

120

0.1

140

55

Fig.3. Safe operating area. Tsp = 25 C

ID & IDM = f(VDS); IDM single pulse; parameter tp

Normalised Current Derating

ID%

10
VDS/V

Fig.1. Normalised power dissipation.

PD% = 100PD/PD 25 C = f(Tsp)

120

1E+02

BUKX8150-55

Zth / (K/W)

110
3E+01

100
90

1E+01

0.5

80
70

3E+00

60
50

1E+00

0.2
0.1
0.05

3E-01

0.02

40
30

1E-01

20
10

3E-02

0
0

20

40

60

80
Tmb / C

100

120

1E-02
1E-07

140

Fig.2. Normalised continuous drain current.

ID% = 100ID/ID 25 C = f(Tsp); conditions: VGS 5 V

February 1998

PD

tp

D=

0
T

1E-05

1E-03
t/s

1E-01

tp
T
t

1E+01

Fig.4. Transient thermal impedance.

Zth j-sp = f(t); parameter D = tp/T

Rev 1.000

Philips Semiconductors

Product specification

TrenchMOS transistor
Logic level FET

BUK98150-55

10
10
ID/A

4
3.8

gfs/S

VGS/V =
3.6

3.4
5

3.2
4

3.0

2.8
3

2.6
2.4

2.2
0

10

ID/A

Fig.5. Typical output characteristics, Tj = 25 C.

ID = f(VDS); parameter VGS
400 RDS(ON)mOhm

10

Fig.8. Typical transconductance, Tj = 25 C.

gfs = f(ID); conditions: VDS = 25 V

2.5

BUK98XX-55

Rds(on) normalised to 25degC

350

300
3.2
250

3.4

1.5

200

3.6

150

5
100
50

ID/A

10

0.5
-100

11

Fig.6. Typical on-state resistance, Tj = 25 C.

RDS(ON) = f(ID); parameter VGS

-50

50
Tmb / degC

100

150

200

Fig.9. Normalised drain-source on-state resistance.

a = RDS(ON)/RDS(ON)25 C = f(Tj); ID = 5 A; VGS = 5 V

10

2.5

ID/A

VGS(TO) / V

BUK98xx-55

max.
8

2
typ.

1.5

min.

0.5

2
Tj/C = 150
0

25

VGS/V

0
-100

Fig.7. Typical transfer characteristics.

ID = f(VGS) ; conditions: VDS = 25 V; parameter Tj

February 1998

-50

50
Tj / C

100

150

200

Fig.10. Gate threshold voltage.

VGS(TO) = f(Tj); conditions: ID = 1 mA; VDS = VGS

Rev 1.000

Philips Semiconductors

Product specification

TrenchMOS transistor
Logic level FET

BUK98150-55

10

Sub-Threshold Conduction

1E-01

IF/A
8

1E-02
2%

1E-03

typ

98%

Tj/C =

150

25

1E-04
2

1E-05
0

1E-05

0.5

1.5

2.5

0.2

0.4

0.6
0.8
VSDS/V

Fig.11. Sub-threshold drain current.

ID = f(VGS); conditions: Tj = 25 C; VDS = VGS

1.2

1.4

Fig.14. Typical reverse diode current.

IF = f(VSDS); conditions: VGS = 0 V; parameter Tj

600

120
110

500

WDSS%

100
90

400
pF

80
70
60

300

50
Ciss

40

200

30
20

100

10

0
0.01

Coss
Crss
0.1

VDS/V

10

0
20

100

Fig.12. Typical capacitances, Ciss, Coss, Crss.

C = f(VDS); conditions: VGS = 0 V; f = 1 MHz

40

60

80
100
Tmb / C

120

140

Fig.15. Normalised avalanche energy rating.

WDSS% = f(Tsp); conditions: ID = 1.9 A

6
VGS/V

VDD

L
4

VDS = 14V

VDS

VDS = 44V

VGS

-ID/100
0

RGS

T.U.T.

QG/nC

Fig.16. Avalanche energy test circuit.

WDSS = 0.5 LID2 BVDSS /(BVDSS VDD )

Fig.13. Typical turn-on gate-charge characteristics.

VGS = f(QG); conditions: ID = 5 A; parameter VDS

February 1998

R 01
shunt

Rev 1.000

Philips Semiconductors

Product specification

TrenchMOS transistor
Logic level FET

BUK98150-55

VDD

RD
VDS

VGS
RG

T.U.T.

Fig.17. Switching test circuit.

February 1998

Rev 1.000

Philips Semiconductors

Product specification

TrenchMOS transistor
Logic level FET

BUK98150-55

PRINTED CIRCUIT BOARD

Dimensions in mm.
36

18

60
4.5

4.6

10

7
15
50

Fig.18. PCB for thermal resistance and power rating for SOT223.
PCB: FR4 epoxy glass (1.6 mm thick), copper laminate (35 m thick).

February 1998

Rev 1.000

Philips Semiconductors

Product specification

TrenchMOS transistor
Logic level FET

BUK98150-55

MECHANICAL DATA
Dimensions in mm

6.7
6.3

Net Mass: 0.11 g

3.1
2.9

0.32
0.24

0.2

0.10
0.02

16
max

7.3
6.7

3.7
3.3
13

1
10
max
1.8
max

1.05

0.80

2.3

0.60

0.85
4.6

3
0.1 M

(4x)

Fig.19. SOT223 surface mounting package.

Notes
1. Observe the general handling precautions for electrostatic-discharge sensitive devices (ESDs) to prevent
damage to MOS gate oxide.
2. Refer to surface mounting instructions for SOT223 envelope.
3. Epoxy meets UL94 V0 at 1/8".

February 1998

Rev 1.000

Philips Semiconductors

Product specification

TrenchMOS transistor
Logic level FET

BUK98150-55

DEFINITIONS
Data sheet status
Objective specification

This data sheet contains target or goal specifications for product development.

Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification

This data sheet contains final product specifications.

Limiting values
Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and
operation of the device at these or at any other conditions above those given in the Characteristics sections of
this specification is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
Philips Electronics N.V. 1998
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the
copyright owner.
The information presented in this document does not form part of any quotation or contract, it is believed to be
accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any
consequence of its use. Publication thereof does not convey nor imply any license under patent or other
industrial or intellectual property rights.

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices or systems where malfunction of these
products can be reasonably expected to result in personal injury. Philips customers using or selling these products
for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting
from such improper use or sale.

February 1998

Rev 1.000