module counter(

clock,
//50MHz
slowclock,
//25MHz
reset,
enable,
counter_out,
coin,
led1,
//Rightmost 7-Segment
led2,
led3,
led4,
//Leftmost 7-Segment
green
//Time running out LED warning
);
input
input
input
input
input

clock;
slowclock;
enable;
reset;
coin;

output[9:0] counter_out;
output[7:0] green;
output [6:0] led1;
output [6:0] led2;
output [6:0] led3;
output [6:0] led4;
wire
wire
wire
wire
wire
reg
reg
reg
reg

slowclock;
clock;
reset;
enable;
coin;
clk_out;
clk_out2;
[9:0] counter_out;
[7:0] green;

integer i1=0;
always @(posedge clock)
begin
if(i1==50000000/2)
begin
clk_out<=~clk_out;
i1<=1'd1;
end
else
begin
i1<=i1+1'd1;
end
end
integer
integer
integer
integer
integer
integer
integer

i2;
minutes;
seconds;
onessec=0;
onesmin=0;
tenssec=0;
tensmins=0;

always @(posedge slowclock)

begin
if(counter_out >= 0 && counter_out < 11)
begin
if(i2==25000000/8)
begin
clk_out2<=~clk_out2;
i2<=1'd1;
end
else
begin
i2<=i2+1'd1;
end
end
/*

else if(counter_out > 0 && counter_out <= 5)

begin
if(i2==25000000/32)
begin
clk_out2<=~clk_out2;
i2<=1'd1;
end
else
begin
i2<=i2+1'd1;
end
end*/

/*

else
begin
if(i2 == 25000000/64)
begin
clk_out2 <=~ clk_out2;
i2 <= 1'd1;
end
else
begin
i2 <= i2+1'd1;
end
end
*/
end

always @(posedge clk_out2)

begin
if(counter_out > 0 && counter_out < 11)
begin
green =~ green;
end
else
begin
green = 8'b00000000;
end

end
always @(posedge clk_out)
begin
if (reset == 1'b0)
begin
counter_out = 10'b0000000000;
end
else
begin
if(enable == 1'b1)
begin
if(coin == 1'b0 && counter_out >= 0)
begin
counter_out = counter_out + 10'b00000011
11;
end
else if(coin == 1'b1 && counter_out > 0)
begin
counter_out = counter_out - 10'b00000000
01;
end
else
begin
counter_out = 0;
end
end
end
minutes = counter_out;
minutes = minutes / 60;
seconds = counter_out;
seconds = seconds % 60;
onesmin = minutes % 10;
tensmins = minutes / 10;
onessec = seconds%10;
tenssec = seconds/10;
end
bcd
bcd
bcd
bcd

b1(led1,onessec);
b2(led2,tenssec);
b3(led3,onesmin);
b4(led4,tensmins);

endmodule

module bcd(
display,time_input
);
input [4:0] time_input;
output reg [6:0]display;
always @*
case (time_input)
4'b0000 :

//Hexadecimal 0

display
4'b0001
display
4'b0010
display
4'b0011
display
4'b0100
display
4'b0101
display
4'b0110
display
4'b0111
display
4'b1000
display
4'b1001
display

=
:
=
:
=
:
=
:
=
:
=
:
=
:
=
:
=
:
=

endcase
endmodule

7'b1000000;
//Hexadecimal 1
7'b1111001 ;
// Hexadecimal 2
7'b0100100 ;
// Hexadecimal 3
7'b0110000 ;
// Hexadecimal 4
7'b0011001 ;
// Hexadecimal 5
7'b0010010 ;
// Hexadecimal 6
7'b0000011 ;
// Hexadecimal 7
7'b1111000;
//Hexadecimal 8
7'b0000000;
//Hexadecimal 9
7'b0011000 ;