4/9/2014

VLSI DESIGN
UNIT-1
LECTURE-3

nMOS Fabrication
also called Polysilicon gate self aligned nMOS fabrication process.
Fabrication process of nMOS is relevant to pMOS ,CMOS and BiCMOS
except a few additional processing steps.
1. Wafer(substrate)

Processing is carried out on thin wafer from single crystal silicon into
which p-type of impurities are introduced during crystal growth.
75 to 150mm diameter ,0.4 mm thick doped with 1015 to 1016/cm3.
Resistivity range between 25ohm to 2 ohm-cm

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2. A thick layer of field oxide of 1um

is grown over the substrate.
This field oxide acts as barrier to
dopants during processing.
Provides a general insulating layer over substrate over which other layers are
deposited and patterned. Wet oxidation is performed
Used for isolation of devices.
3. A polymer known as photoresist
is dropped over the surface &
spun so that it is Equally distributed.
The wafer is now heated so that Photoresist sticks to the substrate for further
processing

4. Photoresist layer is exposed to UV light

through a mask which defines the
active region of the transistor in which
source, drain implantations and channel
region are defined.
5.UV lights weakens the bonds of
photoresist and is removed and field
oxide is etched in the exposed
areas.

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6.Thin oxide (dry) is grown over the

Substrate which acts as the gate
Oxide for the transistor.
Polysilicon

is

deposited

using

CVD over the thin oxide and

patterned to form the gate .
7. Thin oxide is removed in the exposed
areas .Source and drain diffusion is
performed at high temperatures
By passing a gas containing dopants(eg Phosphine) over the substrate for
Phosphorus impurities .

Polysilicon gate and filed oxide acts as mask during diffusion process.

8.Thick oxide is grown over all again

and is masked with photoresist and
etched to expose selected areas of
polysilicon gate,source and drain
areas and contact holes are made.

9. The whole substrate is covered with

metal and masked so that it is selectively
etched to form contact areas at the
terminals of the transistor.

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CMOS Fabrication
P-well Process
N-well Process
Twin tub process
P-well Process
1. A Thick field oxide is grown over
the wafer. A P-well diffusion is
carried

out

in

the

n-type

substrate.
During P-well diffusion , care should be taken the doping concentration
and depth of well should not affect the threshold voltage and breakdown
voltages of the n-transistors. For Low threshold voltage deep wells are
required which increases spacing between NMOS and PMOS transistors.

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2.Active
pMOS

areas
devices

of

nMOS
are

and

defined

through lithography and etching.

A thin layer of gate oxide is
grown over the substrate.
A Layer of polysilicon is deposited over the surface and patterned to form
gate for both nMOS and pMOS devices.
3. The P-well is masked through P+
Mask during p type diffusion so that
It doesnt affect the characteristics of
nMOS transistors in it.

5. The PMOS transistors are masked through

P+ negative mask and N-type source and
Drain diffusions are carried out.

CMOS P-Well inverter showing VDD and VSS connections

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Summary of Processing steps

Mask 1- to form p-well the areas are defined by the mask at this level. nMOS
transistors are fabricated in p-well.
Mask 2- Thinox regions are defined using this mask. Thick oxide is removed
and a thin dry oxide (gate oxide) is grown and patterned.
Mask 3- Gate oxide is patterned in the previous step, now polysilicon is
deposited over the chip and patterned to form the gate areas in
both pMOS and nMOS device active areas.
Mask 4- using a P+ mask the nMOS active area(P-well) is covered and P type
diffusion is done in the remaining areas of the substrate to form
source and drain regions of pMOS transistors.

Mask 5- p- mask is used to cover the pMOS transistor active areas and n type
diffusion is performed through this mask to form source and drain areas
of the nMOS transistors in P-well.
Mask 6- Thick oxide is grown through out the chip and contact cuts are opened
through this mask.
Mask 7- Metal is deposited in the contact cuts and patterned through this mask.
Mask 8- A overall passivation layer (overglass) is deposited and openings for
bonding pads are patterned using this mask.
Remember thick field oxide is grown using wet oxidation while gate oxide is
grown through dry oxidation. Because it has to be pure and defect free. Field
oxide is used to separate the transistors, active areas and covering the chip after
all processing steps are completed. It serves as a protecting blanket layer..

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N-well process
N-well CMOS circuits are superior to p-well because of low substrate bias
effects on threshold voltage and lower parasitic capacitances associated
with source and drain regions.
Formation of N-well regions
Define nMOS and pMOS active regions
Field and gate oxidations
Form and pattern polysilicon
P+ diffusion

n+ diffusion
Contact cuts
Deposit and Patten metal contacts
Overglass with cuts for bonding pads

Berkely Nwell Fabrication Process

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Twin Tub Process

This technology provides the basis for separate optimization of the nMOS
and pMOS transistors, thus making it possible for threshold voltage, body
effect and the channel transconductance of both types of transistors to
be tuned independently.
The starting material is a n+ or p+ substrate, with a lightly doped epitaxial
layer on top. This epitaxial layer provides the actual substrate on which
the n-well and the p-well are formed.
Since two independent doping steps are performed for the creation of
the well regions, the dopant concentrations can be carefully optimized
to produce the desired device characteristics.

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In the conventional p & nwell CMOS process, the doping density of the
well region is typically about one order of magnitude higher than the substrate, which, among other effects, results in unbalanced drain parasitics.
The twin-tub process avoids this problem.

Twin tub based CMOS inverter

BiCMOS Technology
The limitations of MOS transistors is limited load driving capabilities.
Because of limited current sourcing and sinking of PMOS and NMOS
devices.
Hence Bipolar transistors near the outputs of the CMOS logic known as
BiCMOS technology serves the purpose of low power as well as high
fanout.
BJTs provide high gain and better noise and high frequency
characteristics than MOS transistors.
BiCMOS gates are used where speed as well as high driving capabilities
are required.(not always like ALU,ROM and a register file).

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Fabrication

of

CMOS

and

bipolar transistors need not be

carried out separately.
With few additional processing
steps of CMOS processing npn
transistors

with

good

performance characteristics can

be achieved.
Two additional layers needed
are n+ subcollector region and
P+ base layer.

The npn transistor is formed in a N-well and additional P+ base region is

located in the well to form the base region of the transistor.
The buried subcollector (BCCD)is added to reduce the N-well (collector)
resistance and improve the quality of the bipolar transistor.
Formation of two additional layers requires three additional processing
steps and masks
a) p+ base region.
b) n+ collector region.
c) The buried sub-collector

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Form N-well

N-well BiCMOS fabrication process steps

Form buried n+ layer.

Delineate active areas.

Channel stop implantation.
Form deep n+ collector
Threshold Voltage adjustment.
Delineate poly/gate areas.
Form n+ active areas.
Form p+ active areas.
Form p+ base for BJTs
Define contacts
Delineate the metal areas.