Over View of Combinational

Components

Encoders
An

encoder is a combinational logic circuit that essentially

performs a reverse decoder function.
An encoder accepts an active level on one of its inputs
representing a digit, such as a decimal or octal digit, and
converts it to a coded output, such as BCD or binary.
An encoder has 2n (or fewer) input lines and n output lines.
Encoders can also be devised to encode various symbols
and alphabetic characters.
The process of converting from familiar symbols or
numbers to a coded format is called encoding.
2

Octal-to-Binary Encoder
This encoder has eight inputs, one for each of the octal digits, and three outputs
that generate the corresponding binary number.
It is assumed that only one input has a value of 1 at any given time.

Octal-to-Binary Encoder
The encoder can be implemented with OR gates using inputs

determined directly from the truth table.

Output A0=1 if the input octal is 1 or 3 or 5 or 7.
Similar condition apply for the other two outputs.
These conditions can be expressed by the following Boolean output
functions.

A0 D1 D3 D5 D7

A1 D2 D3 D6 D7
A2 D4 D5 D6 D7
4

Octal-to-Binary Encoder
The encoder can be implemented with three 4-input OR gates.
The encoder just defined the limitation that only one input can be active any
;given time.
If two inputs are active simultaneously, the output produces an incorrect
combination.
For example, if D3 and D6 are 1 simultaneously, the output of the encoder will be
111 because all the three outputs are equal to 1.
This represents neither a binary 3 nor a binary 6.
To resolve this ambiguity, some encoder circuit must establish an input priority to
ensure that only ;one input is encoded.
If D3 and D6 are 1 at the same time, the output will be 110 because D6 has
higher priority than D3.
Another ambiguity in the octal-to-binary encoder is that an output of all 0s is
generated with all the inputs are 0, but this output is the same as when D0 is equal
to 1.
This discrepancy can be resolved by providing one more output to indicate
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that at least one input is equal to 1.

The 74148 Octal-to-Binary

Encoder
The 74148 is a priority encoder that has eight active-LOW inputs and three
active LOW binary outputs.
The device can be used for converting octal inputs to a 3-bit binary code.
To enable the device the EI(enable input) must be LOW.
It is also has the EO (enable output) and GS output for expansion purposes.
The EO is LOW when the EI is LOW and none of the input (0 through 7) is
active.
GS is low when EI is low and any of the inputs is active.
The 74148 can be expanded to a 16-line-to-4 line encoder by connecting the
EO of the higher-order encoder to the EI of the lower-order encoder and negativeORing the corresponding binary outputs.
This particular configuration produces active-HIGH outputs for the 4-bit binary
number.
6

The 74148 Octal-to-Binary

Encoder

Decimal-to-BCD Encoder
This type of encoder has ten inputs, one for each decimal digit, and four outputs
corresponding to the BCD code.
This is basic 10-line-to-4 line encoder.

10

Decimal-to-BCD Encoder
The BCD (8421) code is listed on the previous slide.

For instance, the most significant bit of the BCD code, A3, is a 1 for
decimal digit 8 or 9.
The OR expression for bit A3 in terms of the decimal digits can
therefore be written
A3 = 8 + 9
Bit A2 is a 1 for decimal digit 4,5,6 or 7 and can be expressed as an
OR function as A2 =4 + 5 + 6 + 7
Bit A1 is a 2 for decimal digit 2,3,6, or 7 and can be expressed as

A1= 1 + 3 + 5 + 7

Finally A0 is a 1 for digit 1,3,5,7, or 9. A0 = 1 +3 + 5 +7 + 9

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Decimal-to-BCD Encoder
When a HIGH appears on one of the decimal digit input lines, the appropriate
levels occur on the four BCD output lines.

For instance, if input line 9 is HIGH (assuming all other input lines are LOW), this
condition will produce a HIGH on outputs A0 and A3, which is the BCD code
(1001) for decimal 9.

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The 74LS147 Decimal-toBCD Encoder

The 74LS147 is a priority encoder with active-LOW inputs for decimal digits 1
through 9 and active-LOW BCD outputs as indicated in the logic symbol in the
following figure.
A BCD zero output is represented when none of the inputs is active.
The device pin number are in parentheses.

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An Encoder Application
A classical application example is a keyboard encoder.
The ten decimal digits on the keyboard of a computer, for example, must be
encoded for processing by the logic circuitry.
When one of the keys is pressed, the decimal digit is encoded to the
corresponding BCD code.
Keys are represented by 10 push buttons switches each with a pull-up resistor
to +V.
The pull-up resistor ensure that the line is HIGH when a key is not
depressed.
When a key is depressed, the line is connected to ground, and a LOW is
applied to the corresponding encoder input.
The zero key is not connected because the BCD output represents zero none
of the other key is depressed.
The BCD output of the encoder goes into a storage device, and each
successive BCD code is stored until the entire number has been entered.
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An Encoder Application

15

16

Multiplexers
A Multiplexers (MUX) is a device that allows digital information from
several sources to be routed onto a single line for transmission over that
line to a common destination.
The basic Multiplexers has several data-input lines and a single output line.
It also has data-select inputs, which permit digital data on any one of the
inputs to be switched to the output line.
Multiplexers are also known as data selectors.
Normally there are 2n input lines and n selection inputs whose bit
combinations determine which input is selected.
Each of the four inputs D0 through D3 is applied to one input of an AND gate.
Selection inputs S1 and S0 are decoded to select a particular AND gate.
The outputs of the AND gates are applied to a single OR gate to provide the
1-line output.

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Multiplexers
To visualize the operation of the circuit, consider the case when (S1, S0) = 10.
The AND gate associated with input D2 has two of its input equal to 1 and the
third input connected to D2.
The other three AND gates have at least one input equal to 0, which makes their
outputs equal to 0.
The OR gate output is now equal to the value of D2, providing a path form the
selected input to the output.
A multiplier is also called a data selector, since it selects one of many inputs and
steers the binary information to the output line.
The truth table row 00 D0 represents all rows in which (S1,S0)=00 and, for D0=1,
gives Y=1 and for D0=0, gives Y=0.
Since there are six variables, and only S1 and S0 are fixed, this single row
represents 16 rows of the corresponding full truth table.

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Multiplexers Truth Table

19

Multiplexers Logic

20

Multiplexers

The AND gates and inverters in the multiplexer resemble a decoder circuit and
indeed, they decode the selection input lines.
In general, a 2n-to-1 line multiplexer is constructed from an n-to-2n decoder by
adding 2n input lines to it, one from each data input.
The size of the mulitplexer is specified by the number 2n of its data input lines
and the single output line.
It is implied that the multiplexer contain n selection inputs.
The term multiplexer is often abbreviated as MUX.

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module mux3( select, d, q );

Mux

input[1:0] select;
input[3:0] d;
output q;
reg q;
wire[1:0] select;
wire[3:0] d;
always @( select or d )
begin
if( select == 0)
q = d[0];
if( select == 1)
q = d[1];
if( select == 2)
q = d[2];
if( select == 3)
q = d[3];
end

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endmodule

The 74157 Quadruple 2-Input

Data Selector/Multiplexer
The 74157, as well as its LS and CMOS versions, consists of four separate 2input mulitplexers.
Each of the four multiplexers shares a common data-select line and a common
enable.
Because there are only two inputs to be selected in each multipler, a single dataselect input is sufficient.
The data-select input is ANDed with the B input of each 2-input mulitplexer, and
the complement of data-select is ANDed with each A input.
A LOW on the Enable input allows the select input data to pass through to the
output.
A HIGH on the Enable input prevents data from going through to the output, that
is, it disables the mulitplexers.
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The ANSI/IEEE Logic Symbol

The ANSI/IEEE logic symbol for the 74157 is shown in the next figure.
The four multiplexers are indicated by the partitioned outline and that the input
common to all four multiplexers are indicated as inputs to the notched block at the
top, which is called the common control block.

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Mux to Implement Function

The

minterms of a function are generated in a multiplexer by

the circuit associated with the selection inputs.
The individual minterms can be selected by the data inputs.
This provides a method of implementing a Boolean function of
n variables with a multiplexer that has n-selection inputs and
2n data inputs, one for each minterms.
F of n inputs (where n is size of mux selector) is trivial
Just tie D lines to 1 or 0 appropriately.

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Function of n+1 Variables

Set input to one of 0,

1, Z, not_Z

26

Algorithm

Connect first n variables (2 here: X and

Y) to selector inputs
For each term decide whether output
dependent on last variable
If not, either 0 or 1
If so, Z or not_Z
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Four-Input Function with a

Multiplexer
The Boolean function is first listed in a truth table. The first n-1 variables in the
table are applied to the selection inputs of multiplexer.
For each combination of the selection variables, we evaluate the output as a
function of the last variables.
This function can be 0,1, the variable, or the complement of the variable.
These values are then applied to the data inputs in the proper order.
As an example, consider the implementation of the following Boolean function:

F(A,B,C,D) = m(1,3,4,11,12,13,14,15)

This function is implemented with a multiplexer with three selection inputs.

To correspond to the order of the variables in the associated truth table,
variables must be connected to selection inputs such that A,B and C correspond
to selection inputs S2,S1, and S0 respectively.
The values for the data inputs are determined from the truth table. The
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data line number is determined from the binary combinations of A,B, and C.

Four-Input Function with a

Multiplexer
For

example, when (A,B,C) = 101, the truth table shows that

F=D; so the input variable D is applied to data input 5.
The binary constants 0 and 1 correspond to two fixed signal
values.
Logic 1 and logic 0 are not appropriate schematic symbols,
for CMOS, or TTL-type integrated circuits, fixed logic 0
corresponds to signal ground, and fixed logic 1 is
equivalent to a +VDD or +VCC power signal.

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Example

30

DeMultiplexers
A demultiplexer (DEMUX) basically reverses the multiplexing function.
It takes data from one line and distribute them to a given number of output
lines.
OR
Demultiplexer receives information form a single line and transmits it to one of 2n
possible output lines.
Demultiplexer is also called data distributor.
Decoder can also be used as demultiplexer.
The selection of the specific output is controlled by the bit combination of n
selection lines.

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1-line-to-4-line Demultiplexer
The data-input lines goes to all of the AND gates.
The two data-select lines enable only one gate at a time, and the data
appearing on the data-input line will pass through the selected gate to the
associated data-output line.

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74154 as a Demulitplexer
74154 can also be used as a 4-lineto-16 line decoder.
This device and other decoders are
also used in demultiplexing applications.
In demultiplexer applications, the input
lines are used as the data-select lines.
One of the Enable inputs is used as
the data-input line, with the other Enable
input held LOW to enable the internal
negative-AND gate at the bottom of the
diagram.

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Demux is a Decoder

With an enable

34

Write complete process flow

for following take any suitable
size for practice

Decoder
Encoder
Mux
DeMux

35