FEATURES
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Part No.
Pin
Package
Operating
Temperature
Range
Part No.
Pin
Package
Operating
Temperature
Range
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PIN CONFIGURATION
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PIN DESCRIPTION
Pin Number
Pin Number
Symbol
Type
8
Description
No Connect.
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XR68C681
PIN DESCRIPTION (CONTD)
Pin Number
Pin Number
<
Symbol
Type
Description
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PIN DESCRIPTION (CONTD)
Pin Number
Pin Number
@
6
Symbol
Type
Description
,@
Output 7.
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XR68C681
PIN DESCRIPTION (CONTD)
Pin Number
Pin Number
11
1
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Symbol
Type
5
Description
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PIN DESCRIPTION (CONTD)
Pin Number
Pin Number
=
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Symbol
Type
Description
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Input 5. 0
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XR68C681
DC ELECTRICAL CHARACTERISTICS 1, 2, 3
Test Conditions: TA = 0 - 70C, VCC = 5V +5% unless otherwise specified.
Symbol
Parameter
Min
Typ
Max
Unit
;#:
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6
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Conditions
J 66 6
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Notes
1. Parameters are valid over the specified temperature and operating supply ranges. Typical values are 25C, V
CC = 5V and typical
processing parameters.
2. All voltages are referenced to ground (GND). For testing, input signal levels are 0.4V and 2.4V with a transition time of 20ns
maximum. All time measurements are referenced at input voltages of 0.8V and 2.0V as appropriate. See Figure 31.
3. For prime grade N, P, J, L, M, ML, V
CC = 5V + 10%
4. Measured operating with a 3.6864MHz crystal and with all outputs open.
<
XR68C681
AC ELECTRICAL CHARACTERISTICS 1, 2, 3
Test Conditions: TA = 0 - 70C, VCC = 5.0V +5% unless otherwise specified.
Symbol
Parameter
Min
Typ
Max
Unit
%
Read, Write and Interrupt Cycle Timing (Figure 33, Figure 34, Figure 35 )
9
A
A9
A($ =" 6
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Conditions
XR68C681
AC ELECTRICAL CHARACTERISTICS 1, 2, 3 (CONTD)
Test Conditions: TA = 0 - 70C, VCC = 5.0V +5% unless otherwise specified.
Symbol
Parameter
Min
Typ
Max
Unit
Conditions
5
$ 5
2!
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5
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2!
C
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5
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9G
9G
16
6
=
Notes
1. Parameters are valid over the specified temperature and operating supply ranges. Typical values are 25C, V
CC = 5V and typical
processing parameters.
2. All voltages are referenced to ground (GND). For testing, input signal levels are 0.4V and 2.4V with a transition time of 20ns
maximum. All time measurements are referenced at input voltages of 0.8V and 2.0V as appropriate. See Figure 31.
3. AC test conditions for outputs: CL = 50pF, RL = 2.7k to V .
CC
4. Consecutive write operations to the same register require at least three edges of the X1 clock between writes.
5. This specification imposes a 6 MHz maximum 68000 clock frequency if a read or write cycle follows immediately after the previous
read or write cycle. A higher 68000 clock can be used if this is not the case.
6. This specification imposes a lower bound on CS and IACK low, guaranteeing that they will be low for at least one CLK period.
7. This parameter is specified only to insure DTACK is asserted with respect to the rising edge of X1/CLK as shown in the timing diagram, not to guarantee operation of the part. If the specified setup time is violated, DTACK may be asserted as shown or may be
asserted one clock cycle later.
8. The minimum high time must be at least 1.5 times the X1/CLK period and the minimum low time must be at least equal to the X1/CLK
period if either channels Receiver is operating in external 1X clock mode.
Specifications are subject to change without notice
This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the Electrical Characteristics section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
2. This product includes circuitry specifically designed for the protection of its internal devices from damaging effects of excessive static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying any voltage larger than the rated
maximum.
XR68C681
A. DATA BUS BUFFER
SYSTEM DESCRIPTION
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Read Mode Registers
Address
(HEX)
Register Name
Symbol
Register Name
Symbol
%3$ #
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Table 1 (
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Bit 5
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Bit 2
Bit 1
Bit 0
Miscellaneous Commands
Enable/Disable Transmitter
Enable/Disable Receiver
(
- !
J 8
-
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!
J (% !
J 8 ;($
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-
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!
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Bit 7
Bit 6
Bit 5
Bit 4
Description
Null Command:
F%
(
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Reset Receiver: %% (
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Reserved
Reserved
Table 3. Miscellaneous Commands, Upper Nibble of all Command Registers, Unless Otherwise Specified.
6
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Description
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XR68C681
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Input Port
Change
Delta Break
B
RXRDY/
FFULLB
TXRDYB
Counter
Ready
Delta Break
A
RXRDY/
FFULLA
TXRDYA
J 8
J 8
J 8
J 8
J 8
J 8
J 8
J 8
J E%
J E%
J E%
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6
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where:
fSTS = The frequency of the selected timing source (See
Table 7)
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form
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form
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Bit 0
Table 8. Bit Format of the Clock Select Registers, CSRA and CSRB
Field
Bit Rate
CSR[7:4]
CSR[3:0]
X=0
X=1
X=0
X=1
6
@6
@6
6
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1=6
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Table 9. Bit Format of the Clock Select Registers CSR[3:0] and CSR[7:4]
XR68C681
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XR68C681
Received Data
Actual Data
1
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XR68C681
Example B: Programming the Bit Rate via the
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XR68C681
D.8 Explanation of Clock Timing Signals
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Table 11. The XR68C681 Data Sheet presents the following parameter specifications, in the
AC ELECTRICAL CHARACTERISTICS
tCLK - X1/CLK (External) High or Low Time
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%(-
($ 5.:7 (
% %($
(-
$ %%
fCLK - X1/CLK Crystal High or Low Time
(% %'(+(%
- + +C
'(%
(%%( 5.:7 (
" ( ( '&%
%'( ($ : (
%(-
+" %
'
& &
$ = 9G (% (
tRTX - RXC and TXC (External) High or Low Time via IP2, IP3, IP4 and IP5
16
(
% ( "
- ( (% % (%
(
(
#,
XR68C681
fRTX - RXC and TXC (External) Frequency - via IP2,
IP3, IP4, and IP5
E. INPUT PORT
& & %(-
( +C
'(% 9G (%
(
( %% (
( + % % 2! #+
% (% % % /5 ''3" .% '
& &
%(-
( +C
'(% 9G (
' (%
9G ''3 %(-
(% /5 %(-
" (% ( % (
!( ( + 63%
(
'
%$ % -
% (
'
-$ % % + %
(
% + %'( +
'(
% '
% +
(
% (%
' $ '
$ & , &
$(
- #, -(% + %% + #, #,6
(-
(
%(-
#,M
N (
%% (
-(' HI (
#,M
N ( %((
" ( (
#, -(% :(3(%" HI
(
%(-
#,
(
%% (
-(' HI (
#,M
N
( %((
" ( (
#, -(%
#
%&"
((
- '
'3 -(%
% ((& -
(&
& $
% $%(% ((
- '
'3 -(% %
''%% +(
- %'%4
1 $(++
%
$$ ( % ( *0
.(" (' '
'
+(-$ -
( % ('
( + *0
#
% ((
-
*'3 ( % (
(
% (' % % + !
''3 %(-
% -
'% (
1/
XR68C681
Input
Port
#,
Alternate Function(s)
4
$ (
+ '
#, '
-$ +
'(
%
(
& %(
-
M=N J $($ $(%'%%(
(% +
'(
" % % Section G.3
84 (% (
(%
'( :" + +
'(
#,
*4
$ (
+ '
*
#, '
-$ +
'(
% * (
& %(
- *M=N J $($ $(%'%%(
(% +
'(
" % % Section G.3
84 (% (
(%
'( : + +
'(
#,
D254
.( 2!
'3 #
#, '
-$ +
'(
% !
''3 (
+
.( & %(
-
M/4=N J
M" " N $($ $(%'%%(
(
++'
+ (% '(
% % Section D.2
5*4 2!
'3 (
+ '( '
*
#, '
% -$ +
'(
% !
''3 (
+ '( + '
* & %(
*M@4=N J M" " " N + /5 '3" *M@4=N
J M" " " N + 5 '3
#,1
5
4 2!
'3 (
+
%( '
#,1 '
-$ +
'(
% !
''3 (
+
%( + '
& %(
M14N J M" " " N + /5 '3"
M14N
J M" " " N + 5 '3
#,=
5
4 2!
'3 (
+ '( '
#,= '
-$ +
'(
% !
''3 (
+ '( + '
& %(
M@4=N J M" " " N + /5 '3"
M@4=N
J M" " " N + 5 '3
#,6
5*4 2!
'3 (
+
%( '
*
#,6 '
-$ +
'(
% !
''3 (
+
%( + '
* & %(
*M14N J M" " " N + /5 '3" *M14N
J M" " " N + 5 '3
Table 12. Listing of Alternate Function for the Input Port Pins
%C
&" #
,
+(-(
-(% (%
+
'(
& $(($ (
%'(
%4
% 3
'
-(' % + %
+ (
(
%
( + + #
,
+(-(
-(% (%
%
$ (
Table 13.
*(% @ =4 H
- (
:-(' I #$
(+('(
(%
*(% 1 4 '
% + #
,(
% #, #,1
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
#,1
#,
#,
#,
#,1
#,
#,
#,
J 8
J 8
J 8
J 8
J :
J :
J :
J :
J E%
J E%
J E%
J E%
J 9(-
J 9(-
J 9(-
J 9(-
Table 13. Bit Format of the Input Port Configuration Register (IPCR)
(+ $(%'%%(
+ ' (+($" ( (
(% -(% +%
1@
XR68C681
Bits 7 - 4: Change in Logic State Identification Bits
% (+($% H%
$I
$ '
$ & H
- + '%I % H
- +
'%I ($$ + (
(
% #, - #,1 #+ % H
- + '%I $' '
- (
-('
% (
& + % + (
(
%"
& ( ($
(+& H--(
-I (
& %(
- '%
$(
- HI (+($
( (
#, HI #+ H
- + '%I $
$' '
- + %" (' (
"
&
( +' (% & 3(
- '%
$(
- (+($% % HI
#
$%" (+ (
(
#,1 !(
'% '
- (
-(' %"
( @ ( '
(
-(' HI
Bits 3 - 0: The Current State of Input Pins IP0 - IP3
% (+($% H$
&I
$ +' '
-(' % #, - #,1 (
(
%
#
$
H#
,
- + I (
"
% $ +(
-
A( ( $
( +
( +% +
(% %
$ ,%
(' (%" ( (
-(%" % $$
( + #, ( (
$(' (' + + (
% (
% !(
'$ '
- + %
( + #, %
% %
% + % (
% +"
$(
- #," (
%
% H
- + I (
" , ( $(
4
(
(
% --$
+(
% + '
-(
- (
(
(
- # M@N
Bit 7
Bit 6
Bit 5
Bit 4
Bit3
Bit 2
Bit 1
Bit 0
BRG Set
Select
Delta IP3
Interrupt
Delta IP2
Interrupt
Delta IP1
Interrupt
Delta IP0
Interrupt
J
J
Table 7
J
J 8
J
J 8
J
J 8
J
J 8
1<
XR68C681
F. OUTPUT PORT
'
%(%% +
< (
'
%$ % -
%
'
%$ + ((
-
$ %% %(-
% &
(& -(
- + $ -(%%
"
*
$
" *
$ % '
+(-(
%
(
$ (" % + ,
$
'
%C
&" (
% (% '
$ &
H
$$%% (--$I '
$%
,-(
- (% ( $(++
+
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(
(% &(' $
% '('(& '
%(%% + ,
-(% ,"
$ (
% %%
'
% + , '
% + '
% + (
% !" (+ ( ,M6N
(% % -(' HI" (% ( % (
,6 (
(
-
-(' HI :(3(%" (+ ( ,M6N (% % -(' HI" (%
%% (
,6 (
(
- -(' HI (
3% -(
- ( $$ (%
'$
% % ''(% (% +
A
((
- (% "
% (
3
+ $$%% (--$ '
$%4 H2
, , *#I
$ H:2
, ,
*#I # (% (
(
3(
- H2
, , *#I '
$" % (% %(
-
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, 9" (% '(
%%
(
%(
- '%
$(
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%" -(' HIK
$ '
& (
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%
+ (
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H:2
, , *#I '
$ (%
(
3$" %'(+($ (%" ( (
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$(
- (
%
% -(' HI %
% + ' ( ( (
," +(
- ,
1
XR68C681
*%" @
(
,M@4N
$$%% 2
Figure 14. Illustration of the SET OUTPUT PORT BIT Command and its
Effect on the Output Port Register and the State of the Output Port Pins.
#
%&" + H2 , , *#I
'
$K
J K %% (
'
- + ,M
N"
(
,
J K %% (
,M
N J HI"
$ (
"
,
J HI
% + (
(%
'
-$
!4
% '
% + , -(%"
, J M" " " " " " " N
%C
&" % +
(
% 4
M,@" ,/" ,6" ,=" ,1" ," ," ,N J M" " " "
" " " N
=
XR68C681
*%" @
(
,M@4N
$$%%
Figure 15. Illustration of the CLEAR OUTPUT PORT BIT Command and its
Effect on the Output Port Register and the State of the Output Port Pins.
M,@" ,/" ,6" ,=" ,1" ," ," ,N J M" " " "
" " " N
#
%&" + H:2
, , *#I
'
$K
J " %% (
'
- + ,M
N
$
'
- (
=
+
'(
% Table 15 (%%
+
'(
%
+ ' + (
%
XR68C681
Output Port
Alternate Function(s)
,
RTSA: C%
$ + '
,
RTSB: C%
$ + '
,
TXCA_16X Output:
/5
%( '3 4
TXCA_1X Output:
5
%( '3
RXCA_1X: Output:
,1
TXCB_1X Output:
* 5
%( '3 4
RXCB_1X Output:
,=
RXRDY/FFULL_A Output:
,6
RXRDY/FFULL_B Output:
,/
TXRDY_A Output:
%( $& #
$(' (% (%
(
+
5ED
+
'(
,@
TXRDY_B Output:
*
%( $& #
$(' (% (%
(
+
5ED* +
'(
Table 15. Listing of the Alternate Functions for the Output Port
& +
'(
% + (% (
% %'$ & ((
- ( $ ,
( + + (% -(% +%
Bit 7
Bit 6
Bit 5
Bit 4
OP7
OP6
OP5
OP4
J ,M@N
J 5E*
J ,M/N
J 5E
J ,M6N
J 5E.
::*
Bit 3
Bit 2
OP3
J ,M=N
J 5E.
::
J ,M1N
J . P
J 5*5
J 5* 5
Bit 1
Bit 0
OP2
J ,MN
J 5
/5
J 5
5
J 5
5
Note:
OPCR only addresses the alternate functions for output port pins, OP7 - OP2. OP0 and OP1 assume their RTS roles if either
MR1n[7] = 1 or MR2n[5] = 1. Setting those mode register bits enables the RTS function. Otherwise, these two ports will only be
general purpose output ports.
+
'(%%
+$! %&
'
% '(
$
%(
'
% '
(
$
$
& %' ( (
+C
'& + *0" ."
!
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% (
- $ *%($%
$ (
=
(' '(
$
%( + ' '
(
$
$
&"
'
'
+(-$
(
(% (
- $%" (' %+ +
'
$ $(-
%('%" % % (
3
$ %$ + ($ ('(
%
XR68C681
#
(% %'(
'(
%&% ( %$ $
'(
%'% +
%(
$ '(
$+(
((
+ % + % %&% +%
5
%( ( +
5
%( '3 (-
+
5
'( ( #
+
5
'( '3 (-
+
(% %'(
+ $ % $(%'%%% %'%
( ' '
% %'%
(%$ 4
%(
%( 9$(
- -(%
$
%(
(+ -(%
'( '( 9$(
- -(%
$ '(
(+ -(%
% -(%
$ -(%
$ -(% Section B.2"
$
'$(
-
%( ''% $ + ,
$
'
% ( %( ( % ( (%
5
(
" $$(
- %" %
$ (
(& (% %
C($ & %&
'
% '
2'
%( '
%(%% +
%( (+ -(%
$
%( 9$(
- -(% 9 9
(% '& & # Figure 16 %
% %((+($
(%(
+
$ 9 , (
((%
%(%%(
+ %( $ & ((
- ' ' $
9 ' ' ( $$ (
$ '%%$
- # "
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-
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(
%( '3 + ((
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5
5
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-(
(
%( 9$(
-(%
Figure 16. A Simplified Drawing depicting the Transmit Shift Register and the Transmit Holding Register.
=1
XR68C681
A
%( (% ($ (
'(" 5
( '
(
%&
3(
- -(' H (- I 9" L% (
%(%%(
+ ' '"
%( %
'( & -
(
-
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%('& 5
--(
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+(
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+
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*(
5
*(
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C%
&(
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9
$ & + ' '% , '
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C% & ((
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& 9
%( '
$ $(%$ (
'
$ -(% % Table 2 (
Section B.2 #+
'
$ (% (%%$ $(%
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9
$ "
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- + (
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9
$ "
( & '& & +
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' '% '
(
9
' #
*:2
8#2 '
$ %
(%%$
==
%%
'" & # '( '(% $
5
(
" ( (% '%%$ -
+$%" $ (% '
$ +"
$ (%
%+$ 9 (% ' ' (%
'%%$
- 1 &% + #
' '($ ' '
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H$I $ &
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( $% 9 Figure 18 $('%
%((+($ $(
- + '(
XR68C681
'( '3 + ((
- *'3
#
'(
(
5
5
$ %
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-(%
'( +
'(
% & %
%(
- -
5
(
A
+
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%( (% ($" (% 5
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%C
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(
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+
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--(
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(' (% / (% $ ( /! ''3" (
% %(
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%
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(
(% %( HI + (% @ %"
=6
(% (
$ (& ' '3 (+
& % ($K
%''%%+ '(
+ ' ' (% %$K
$
'( ( %
%
$ %
''
' +
( +
! ' '
XR68C681
Receiver Errors
#+ '( $%
% H3I" %$
( + , (" (
- 2 2 (% +--$ &
%(
-"
M/N J #+"
' '(
+
' '" %%C
(& ' '3 (% (
''" ,(&
2 ,2 (% +--$ & %(
-
M6N J #+ 9 %
+"
$
' ' !(%$ (
K
$ (+
$
%
( '%
$(
- 5
(
K
' ' (
( (
"
$
H'(
2I 2 '
$((
( +--$ (
(%& %% (
%% + $
(
& (+ 5
(
(% $ %' '
$((
+
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$
, ( % $'$
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- %$ (
%'K '($
*3 '
$((
* (% %$ A
(% '
$((
(%
$'$ % (
-%
H'($ *3I '
$((
(% +--$ (
% -(%
M@N J
H*3I ' ' (% $$ (
9
9"
+ $ (% '($ $$ (
9
( 5
(
% H3I
'
$((
1 '%
$(
- H *3I (
(%
C%$ (+ -$
$ +--$ (
(
%% -(%
' 5
(
% H3I '
$((
"
%%C
' '% ( $$ (
9"
$
'%
$(
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'
$((
(
' -(
C%$ (+ -$
$ +--$ (
(
%% -(%
'
-$ -
(
C% , (+ 5E '( $&
:: # '
$((
!(%% + ( '
5E '
$((
!(%%
%
' ' +
$ !(%% ( (
9"
$ (% (& ((
-
H$I
$ $ & ,
:: '
$((
!(%%
9 (% '& +
$ '
''
&
' '% +
( , % $
H$I # % '
%' (
C% '' $ (
5E
:: '
$((
( '
%
$ *" %'(&
2' '
(% C($ (
% -(%%
%$ ($ '
$
((
- + %
'
( %'(
% + $ % 9" $($
$(%'%%(
+ (
$ + % -(%%
%
$ (
+(
- %'(
G.3 Mode Registers, MR1n and MR2n
$ -(%%" % %'(+& '
% .% $ (3 '
% -(%% % % '
+(-
'
%
-- (
$
$% 3(
'
(C% (% ( (
' + % -(%%
$(%'%%$
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Rx RTS
Control
Rx Interrupt
Select
Error Mode
Select
Parity Mode
J 8
J E%
J!E
J ::
J '
J *'3
J A( ,(&
J ' ,(&
J 8 ,(&
J ( $
Bit 2
Number of Bits
per Character
J 2
J $$
J 6
J /
J @
J <
Table 17. The Bit Format for Mode Registers MR1A and MR1B
=/
Bit 0
Parity Type
Select
Bit 1
XR68C681
+ ' '
(% ''%%$
'
F%
(
(
% (
(% %
&
$ 22 & H22 ,#82I
Bit 7
Bit 6
Bit 5
Bit 4
Channel Mode
Tx RTS
Control
CTS Enable
Tx
J 8
J
2'
J :' :
J :
J 8
J E%
J 8
J E%
'
$ (
3$ ( '
F% '
$ -(%
+
& $ ( " (
(
('& (
Bit 3
Bit 2
Bit 1
Bit 0
Bit Length
J 6/1
J /6
J /<<
1 J @6
= J <1
6 J <@6
/ J 1<
@ J
< J 6/1
J /6
J /<<
* J @6
J <1
J <@6
2 J 1<
J
Table 18. The Bit Format for Mode Registers MR2A and MR2B
MR1n[7] - Receiver Request to Send Control
$(
(&" C%
$ (% %%$
-$
& (
3(
- H2 , , *#
8I
H:2
, , *#
8I (
(
%
(% ( '
% (
+ # %% (%
,2" 2" '($ *3 +
#+ (% ( (% %
HI" (% (' '
( (
H 'I $ #+ (% (% (% % HI" (%
(' '
( (
H*'3I $
Figure 24 %
% $(- (' (%%
'('
$ C% %
$ '
+(-(
$
+
'(
MR1n[6] - Receiver Interrupt Select
(% ( %'% ( 5E %% ( ::
%% ( + '
$ #M6N + '
*
=@
#
' ' $ % %% (% &
&
' ' (% '
& + # #
'3 $" % (% %
'( -('
+ %% + ' '% '(
- +
# %(
' % H22 2
I '
$
+ '
% (%%$
MR1n[4:3] - Parity Mode Select
#+ HA#9 ,
#EI H 2 ,
#EI (
(%
-$" (& ( (% $$$
%($
' '%
$ '( +% (& ' '3
XR68C681
MR1n[2] - Parity Type Select
M=41N
+ ' '
(% ''%%$
'
F%
,(
(
%
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&
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'
(
+ + $%
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-
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$
&
Figure 19 %
% $(- $('(
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5
5
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5
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5
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<
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$ %
$ & ,
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XR68C681
(
-
M@4/N J '% '
(
(' ' $" (' ('&
%
(% '($ $ Figure 20 %
% $(
- $('(
- (' ' $ (
+(
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$((
% & ( (
(% $
F% 5
'( %
$
%(
$
$
5
5
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(
5
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5
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<
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''%%
%(
$ %
$ & ,
1 '
F% 5E
$ 52 %% (%
(
'(
@ , '( '
('(
% %
&"
,
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3 (% $(%$
=
2' '
'
'
+(-$ (
+
$(-
%(' $%
Local Loopback Mode
(% $ (% %'$ & %(
-
M@4/N J
Figure 21 (% $(- $('(
- ' '3 $
(
XR68C681
;
5
5
5
%( (+ -(%
%( 9$(
-(%
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-(%
<
<
$ %
$ & ,
#
(% $4
%( (% (
& '
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%( ''3 (% %$ + '(
= '
F% 5
(
(% (-
$
6
%( (%
$" '($
$
$
/ ,
%(
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('(
%
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(
&
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F% 5
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- (-
6
XR68C681
Remote Loopback Mode
(% $ (% %'$ & %(
-
M@4/N J Figure 22 %
% $(- $('(
- '3 $
(
5
5
#
'(
(
5
%( (+ -(%
5
-(
(
%( 9$(
-(%
'( 9$(
-(%
Note: The CPU has no access to the Serial Data during Remote Loopback Mode.
#
(% $4
'($ $ (%
%($
'
F% 5
'($ $ (%
%
,
$
%% '
$((
%
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8I (
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M6N J %
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- % (%
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Figure 26 %
% $(- (%
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$ C% %
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+(-(
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$
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(
#, + '
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$ ' ' #+
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(
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3(
%
$
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+
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$&$
(
-%
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(
6
XR68C681
( ' ' (% (
- %((G$ $
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Bit 6
Bit 5
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Bit 0
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Break
Framing
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Parity Error
Overrun
Error
TXEMT
TXRDY
FFULL
RXRDY
J 8
J E%
J 8
J E%
J 8
J E%
J 8
J E%
J 8
J E%
J 8
J E%
J 8
J E%
J 8
J E%
Table 19. The Bit Format of the Status Registers SRA and SRB
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H. SPECIAL MODES OF OPERATION
H.1.1 Receiver-Controlled RTS/CTS Handshaking
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Transmitting Device
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RTSA
(OP0)
IP2
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CTSA
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OP3
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TXDA
RXDB
TXRDY_A
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To CPU
TXRDY_A
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Figure 25. Block Diagram and Timing Sequence of Two DUARTs Connected
in the Transmitter-RTS Controlled Configuration.
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Figure 26. A Flow Diagram Depicting an Algorithm That Could be Used to Realize
the Transmitter-Controlled RTS/CTS Handshaking Mode
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Bit 7
Bit 6
Bit 5
Bit 3
Bit 2
Bit 1
Bit 0
Rx RTS
Control
Rx Int Select
Error Mode
Parity Select
Number of Bits/Char.
J 8
J E%
J5E
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J
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J A( ,(&
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Bit 5
Bit 4
Bit 3
Channel Mode
Tx RTS
Control
CTS Enable
Tx
J 8
J
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J 8
J E%
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Bit 2
Bit 1
Bit 0
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Bit 6
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%( '3 '
Table 6
Table 6
/
Bit 0
XR68C681
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
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Bit 1
Bit 0
Miscellaneous Commands
Enable / Disable
Transmitter
Enable / Disable
Receiver
! (
Section B.2
J 8
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Bit 6
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Bit 0
Received
Break
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Error
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Overrun
Error
TXEMT
TXRDY
FFULL
RXRDY
J 8
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J 8
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J 8
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Bit 0
Bit 6
Bit 5
Bit 4
Bit 3
OP7
OP6
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5
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5
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Bit 1
Bit 0
BRG Set
Select
Bit 7
Bit 6
Bit 5
Bit 4
Delta IP3
Interrupt
Delta IP2
Interrupt
Delta IP1
Interrupt
Delta IP0
Interrupt
J
J
Table 4
J
J 8
J
J 8
J
J 8
J
J 8
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Delta IP3
Delta IP2
Delta IP1
Delta IP0
IP3
IP2
IP1
IP0
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XR68C681
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
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Bit 1
Bit 0
Input Port
Change
Delta Break
B
RXRDY/
FFULLB
TXRDYB
Counter #1
Ready
Delta Break
A
RXRDY/
FFULLA
TXRDYA
J 8
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Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Input Port
Change
Delta Break
B
RXRDY/
FFULLB
TXRDYB
Counter #1
Ready
Delta Break
A
RXRDY/
FFULLA
TXRDYA
J ++
J
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J
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XR68C681
J. Timing Diagrams
;
=;
;
% :%
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<;
Note:
AC testing inputs are driven at 0.4V for a logic 0 and 2.4V for a logic 1 except for -40 to 85C and -55 to 125C, logic 1 shall be
2.6V. Timing measurements are made at 0.8V for a logic 0 and 2.0V for a logic 1.
22
2
//
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44 LEAD PLASTIC LEADED CHIP CARRIER
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Rev. 1.00
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40 LEAD CERAMIC DUAL-IN-LINE
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Rev. 1.00
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%
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(% (($
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