Current Mirrors: Fundamentals,

Topology, Head-Room Voltage, Output

Impedance, CommonMode Gain,
Active Current Mirrors
Dipankar Pal,
Dept. of EEE & EI,
BITS-Pilani, K. K. Birla Goa Campus

Current Mirrors
Recapitulation:

1. What is a current mirror?

2. Why a current mirror?

Ref: Behzad Razavi, Design of Analog Integrated Circuits

Current Mirrors
Recapitulation:

1. How?

VDD

IREF

I1

WR
LR

W1
L1

W1
1 1VDS1
L
I1 IREF 1
WR
1 R VDSR
LR

GND
Ref: Behzad Razavi, Design of Analog Integrated Circuits, and Giovanni Anelli, Basic Analog Design (CERN Technical Training 2005)

Inaccuracies in Copying Current

VDS (O/P) a source of error in small geometry!
Finite o/p resistance - another source of error!
I3

VDD

1. How to ensure VD1 = VD2

Solution:

VG3 to be chosen
so that VD1=VD2

IREF

VD3
VG3

W3
L3

VD1

VD2

W1
L1

W2
L2

GND
Ref: Behzard Razavi, Design of Analog Integrated Circuits, and Giovanni Anelli, Basic Analog Design (CERN Technical Training 2005)

Cascode Current Mirror

Stacking a diode connected MOS of

W/L of similar ration we get required
VG3.

VDD

IREF

I3

VD3
W4
L4 M4

Darin voltage effect desensitized by

V D 3

g m3 g mb3 .ro3

W3
M3L
3

VD1

VD2

W1
L1 M1

W2
M2L
2
GND

Ref: Behzard Razavi, Design of Analog Integrated Circuits, and Giovanni Anelli, Basic Analog Design (CERN Technical Training 2005)

Exercise
What is the maximum value of IREF if 0.5V is needed to drive
it?
VDD

Answer:
I REF max

n Cox VDD 0.5 VT 1 VT 4 2

2

L1
L4

W W
1
4

IREF

I3

VD3

W4
L4 M4

W3
M3L
3

VD1

VD2

W1
L1 M1

W2
M2L
2
GND

Ref: Behzad Razavi, Design of Analog Integrated Circuits; Figure : Giovanni Anelli, Basic Analog Design (CERN Technical Training 2005)

Head-Room voltage

IREF
Basic
Mirror

Voltage head for Cascode is: 2 Veff 1 Vt

This is higher by 1 Vt than the basic mirror with an active
load driven by a gate voltage Vb
Ref: Behzad Razavi, Design of Analog Integrated Circuits, Figure : Giovanni Anelli, Basic Analog Design (CERN Technical Training 2005)

Output Resistance

Ro r03 1 g m3 r02 r02

VDD

IREF

Much higher than simple current mirror

I3
VD3

W4
L4

W3
L3

VD1

VD2

W1
L1

W2
L2
GND

Makes it a current source

Ref: Behzad Razavi, Design of Analog Integrated Circuits; Figure : Giovanni Anelli, Basic Analog Design (CERN Technical Training 2005)

Active Current Mirror

Ref: Behzad Razavi, Design of Analog Integrated Circuits

Analysis
If
input NMOS have same transconductance
and - negligible

Av Gm Rout

Rout

is

of

where

I out Vin
g m1
1
Gm
.g m1 .

Vin 2
2
vin

Rout NMOS and RoutPMOS

1
M2 is degenerated by
of M1.
g m1

1
1
Rout NMOS 1 g m 2 .ro 2 .
ro 2 2.ro 2
and Rout PMOS ro 4
g m1
g m1

1
1
Rout ro 4 2ro 2

o 4 2ro 2 and 2 202 04

g
m1

Ref: Behzad Razavi, Design of Analog Integrated Circuits

Replacing CM by ro4
We can write

Vout VP Vout

Vin Vin VP
where

Req
VP

Vin R 1
eq
g m1

ro 2 ro 4
1
Req

1 g m 2 ro 2 g m 2

ro 4
1

ro 2

Ref: Behzad Razavi, Design of Analog Integrated Circuits

Analysis
Now

VP
Vin

is:

ro 4
1
ro 2
ro 4
2
ro 2

For calculating

Vout
VP

we use small signal

model of the circuit.

Vout 1 g m2 .ro 2 g m2 .ro 2

r
ro 2
VP
o2
1
1
ro 4
ro 4
Vout
Vin

ro 4
1
1
ro 2 g m 2 .ro 2

ro 4
ro 2
2
2
1
ro 2
ro 4

202 04
Ref: Behzad Razavi, Design of Analog Integrated Circuits

Combining Drain Currents to Boost Transconductance

Ref: Behzad Razavi, Design of Analog Integrated Circuits

Large Signal Analysis: Open Loop Issues

Ref: Behzad Razavi, Design of Analog Integrated Circuits

Small Signal Analysis

Av Gm Rout

Ref: Behzad Razavi, Design of Analog Integrated Circuits

Transconductance

ID1 = I D3 = ID4 = gm1,2 Vin / 2

I D2 = -gm1,2 Vin / 2

Iout = I D2 - I D4 = -gm1,2 Vin , Gm = gm1, 2

Ref: Behzad Razavi, Design of Analog Integrated Circuits

Output Resistance

VX
VX
IX = 2
+
2ro1, 2 + 1/ gm 3 ro4

Rout ro2 || ro4 , (2ro1,2 >> [1/ gm3] || ro3 )

Ref: Behzad Razavi, Design of Analog Integrated Circuits

Small Signal Gain

Av gm 1,2 (ro2 || ro4 )

Ref: Behzad Razavi, Design of Analog Integrated Circuits

Common Mode Gain

DVout
ACM =
DVin,CM
Ref: Behzad Razavi, Design of Analog Integrated Circuits

Gain Analysis & CMRR

1
ro3 ,4
||
2gm3, 4
2
gm1,2
-1
ACM
=
1
1 + 2gm1,2 RSS gm 3, 4
+ RSS
2gm1,2

= gm1,2 (ro1,2

ADM
CMRR =
ACM

gm 3,4 (1 + 2gm1,2 RSS )

|| ro3,4 )
gm1,2

= gm3,4 (ro1,2 || ro3,4 )(1 + 2gm1,2RSS )

Ref: Behzad Razavi, Design of Analog Integrated Circuits

OP-AMPS: Block View, Gain

Parameter and Frequency, Cascode,
Folded Cascode, 2-Stage Op-Amps,
Gain Boosting

Dipankar Pal,
Dept. of EEE & EI,
BITS-Pilani, K. K. Birla Goa Campus

Op-Amp: As a Block (contd.)

The circuit is designed for a nominal of 10, i.e., 1+R1/R2=10.
Determine the minimum value of A1 for a gain error of 1% or less.

Vout

Vin

A1
R1 R2
A1

R2
R2 R1 R2
1
A1
A1
R1 R2
R2
Ref: Behzad Razavi, Design of Analog Integrated Circuits

Op-Amp: As a Block
Vout R1 R1 R2 1
1 .1
.
Assuming A1>>10 we can approximate:
Vin R2
R2
A1
R1 R2 1
.
where the quantity
represents the gain error.
R2
A1
From above, it is clear that to have a gain error of 1% or less A1
should be 1000 or more.

Op-Amp Frequency Response: Block Perspective

Open-loop gain drops as frequency
goes up.
fu : unity-gain; f3-dB : 3-dB frequency
Ref: Behzad Razavi, Design of Analog Integrated Circuits

Frequency Response: Exercise

Assume the op amp is a single-pole
voltage amplifier. If Vin is a small
step, calculate the time required
for the output voltage to reach
within 1% of its final value. What
unity-gain bandwidth must the op
amp provide if 1+R1/R2 10 and the
settling time is to be less than 5ns.
For simplicity, assume the lowfrequency gain is much greater
than unity.
For a single-pole system

As

A0
s
1

R2
Vin Vout
. As Vout
R1 R2

Vout
As
s

R2
Vin
1
. As
R1 R2
where 0 is the 3dB

cut-off and

A0 .0

is the unity-gain bandwidth. It leads to (contd.)

Ref: Behzad Razavi, Design of Analog Integrated Circuits

Frequency Response: Exercise

A0
R2
1
. A0
Vout
A0
R1 R2
s

R
s
s
Vin
2
1
1
. A0
R1 R2
0

R2
1
. A0 .0
R1 R2

This indicates that the closed loop transfer function is a single pole
system with a time constant ( ) where:
1

R2
1
. A0 .0
R1 R2

R2
.A0 is >> 1, time constant ( )
Since low frequency loop gain
R1 R2
R1 1
becomes 1 .
R2 A00

Ref: Behzad Razavi, Design of Analog Integrated Circuits

Frequency Response: Exercise

The output step response for Vin au t can now be written as with
t

R1

Vout t a1 .1 e .u t
R2

R1
the final value VF a1 . For 1% settling Vout 0.99 VF . Thus
R2
t
1%

1 e
0.99 t1% ln100 4.6

For 1% settling time of 5ns, 1.09ns . We also get:

R1
A00 1 / 9.21Grad / s1.47Ghz
R2
Ref: Behzad Razavi, Design of Analog Integrated Circuits

Op-Amp: Open Loop Topology

Small Signal Open Loop Gain at Low Frequency ( Av )

RoN RoP

Av g mN
RoN RoP
Ref: Behzad Razavi, Design of Analog Integrated Circuits

Op-Amp Voltage Follower: Closed Loop (feed back)

Assume all the overdrives are

0.3 V and the VT = 0.7 V

for both NMOS and PMOS.

Vin(min) VGS1 + over-drive for current source
= VGS1+0.3=(0.3+VT)+0.3=0.3+0.3+0.7=1.3V
Vin(max) when M1 on triode-border = VDD-mod(VGS3)+VT= 3-(0.3+0.7)
+0.7=2.7V
Rout

Rout ( open )
1 . Av

Rout ( open )
1 g mN .Rout ( open )

Rout ( open )
g mN .Rout ( open )

1
g mN

Ref: Behzad Razavi, Design of Analog Integrated Circuits

Telescopic Cascode Op-Amp: For High Gain

Av g mN . g mN r 2 oN

2
r
oP
mP

Drawback - Output swing is limited to:

2.VDD VODM 1 VODM 3 VCSS VODM 5 VODM 7 where

subscript

OD denote overdrive.
Ref: Behzad Razavi, Design of Analog Integrated Circuits

Other Drawback in Telescopic Cascode Op-Amp

Shorting output to input to design unity gain buffer requires
output to be within a maximum and minimum value.
Condition for M2 to be
in saturation limits:
Vout VX VTH 2

Again for M4 to be in saturation:

Vout Vb VTH 4

Thus we get
Vb VTH 4 Vout V X VTH 2 Vb VTH 4 Vout Vb VGS 4 VTH 2

(substituting VX Vb VGS 4 )
Ref: Behzad Razavi, Design of Analog Integrated Circuits

Telescopic Cascode Op-Amp (contd.)

The range (=Vout-Max-Vout-Min) is:
Vout range VTH 4 VTH 2 VGS 4

This can be maximized by

reducing overdrive of M4.

Ref: Behzad Razavi, Design of Analog Integrated Circuits

Telescopic Cascode Op-Amp: Design Exercise

Specification:
VDD=3
V,
differential output swing = 3V,
power dissipation = 10mW,
voltage gain = 2000. Given
nCox=60 A/V2, pCox=30A/V2,
n=0.1V-1, p=0.2V-1 (for an
effective channel length of 0.5
m), =0, VTHN= |VTHP|=0.7 V

Ref: Behzad Razavi, Design of Analog Integrated Circuits

Telescopic Cascode: Design Exercise (Contd.)

Power budget: Itotal= 3.330 mA. Hence: IM9 = 3 mA, IMb1 + IMb2 =
330 A (apportioned on estimated drain current need)

Output swing:
Node X(Y) swing=1.5 V,
M3-M6 in saturation
|VOD7|+|VOD5|+VOD3+VOD1+VOD9=1.5 V
Since M9 carrying largest current, VOD90.5 V (chosen)
Since M5-M8 suffer from low mobility, |VOD5|=|V|0.3 V,
VOD1=VOD3 0.2 V (chosen)
W/L: From ID=(1/2)Cox(W/L)(VGSVTH)2 and using minimum
length (0.5m) for all MOS to minimize capacitances.
(W/L)14=1250, (W/L)58=1111, (W/L)9=400
Ref: Behzad Razavi, Design of Analog Integrated Circuits

Telescopic Cascode: Design Exercise (Contd.)

Gain: Av gm1[(gm3ro3r)|| (gm5ro5ro7)]. Since 1/L.
We can therefore increase the
nCoxWI D 1
WL width or length
g m .ro
.

L
I D
ID
Modulation:
Since M1~M4 appear in signal path for keeping minimum
capacitance, we double the width and length of M5~M8 to
increase
ro
(gm
remains
constant).
Choosing
(W/L)58=1111m/1m Av 4000
CM level: Minimum allowable input CM level=VGS1+VOD9 =1.4 V.

Bias:

Vb1, min=VGS3+VOD1+VOD9=1.6V;
Vb2, max=VDD(|VGS5|+|VOD7|)=1.7V
Ref: Behzad Razavi, Design of Analog Integrated Circuits

Folded Cascode Fundamentals

Genesis of Folded
Cascode Topolgy

Ref: Behzad Razavi, Design of Analog Integrated Circuits

Folded Cascode Topology

In left, ISS carries currents of both channels of cascode stage. In right,

input pair requires an additional bias current ISS1 = (ISS/2)+ID3.
Folded topology consumes more power.
Input common mode (CM): Vin in Telescopic Cascode cannot be higher
than Vb1-VGS3+VTH1. The same for Folded Cascode cannot be less than
Vb1-VGS3+|VTHP|.
Substrates can be connected to VSS for M1(2).
Ref: Behzad Razavi, Design of Analog Integrated Circuits

Folded Cascode Op-Amp Implementation

Current implementation: Current sources
of original folded cascade are replaced by
M5~M10.
Maximum output swing: Proper
choice of Vb1 and Vb2 gives
VDD-VOD3-VOD5-|VOD7|-|VOD9|
as peak-to-peak swing on
each side.
Improvement: The swing is
larger in folded cascode.

Note: M5 and M6 may require high overdrive to minimize their

capacitance-contribution to nodes X and Y.
Ref: Behzad Razavi, Design of Analog Integrated Circuits

Folded Cascode Op-Amp Topology

Ref: Behzad Razavi, Design of Analog Integrated Circuits

Gain Estimation: Folded Cascode Op-Amp

Rop g m 7 g mb 7 .ro 7 .ro 9

Since (gm3+gmb3)1||ro3 << ro1||ro5;

Rout Rop

m3

g mb 3 .ro 3 .ro1 ro 5

Iout ID1 Gm gm1; Av=Gm.Rout

Av g m1 .g m3 g mb 3 .ro 3 ro1 ro 5

g m7 g mb7 .ro7 .ro9

Ref: Behzad Razavi, Design of Analog Integrated Circuits

Telescopic Cascode & Folded Cascode: Comparison

For comparable dimensions, PMOS has a lower gm. Further in

Folded Cascode ro1 and ro5 comes in parallel at output resistance,
making the gain 2/3 times lower than Telescopic Cascode.

Folded Cascode consumes more power.

It has a pole at folding point which is closer to origin (due to

added capacitances: Ctot= CGS3+CSB3+CDB1+CGD1+(CGD5+CDB5) - higher
than Telescopic Cascode by CGD5+CDB5.
Ref: Behzad Razavi, Design of Analog Integrated Circuits

Folded Cascode: NMOS Input Stage

Has higher gain at the cost of poles at folding point closer to origin.
Ref: Behzad Razavi, Design of Analog Integrated Circuits

Single Ended Output: Telescopic Cascode Topology

VX=VDD|VGS5| |VGS7|, limits maximum value of Vout to VDD

|VGS5| |VGS7| |VTH6|and wastes one PMOS threshold voltage in
the swing
To solve this M7 and M8 are biased at the edge of triode region
Disadvantages
- it provides only half the output voltage swing
- it contains a mirror pole at node X
Ref: Behzad Razavi, Design of Analog Integrated Circuits

Single Stage Vs. Two Stage Op-Amp

Op-Amps seen so far make small signal input-current to flow
directly through output resistance. They are single stage op-amps.
There gain is obtained by multiplying transconductance with output
resistance.
Gain can be increased by cascoding at the cost of output swing.
Where gain and output swing are both desirable, the stage giving
high gain and the one giving high output swing are isolated to
design a two stage op-amp.

Ref: Behzad Razavi, Design of Analog Integrated Circuits

Two Stage Op-Amp

First (gain) stage can be any of the topologies discussed so far.
2nd stage usually is a CS-stage which gives high output swing

Overall Gain: Gain 1st Stage

(Av1) Gain 2nd Stage ( Av 2)
Av1 g m1 .ro1 ro 3 g m 2 .ro 2 ro 4

Av 2 g m 5 .ro 5 ro 7 g m 6 .ro 6 ro8

Output swing: VDD- |VOD5(6)|
-VOD7(8)

Ref: Behzad Razavi, Design of Analog Integrated Circuits

Two Stage Cascode Op-Amp (for increased gain)

Av g m1, 2 .g m 3, 4 g mb 3, 4 .rO 3, 4 .rO1, 2

m 9 ,10

.rO 9,10 rO11,12

m5 ,6

g mb 5, 6 .rO 5 ,O 6 .rO 7 ,O8

Ref: Behzad Razavi, Design of Analog Integrated Circuits and Ching Y. Yang, Dept. of EE, National Chung Hsing University

Two Stage Op-Amp with Single Ended Output

Ref: Behzad Razavi, Design of Analog Integrated Circuits and Ching Y. Yang, Dept. of EE, National Chung Hsing University

Single Stage Op-Amp with Gain Booster

Rout g m 2 .rO 2 .rO1

Rout A1 g m 2 .rO 2 .rO1

Increasing impedance by feedback. Rout 1 g m 2 g mb 2 .rO 2 .rO1 rO 2

Assuming g m .rO 1 we get Rout g m 2 g mb 2 .rO 2 .rO1

If we ignore body-effect then Rout A1 g m 2 .rO 2 .rO1

Ref: Behzad Razavi, Design of Analog Integrated Circuits and Ching Y. Yang, Dept. of EE, National Chung Hsing University

Gain Boosting in Cascode State (Regulated Cascode)

Drawback:

Av g m1 g m 2 .rO 2 .rO1
. g m 3 .rO 3

Since VX = VGS, the minimum Vout = VGS3+VOD2 is higher (in a simple

cascode with proper choice of VG2 it would be VOD1+VOD2)
Ref: Behzad Razavi, Design of Analog Integrated Circuits and Ching Y. Yang, Dept. of EE, National Chung Hsing University