4-BIT BIDIRECTIONAL
UNIVERSAL SHIFT REGISTER
The SN54 / 74LS194A is a High Speed 4-Bit Bidirectional Universal Shift
Register. As a high speed multifunctional sequential building block, it is useful
in a wide variety of applications. It may be used in serial-serial, shift left, shift
right, serial-parallel, parallel-serial, and parallel-parallel data register transfers. The LS194A is similar in operation to the LS195A Universal Shift
Register, with added features of shift left without external connections and
hold (do nothing) modes of operation. It utilizes the Schottky diode clamped
process to achieve high speeds and is fully compatible with all Motorola TTL
families.
4-BIT BIDIRECTIONAL
UNIVERSAL SHIFT REGISTER
LOW POWER SCHOTTKY
J SUFFIX
CERAMIC
CASE 620-09
16
1
N SUFFIX
PLASTIC
CASE 648-08
Q0
Q1
Q2
Q3
CP
S1
S0
16
15
14
13
12
11
10
16
1
16
1
MR
DSR
P0
P1
P2
P3
DSL GND
ORDERING INFORMATION
SN54LSXXXJ
SN74LSXXXN
SN74LSXXXD
PIN NAMES
LOADING (Note a)
LOW
HIGH
S0, S1
P0 P3
DSR
DSL
CP
MR
Q0 Q3
D SUFFIX
SOIC
CASE 751B-03
0.5 U.L.
0.5 U.L.
0.5 U.L.
0.5 U.L.
0.5 U.L.
0.5 U.L.
10 U.L.
0.25 U.L.
0.25 U.L.
0.25 U.L.
0.25 U.L.
0.25 U.L.
0.25 U.L.
5 (2.5) U.L.
NOTES:
a. 1 TTL Unit Load (U.L.) = 40 A HIGH/1.6 mA LOW.
b. The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74)
b. Temperature Ranges.
Ceramic
Plastic
SOIC
SN54/74LS194A
LOGIC DIAGRAM
P0
10
P1
S1
P2
P3
S0
2
DSR
VCC = PIN 16
GND = PIN 8
= PIN NUMBERS
CP
Q0
Q1
Q2
DSL
Q3
CP
CP
CP
CP
R
CLEAR
R
CLEAR
R
CLEAR
R
CLEAR
11
1
MR
15
14
Q0
12
13
Q2
Q1
Q3
FUNCTIONAL DESCRIPTION
The Logic Diagram and Truth Table indicate the functional
characteristics of the LS194A 4-Bit Bidirectional Shift Register. The LS194A is similar in operation to the Motorola LS195A
Universal Shift Register when used in serial or parallel data
register transfers. Some of the common features of the two
devices are described below:
All data and mode control inputs are edge-triggered,
responding only to the LOW to HIGH transition of the Clock
(CP). The only timing restriction, therefore, is that the mode
control and selected data inputs must be stable one set-up
time prior to the positive transition of the clock pulse.
The register is fully synchronous, with all operations taking
place in less than 15 ns (typical) making the device especially
useful for implementing very high speed CPUs, or the memory
buffer registers.
The four parallel data inputs (P0, P1, P2, P3) are D-type
inputs. When both S0 and S1 are HIGH, the data appearing on
P0, P1, P2, and P3 inputs is transferred to the Q0, Q1, Q2, and
INPUTS
MR
OUTPUTS
S0
X
DSL
Q1
Q2
Pn
X
Q0
S1
X
DSR
Reset
Q3
L
Hold
Shift Left
H
H
h
h
I
I
X
X
I
h
X
X
q0
q1
q1
q1
q2
q2
q2
q3
q3
q3
L
H
Shift Right
H
H
I
I
h
h
I
h
X
X
X
X
L
H
q0
q0
q1
q1
q2
q2
Parallel Load
Pn
P0
P1
P2
P3
SN54/74LS194A
GUARANTEED OPERATING RANGES
Symbol
Parameter
Min
Typ
Max
Unit
VCC
Supply Voltage
54
74
4.5
4.75
5.0
5.0
5.5
5.25
TA
54
74
55
0
25
25
125
70
IOH
54, 74
0.4
mA
IOL
54
74
4.0
8.0
mA
Min
P
Parameter
VIH
VIL
VIK
VOH
VOL
IIH
IIL
IOS
ICC
Typ
Max
U i
Unit
2.0
54
0.7
74
0.8
0.65
1.5
T
Test
C
Conditions
di i
Guaranteed Input
p LOW Voltage
g for
All Inputs
54
2.5
3.5
74
2.7
3.5
54, 74
0.25
0.4
IOL = 4.0 mA
74
0.35
0.5
IOL = 8.0 mA
20
0.1
mA
0.4
mA
100
mA
VCC = MAX
23
mA
VCC = MAX
20
Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.
P
Parameter
Min
Typ
25
36
Max
U i
Unit
fMAX
tPLH
tPHL
Propagation Delay,
Clock to Output
14
17
22
26
ns
tPHL
Propagation Delay,
MR to Output
19
30
ns
MHz
T
Test
C
Conditions
di i
VCC = 5.0
50V
CL = 15 pF
SN54/74LS194A
AC SETUP REQUIREMENTS (TA = 25C)
Limits
S b l
Symbol
P
Parameter
Min
Typ
U i
Unit
Max
tW
20
ns
ts
30
ns
ts
20
ns
th
ns
trec
Recovery Time
25
ns
T
Test
C
Conditions
di i
VCC = 5.0
50V
DEFINITIONS OF TERMS
SETUP TIME(ts) is defined as the minimum time required
for the correct logic level to be present at the logic input prior
to the clock transition from LOW to HIGH in order to be
recognized and transferred to the outputs.
AC WAVEFORMS
The shaded areas indicate when the input is permitted to change for predictable output performance.
1/fmax
S0
1.3 V
CLOCK
S1
tW
tPHL
OUTPUT
( IS SHIFT LEFT)
1.3 V
tPLH
1.3 V
1.3 V
1.3 V
DSR DSL
ts(L)
th(L) = 0
OTHER CONDITIONS: S1 = L, MR = H, S0 = H
P0 P1 P2 P3
ts(L)
th(L) = 0
CLOCK
OUTPUT*
MR
ts(H)
th(H) = 0
1.3 V
1.3 V
OTHER CONDITIONS: MR = H
OTHER CONDITIONS: *DSR SET-UP TIME AFFECTS Q0 ONLY
OTHER CONDITIONS: DSL SET-UP TIME AFFECTS Q3 ONLY
1.3 V
trec
tW
ts(H)
th(H) = 0
Figure 3. Setup (ts) and Hold (th) Time for Serial Data
(DSR, DSL) and Parallel Data (P0, P1, P2, P3)
1.3 V
CLOCK
tPHL
OUTPUT
(STABLE TIME)
1.3 V
1.3 V
S0 S1
ts
th = 0
CLOCK
ts
th = 0
1.3 V
1.3 V
OTHER CONDITIONS: MR = H