Inside the 8086 Central Processor Unit (CPU)

GENERAL PURPOSE REGISTERS

8086 CPU has 8 general purpose registers, each register has its own name:

AX - the accumulator register (divided into AH / AL):

o Generates shortest machine code
o Arithmetic, logic and data transfer
o One number must be in AL or AX
o Multiplication & Division
o Input & Output

BX - the base address register (divided into BH / BL).

CX - the count register (divided into CH / CL):

o Iterative code segments using the LOOP instruction
o Repetitive operations on strings with the REP command
o Count (in CL) of bits to shift and rotate

DX - the data register (divided into DH / DL):

o DX:AX series into 32-bit register for some MUL and DIV operations
o Specifying ports in some IN and OUT operations

SI - source index register:

o Can be used for pointer addressing of data

o Used as source in some string processing instructions

o Offset address relative to DS

DI - destination index register:

o Can be used for pointer addressing of data
o Used as destination in some string processing instructions
o Offset address relative to ES

BP - base pointer:
o Primarily used to access parameters passed via the stack
o Offset address relative to SS

SP - stack pointer:
o Always points to top item on the stack
o Offset address relative to SS
o Always points to word (byte at even address)
o An empty stack will had SP = FFFEh

SEGMENT REGISTERS

CS - points at the segment containing the current program.

DS - generally points at segment where variables are defined.

ES - extra segment register, it's up to a coder to define its usage.

SS - points at the segment containing the stack.

Although it is possible to store any data in the segment registers, this is never a good idea.
The segment registers have a very special purpose - pointing at accessible blocks of memory.

Segment registers work together with general purpose register to access any memory value.
For example if we would like to access memory at the physical
address 12345h (hexadecimal), we should set the DS = 1230h and SI = 0045h. This is good,
since this way we can access much more memory than with a single register that is limited to
16 bit values.
CPU makes a calculation of physical address by multiplying the segment register by 10h and
adding general purpose register to it(1230h * 10h + 45h = 12345h):

The address formed with 2 registers is called an effective address.

By default BX, SI and DI registers work with DS segment register;
BP and SP work with SS segment register.
Other general purpose registers cannot form an effective address!
Also, although BX can form an effective address, BH and BL cannot!
SPECIAL PURPOSE REGISTERS

IP - the instruction pointer:

o Always points to next instruction to be executed
o Offset address relative to CS

IP register always works together with CS segment register and it points to currently
executing instruction.
FLAGS REGISTER

Flags Register - determines the current state of the processor.

Flags Register is modified automatically by CPU after mathematical operations, this allows
to determine the type of the result, and to determine conditions to transfer control to other
parts of the program.
Generally you cannot access these registers directly.

Carry Flag (CF) - this flag is set to 1 when there is an unsigned overflow. For
example when you add bytes 255 + 1(result is not in range 0...255). When there is no
overflow this flag is set to 0.

Parity Flag (PF) - this flag is set to 1 when there is even number of one bits in result,
and to 0 when there is odd number of one bits. Even if result is a word only 8 low bits
are analyzed!

Auxiliary Flag (AF) - set to 1 when there is an unsigned overflow for low nibble (4
bits).

Zero Flag (ZF) - set to 1 when result is zero. For none zero result this flag is set to 0.

Sign Flag (SF) - set to 1 when result is negative. When result is positive it is set to 0.
Actually this flag take the value of the most significant bit.

Trap Flag (TF) - Used for on-chip debugging.

Interrupt enable Flag (IF) - when this flag is set to 1 CPU reacts to interrupts from
external devices.

Direction Flag (DF) - this flag is used by some instructions to process data chains,
when this flag is set to 0 - the processing is done forward, when this flag is set to 1 the
processing is done backward.

Overflow Flag (OF) - set to 1 when there is a signed overflow. For example, when
you add bytes 100 + 50 (result is not in range -128...127).

Registers are the most important components of CPU. Each register

performs a specific function. A brief description of most important CPU's
registers and their functions are given below:
1. Memory Address Register (MAR):
This register holds the address of memory where CPU wants to read or
write data. When CPU wants to store some data in the memory or reads
the data from the memory, it places the address of the required memory
location in the MAR.
2. Memory Buffer Register (MBR):
This register holds the contents of data or instruction read from, or written
in memory. The contents of instruction placed in this register are
transferred to the Instruction Register, while the contents of data are
transferred to the accumulator or I/O register.
In other words you can say that this register is used to store
data/instruction coming from the memory or going to the memory.
3. I/O Address Register (I/O AR):
I/O Address register is used to specify the address of a particular I/O
device.
4. I/O Buffer Register (I/O I3R):
I/O Buffer Register is used for exchanging data between the I/O module
and the processor.
5. Program Counter (PC)
Program Counter register is also known as Instruction Pointer Register.
This register is used to store the address of the next instruction to be
fetched for execution. When the instruction is fetched, the value of IP is
incremented. Thus this register always points or holds the address of next
instruction to be fetched.

6. Instruction Register (IR):

Once an instruction is fetched from main memory, it is stored in the
Instruction Register. The control unit takes instruction from this register,
decodes and executes it by sending signals to the appropriate component
of computer to carry out the task.
7. Accumulator Register:
The accumulator register is located inside the ALU, It is used during
arithmetic & logical operations of ALU. The control unit stores data values
fetched from main memory in the accumulator for arithmetic or logical
operation. This register holds the initial data to be operated upon, the
intermediate results, and the final result of operation. The final result is
transferred to main memory through MBR.
8. Stack Control Register:
A stack represents a set of memory blocks; the data is stored in and
retrieved from these blocks in an order, i.e. First In and Last Out (FILO).
The Stack Control Register is used to manage the stacks in memory. The
size of this register is 2 or 4 bytes.
9. Flag Register:
The Flag register is used to indicate occurrence of a certain condition during an operation of
the CPU. It is a special purpose register with size
one byte or two bytes. Each bit of the flag register constitutes a flag (or
alarm), such that the bit value indicates if a specified condition was
encountered while executing an instruction.
For example, if zero value is put into an arithmetic register (accumulator)
as a result of an arithmetic operation or a comparison, then the zero flag
will be raised by the CPU. Thus, the subsequent instruction can check
this flag and when a zero flag is "ON" it can take, an appropriate route in
the algorithm.
Registers used in 8085 Microprocessor and their details
Registers Used(
1) Simple register (main register)
(2)General purpose register
(3)Special function register
(4)Other register
1)Simple registers
a) Accumulator
(A) 8 bit
(B) Used as a register for storing one data when two are arithmetically and logically
operated .
(C) after ALU operation result is also stored in accumulator.
(D) when single no is to be logically operated only accumulator is used as a storage as well as
storing
result after execution.
2) General purpose register(
A)B,C,D,E,H &L are used as general purpose register.
(B) Each 8 bit long .
(C)Pairing can also be done in a standard way to stored 16 bit data
eg (BC,

DE,
HL)
(D) HL
pair is an exceptional pair which is used as a memory pointer to locate an address L X H
2000H.
H recognize HL
pair of general purpose register.
Load 16 bit data immediately in HL
pair it means 2000H is the location of memory where data is
stored and it is recall by an instruction MOV A M
M locates memory location 2000H which is pointed bye HL
pair.
Exceptional point in 8085 microprocessor 16 bit additional can only be possible by using an
instruction
DAD.
3) Special function registerstack
pointer & program counter are two special function register these are those register which are
used only by microprocessor not by user.
a) Program counter(
1) it is a 16 bit register
(2)Used by microprocessor
(3)It holds the address of next instruction to be executed for egafter
execution MOV A,B instruction
program counter will be automatically incremented and points next location of memory
where another
data to stored.
b) Stack pointerIt
is used when interrupt is generated by microprocessor interrupt is a command
which stop the main program counter location will be stored in a stack and program counter
will be
loaded with a new address through which sub routine is called.
Sub routine is a small program which is used many times by main program. For
exampleGenerating
delay in main program after execution of each instruction.
c) Stack
Small memory location acquired by main program in RAM area.
4) Other Registers1)
Instruction Registers
2) Temporary Register
a) Instruction Registers1)
8 Bit long
2) It will store opcode (8 Bit) of an instruction.
b) Temporary register1)
8 Bit long
2) It will store the data temporary before execution of instruction.
Instruction decoderBits
generated by instruction registers will be decoded by instruction decode, It means digital
signal
will be converted in analog signals and these signals will be send to timing and control unit.

Timing and Control UnitSignals

generated by instruction decoder will be provided by control by way using this unit.
For exampleRD,
WR, SID, SOD.
SID & SOD are known as Serial In data and Serial out Data.
For exampleCopy
data from pen drive to microprocessor and vice versa.
Address/Data Bus Buffer (AD0 to AD7)1)
8 bit bidirectional.
2) Address as well as data on the same bus.
3) Both data and address will be differentiating by clock cycle generated by timing and
control unit.
4) First clock cycle will be loaded lower 8 bit address on the bus.
5) Two more clock cycle will load the data on address bus.
Address Bus buffer( A8 to A15)Higher
order address bus unidirectional. Address latch 74373 will be used as temporary storage for
lower bit of address. If address latch is high than address is high and vice versa.
8085 AH1 microprocessor is only microprocessor which operates at 6MHz frequency
because of
HMOS technology.
Registers
In 16-bit mode, such as provided by the Pentium processor when operating as a Virtual 8086
(this is the mode used when Windows 95 displays a DOS prompt), the processor provides the
programmer with 14 internal registers, each 16 bits wide. They are grouped into several
categories as follows:

Four general-purpose registers, AX, BX, CX, and DX. Each of these is a combination
of two 8-bit registers which are separately accessible as AL, BL, CL, DL (the "low''
bytes) and AH, BH, CH, and DH (the "high'' bytes). For example, if AX contains the
16-bit number 1234h, then AL contains 34h and AH contains 12h.

Four special-purpose registers, SP, BP, SI, and DI.

Four segment registers, CS, DS, ES, and SS.

The instruction pointer, IP (sometimes referred to as the program counter).

The status flag register, FLAGS.

Although I refer to the first four registers as "general-purpose'', each of them is designed to
play a particular role in common use:

AX is the "accumulator''; some of the operations, such as MUL and DIV, require that
one of the operands be in the accumulator. Some other operations, such
as ADD and SUB, may be applied to any of the registers (that is, any of the eight

general- and special-purpose registers) but are more efficient when working with the
accumulator.

BX is the "base'' register; it is the only general-purpose register which may be used
for indirect addressing. For example, the instruction MOV [BX], AX causes the
contents of AX to be stored in the memory location whose address is given in BX.

CX is the "count'' register. The looping instructions (LOOP, LOOPE, and LOOPNE),
the shift and rotate instructions (RCL, RCR, ROL, ROR, SHL, SHR, and SAR), and
the string instructions (with the prefixes REP, REPE, and REPNE) all use the count
register to determine how many times they will repeat.

DX is the "data'' register; it is used together with AX for the wordsize MUL and DIV operations, and it can also hold the port number for
the IN and OUT instructions, but it is mostly available as a convenient place to store
data, as are all of the other general-purpose registers.

Here are brief descriptions of the four special-purpose registers:

SP is the stack pointer, indicating the current position of the top of the stack. You
should generally never modify this directly, since the subroutine and interrupt calland-return mechanisms depend on the contents of the stack.

BP is the base pointer, which can be used for indirect addressing similar to BX.

SI is the source index, used as a pointer to the current character being read in a string
instruction (LODS, MOVS, or CMPS). It is also available as an offset to add to BX or
BP when doing indirect addressing; for example, the instruction MOV [BX+SI],
AX copies the contents of AX into the memory location whose address is the sum of
the contents of BX and SI.

DI is the destination index, used as a pointer to the current character being written or
compared in a string instruction (MOVS, STOS, CMPS, or SCAS). It is also available
as an offset, just like SI.

Since all of these registers are 16 bits wide, they can only contain addresses for memory
within a range of 64K (=2^16) bytes. To support machines with more than 64K of
physical memory, Intel implemented the concept of segmented memory. At any given
time, a 16-bit address will be interpreted as an offset within a 64K segment determined by
one of the four segment registers (CS, DS, ES, and SS).
As an example, in the instruction MOV [BX], AX mentioned above, the BX register really
provides the offset of a location in the current data segment; to find the true physical address
into which the contents of the accumulator will be stored, you have to add the value in BX to
the address of the start of the data segment. This segment start address is determined by
taking the 16-bit number in DS and multiplying by 16. Therefore, if DS contains 1234h and
BX contains 0017h, then the physical address will be 1234h TIMES
16+0017h=12340h+0017h=12357h. (This computation illustrates one reason why
hexadecimal is so useful; multiplication by 16 corresponds to shifting the hex digits left one

place and appending a zero.) We refer to this combined address as 1234:0017 or, more
generally, as DS:BX.
Since segment starts are computed by multiplying a 16-bit number by 16=2^4, the effect is
that physical addresses have a 20-bit range, so that a total of 1M (=2^20) of memory may be
used. Intel considered that this would be enough for applications of the 8086 over its
projected lifetime of about five years from its introduction in 1978; by the time
microcomputers were needing more than a meg of main memory, the next Intel processor (the
iAPX432) was due to be available, with a 32-bit address space (able to address 4G---over 4
billion memory locations). However, the IBM PC's debut in 1981 and subsequent popularity
has forced Intel to continue the 80x86 family of backward-compatible processors to the
present, including support for a mode in which only 1M of memory is accessible. Processors
since the 80286 have also provided the "protected'' mode of operation, which in the Pentium
gives each process a flat 32-bit address space of up to 4G.
You might think that a segment register would only need to provide the uppermost 4 bits to
extend an address out to 20 bits, but consider one of the implications of only having 16
different, non-overlapping segments: every segment would have to occupy a full 64K of
memory, even if only a small fraction of this space were needed. By allowing a segment to
start at any address divisible by 16, the memory may be allocated much more efficiently---if
one program only needs 4K for its code segment, then theoretically the operating system
could load another program into a segment starting just 4K above the start of the first. Of
course, MS-DOS is not really this sophisticated, but the Intel designers wanted it to be
possible.
Each segment register has its own special uses:

CS determines the "code'' segment; this is where the executable code of a program is
located. It is not directly modifiable by the programmer, except by executing one of
the branching instructions. One of the reasons for separating the code segment from
other segments is that well-behaved programs never modify their code while
executing; therefore, the code segment can be identified as "read-only''. This
simplifies the work of a cache, since no effort is required to maintain consistency
between the cache and main memory. It also permits several instances of a single
program to run at once (in a multitasking operating system), all sharing the same code
segment in memory; each instance has its own data and stack segments where the
information specific to the instance is kept. Picture multiple windows, each running
Word on a different document; each one needs its own data segment to store its
document, but they can all execute the same loaded copy of Word.

DS determines the "data'' segment; it is the default segment for most memory
accesses.

ES determines the "extra'' segment; it can be used instead of DS when data from two
segments need to be accessed at once. In particular, the DI register gives an offset
relative to ES when used in the string instructions; for example,
the MOVSB instruction copies a byte from DS:SI to ES:DI (and also causes SI and DI
to be incremented or decremented, ready to copy the next byte).

SS determines the "stack'' segment; the stack pointer SP gives the offset of the current
top-of-stack within the stack segment. The BP register also gives an offset relative to
the stack segment by default, for convenient access to data further down in the stack
without having to modify SP. Just as with SP, you should not modify SS unless you
know exactly what you are doing.

The instruction pointer, IP, gives the address of the next instruction to be executed, relative to
the code segment. The only way to modify this is with a branch instruction.
The status register, FLAGS, is a collection of 1-bit values which reflect the current state of
the processor and the results of recent operations. Nine of the sixteen bits are used in the
8086:

Carry (bit 0): set if the last arithmetic operation ended with a leftover carry bit coming
off the left end of the result. This signals an overflow on unsigned numbers.

Parity (bit 2): set if the low-order byte of the last data operation contained an even
number of 1 bits (that is, it signals an even parity condition).

Auxiliary Carry (bit 4): used when working with binary coded decimal (BCD)
numbers.

Zero (bit 6): set if the last computation had a zero result. After a comparison
(CMP, CMPS, or SCAS), this indicates that the values compared were equal (since
their difference was zero).

Sign (bit 7): set if the last computation had a negative result (a 1 in the leftmost bit).

Trace (bit 8): when set, this puts the CPU into single-step mode, as used by
debuggers.

Interrupt (bit 9): when set, interrupts are enabled. This bit should be cleared while the
processor is executing a critical section of code that should not be interrupted (for
example, when processing another interrupt).

Direction (bit 10): when clear, the string operations move from low addresses to high
(the SI and DI registers are incremented after each character). When set, the direction
is reversed (SI and DI are decremented).

Overflow (bit 11): set if the last arithmetic operation caused a signed overflow (for
example, after adding 0001h to 7FFFh, resulting in 8000h; read as two's complement
numbers, this corresponds to adding 1 to 32767 and ending up with -32768).

There are numerous operations that will test and manipulate various of these flags, but to get
the contents of the entire FLAGS register one has to push the flags onto the stack
(with PUSHF or by calling an appropriate interrupt handler with INT) and then pop them off
into another register. To set the entire FLAGS register, the sequence is reversed
(with POPF or IRET). For example, one way to set the carry flag (there are much better ways,
including the STC instruction) is the following:

PUSHF
POP AX
OR AX, 1
PUSH AX
POPF
Most of the time you will not have to deal with the FLAGS register explicitly; instead, you
will execute one of the conditional branch instructions, Jcc, where cc is one of the following
mnemonic condition codes:

O, Overflow

NO, Not Overflow

B, Below; C, Carry; NAE, Not Above or Equal

NB, Not Below; NC, Not Carry; AE, Above or Equal

E, Equal; Z, Zero

NE, Not Equal; NZ, Not Zero

BE, Below or Equal; NA, Not Above (true if either Carry or Zero is set)

NBE, Not Below or Equal; A, Above

S, Sign

NS, Not Sign

P, Parity; PE, Parity Even

NP, Not Parity; PO, Parity Odd

L, Less; NGE, Not Greater or Equal (true if Sign and Overflow are different)

NL, Not Less; GE, Greater or Equal

LE, Less or Equal; NG, Not Greater (true if Sign and Overflow are different, or Zero
is set)

NLE, Not Less or Equal; G, Greater

All of the conditions on the same line are synonyms. The Above and Below conditions refer
to comparisons of unsigned numbers, and the Less and Greater conditions refer to
comparisons of signed (two's complement) numbers.nt) Numbers.