EL3100 - Microprocessors Lab

Experiment-2
(a) Consider the following module for a 4-to-1 multiplexer. Complete the testbench file given below the multiplexer module and simulate the design in Xilinx ISE.
// Module defining a 4-to-1 multiplexer
module mux_4x1(in1, in2, in3, in4, s1, s2, mux_out);
input in1, in2, in3, in4; // input to the MUX
input s1, s2//select lines of the mux
output mux_out; //output of the mux
assign mux_out = s2?(s1?in4:in3):(s1?in2:in1);
endmodule
// Testbench module for 4-to-1 multiplexer
module testbench_multiplexer()

endmodule
(b) A 4-bit barrel shifter (of the rotating kind where the shifted LSB goes to the MSB) is shown in Figure
1. Complete the Verilog program given below (for the barrel shifter) based on the multiplexer module and
implement the design on the FPGA board. Since the board has only 4 sliding switches, two of these should be
used to provide select signals while two others should be used to select one of four hard coded input values
(appearing in the program below). The output of the barrel shifter must appear on the LEDs on the board.
Write an implementation constraints file too (.ucf).

D3

D2

D0

D1

3 2 1 0

3 2 1 0

3 2 1 0

3 2 1 0

MUX 4

MUX 3

MUX 2

MUX 1

2
S3

S2

S1

Figure 1: Barrel Shifter using multiplexers

S0

// Barrel shifter module (to be completed)

module Barrel_shifter_4bit( SW, k, S);
wire [3:0] D; //input of the barrel shifter
input [1:0]SW;
input [1:0] k; // select lines of Barrel shifter
output [3:0] S;
//hardcoding the input values of Barrel shifter
assign D = SW[1]?(SW[0]?4d8:4d13):(SW[0]?4d7:4d9);

--- Provide instantiations for multiplexers here ----

endmodule