Computer Organization

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Computer Organization
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CS260 - Computer Organization
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Syllabus:
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Introduction: Function and structure of a computer,

computer Functional components of a
computer, Interconnection of components, Performance of a computer.
Representation of Instructions: Machine instructions, Operands, Addressing
modes, Instruction formats, Instruction sets, Instruction set architectures - CISC and
RISC architectures.
Processing Unit: Organization of a processor - Registers, ALU and Control unit,

Data path in a CPU, Instruction cycle, Organization of a control unit - Operations of a
control unit, Hardwired control unit, Microprogrammed control unit.
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Memory Subsystem: Semiconductor memories, Memory cells - SRAM and DRAM

cells, Internal Organization of a memory chip, Organization of a memory unit, Error
correction memories, Interleaved memories, Cache memory unit - Concept of cache
memory, Mapping methods, Organization of a cache memory unit, Fetch and write
mechanisms, Memory management unit - Concept of virtual memory, Address
t
translation,
l ti
H
Hardware
d
supportt ffor memory management.
t
Input/Output Subsystem: Access of I/O devices, I/O ports, I/O control mechanisms Program controlled I/O,
I/O Interrupt controlled I/O,
I/O and DMA controlled I/O,
I/O I/O interfaces
- Serial port, Parallel port, PCI bus, SCSI bus, USB bus, Firewall and Infiniband, I/O
peripherals - Input devices, Output
devices, Secondary storage devices.
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References
1. C. Hamacher, Z. Vranesic and S. Zaky, "Computer Organization", McGrawHill, 2002.
2. W. Stallings, "Computer Organization and Architecture - Designing for
Performance", Prentice Hall of India, 2002.
3. D. A. Patterson and J. L. Hennessy, "Computer Organization and Design The Hardware/Software Interface", Morgan Kaufmann,1998.
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4. J .P. Hayes, "Computer Architecture and Organization", McGraw-Hill, 1998.
Computer Level Hierarchy
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Program Execution
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Translation: The entire high level program is translated into an

equivalent machine language program. Then the machine language
program is executed.
Interpretation: Another program reads the high level program

instructions one-by-one and executes a equivalent series of
machine language instructions.
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Program translation uses a collection of tools to perform the translation:

Compiler: Translates high level language programs into a lower level
language often called object code.
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Assembler: Translates assembly language instructions into object code.

Linker: Combines collections of object code into a single executable
machine language program.
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Computer System: Layers of Abstraction
Application Program
Algorithms
Language
Software
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Hardware
IInstruction
t ti Set
S t Architecture
A hit t
(and I/O Interfaces)
Microarchitecture
Circuits
Devices
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From Theory to Practice
In theory, computer can compute anything

thats possible to compute
given enough memory and time
In practice, solving problems involves

computing
ti under
d constraints.
t i t
time
cost
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weather forecast
forecast, next frame of animation
animation, ...
cell phone, automotive engine controller, ...
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power
cell phone, handheld video game, ...
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Transformations Between Layers
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How do we solve a problem using a computer?

A systematic sequence of transformations between
layers of abstraction.
Problem
Al
Algorithm
ith
Software Design:
choose algorithms and data structures
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Programming:
g g to express
p
design
g
use language
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Program
Instr Set
A hit t
Architecture
Compiling/Interpreting:
convert language to
machine instructions
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Deeper and Deeper

Deeper
IInstr
t Set
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Architecture
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Microarch
Processor Design:
choose structures to implement ISA
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Circuits
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Logic/Circuit Design:
gates and low-level circuits to
implement components
Process Engineering & Fabrication:

develop and manufacture
lowest-level components
Devices
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Problem Statement
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Descriptions of Each Level
stated using "natural language"

ambiguous imprecise
may be ambiguous,
Algorithm
Program
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step-by-step
p y
p procedure,
p
, guaranteed
g
to finish
definiteness, effective computability, finiteness
express the algorithm using a computer language
high-level language, low-level language
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Instruction Set Architecture (ISA)

specifies the set of instructions the computer can perform
data types,
types addressing mode
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Microarchitecture
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Descriptions of Each Level (cont

(cont.))
Logic Circuits
detailed organization of a processor implementation

different implementations of a single ISA
D i
Devices
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combine basic operations

p
to realize microarchitecture
many different ways to implement a single function
(e.g., addition)
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properties of materials, manufacturability
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Many Choices at Each Level

Solve a system of equations
FORTRAN
Jacobi
iteration
C++
Intel x86
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Sun SPARC
Gaussian
elimination
Red-black SOR
Pentium II
Pentium III
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Ripple-carry adder
CMOS
Bipolar
Java
Compaq Alpha
AMD Athlon
Carry-lookahead adder
GaAs
Multigrid
g
Tradeoffs:
cost
performance
power
(etc.)
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Whats Next
Bits and Bytes
How do we represent information using electrical signals?
Digital Logic
How do we build circuits to process information?
Processor and Instruction Set
How do we build a p
processor out of logic
g elements?
What operations (instructions) will we implement?
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Assembly Language Programming

How do we use processor instructions to implement
algorithms?
How do we write modular
modular, reusable code? (subroutines)
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I/O, Traps, and Interrupts
How does processor communicate with outside world?

Structure and Function of a COMPUTER SYSTEM:
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A computer is
i a complex
l
system; For analysis,
l i
understanding and design - Identify the
hierarchical nature of most complex system.
system
A hierarchical system
y
is a set of interrelated
subsystems, each in turn, hierarchical in structure;
until at the lowest level we have elementary
subsystems.
b
t
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The hierarchical nature of complex systems is

essential to both their design and their description.
g
need only
y deal with a p
particular level
The designer
of the system at a time.
At each
h level,
l
l the
th system
t
consists
i t off a sett off
components and their interrelationships.
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The behavior at each level depends only

on a simplified, abstracted characterization of
the system at the next lower level.
At each level,, the designer

g
is concerned
with structure and function:
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Structure: The
h way iin which
hi h the
h components are
interrelated.
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Function: The operation of each individual

component
p
as p
part of the structure.
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Central Processing Unit (CPU) based CO
The organization of a simple computer with

one CPU and two I/O devices
There are four main functions of a computer:
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Data processing
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Data storage
Data movement
Control
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MAIN STRUCTURAL BLOCKS/PARTS:
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Central
C
t l Processing
P
i
Unit
U it (CPU):
(CPU) Controls
C t l the
th operation
ti
off
the computer and performs its data processing functions.
Often simply referred to as processor.
Main Memory: Stores data.
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I/O: Moves data between the computer and its external

environment.
System Interconnection: e.g. BUS for communication
among CPU, main memory,
and I/O.
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The major
j
structural components
p
of a CPU are:
Control Unit (CU): Controls the operation of the
C
CPU
and
d hence
h
the
h computer.
Arithmetic and Logic Unit (ALU): Performs

computers data processing functions.
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Register: Provides storage internal to the CPU.
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CPU Interconnection:
I
i
communication
i
i
among the
h
control unit, ALU, and register.
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Structure - Top Level

Computer
Peripherals
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Computer
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Central
Processing
Unit
Main
M
Memory
Systems
Interconnection
Input
Output
Communication
lines
li
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Structure - The CPU
Computer
Registers
g
I/O
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Memory
CPU
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System
Bus
Arithmetic
and
Logic Unit
Internal CPU
Interconnection
CPU
Control
Unit
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Structure - The Control Unit
Sequencing
q
g
Logic
ALU
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Registers
Control
Unit
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Internal
Bus
Control Unit
CPU
Registers and
Decoders
Of CU
Control
Memory
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The First Generation: Vacuum Tube Computers

(1945 - 1953)
Atanasoff Berry
y Computer
p
((1937 - 1938))
solved systems of linear equations.
John Atanasoff and Clifford Berryy of
Iowa State University.
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Electronic Numerical Integrator and Computer Computer

(ENIAC) by
b John
J h Mauchly
M hl andd J.
J Presper
P
E k
Eckertat
the
h U
University
i
i
of Pennsylvania, 1946
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The IBM 650 first mass-produced computer. (1955). It was
phased out in 1969.

p
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The Second Generation: Transistorized

Computers
p
((1954 - 1965))
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IBM 7094 (scientific) and 1401 (business)

Digital Equipment Corporation (DEC) PDP-1
PDP 1
Univac 1100
Control Data Corporation 1604
1604.
. . . and many others.
The Third Generation: Integrated Circuit Computers (1965
- 1980)
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IBM 360
DEC PDP-8 and PDP-11
Cray-1
y supercomputer
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p
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IBM had gained overwhelming dominance in the industry.

Computer manufacturers of this era were characterized as IBM
and the BUNCH (Burroughs, Unisys, NCR, Control Data, and
Honeywell).
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The von Neumann Model
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The invention of stored program computers

has been ascribed to a mathematician, John
von Neumann,
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who
h was a contemporary
t
off
Mauchley and Eckert.
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St
Stored-program
d
computers
t
have
h
become
b
known as von Neumann Architecture
systems.
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Todays
Today s stored-program
stored program computers have the
following characteristics:
Three hardware systems:
y
A central processing unit (CPU)

A main memory system
An
A I/O system
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The capacity to carry out sequential instruction

processing.
g data path
p
between the CPU and main
A single
memory.
This single path is known as the von Neumann
b ttl
bottleneck.
k
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IAS (P
(Princeton)
i
t ) computer
t model
d l by
b Von
V Neumanns
N
group.
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IAS computer consists of:

- A main memory,
memory which stores both data and instructions.
instructions
- An arithmetic-logical
arithmetic logical unit (ALU) capable of operating on
binary data.
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- A control unit, which interprets the instructions in memory

and causes them to be executed.
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- Input
p
and output
p
(
(I/O)
/ ) equipment
q p
operated
p
by
y the
control unit.
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CPU Organization
The data path of a typical Von Neumann machine

machine.
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This is a general
depiction of a von
Ne mann s
Neumann
system:
stem
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These computers
p
employ a fetchdecode-execute
cycle to run
programs as
follows . . .
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Th
The control
t l unit
it fetches
f t h the
th nextt instruction
i t
ti
from
f
memory using the program counter to determine where
the instruction is located.
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Th
The instruction
i t
ti
iis d
decoded
d d into
i t a language
l
that
th t the
th ALU
can understand.
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A
Any d
data
t operands
d required
i d to
t execute
t the
th instruction
i t
ti
are fetched from memory and placed into registers
within the CPU.
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Th
The ALU executes
t the
th instruction
i t
ti
and
d places
l
results
lt in
i
registers or memory.
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IAS Von Neumann (1952+)
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1024 x 40 bit words ( = 5KB memory)

Binary number (2
(2s
s complement)
2 x 20 bit instructions
Set of registers (storage in CPU)
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Memory
y Buffer Register
g
Memory Address Register
Instruction Register
Instruction Buffer Register
Program Counter
Accumulator
Multiplier Quotient
Addition time was 62

microseconds and
the multiplication time
was 713 microseconds.
It was an asynchronous
machine.
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Structure of IAS
Central Processing Unit
Arithmetic and Logic Unit

Accumulator
MQ
A ith ti & Logic

Arithmetic
L i Circuits
Ci
it
MBR
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Input
Output
Equipment
IBR
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IR
Instructions
Main
& Data
Memory
PC
MAR
Control
Circuits
Program
g
Control
Unit
Address
MQ - Multiplier/Quotient
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Non-von Neumann Models

Conventional stored
stored-program
program computers have
undergone many incremental improvements over
the years.
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These improvements include adding specialized

buses floating
buses,
floating-point
point units,
units and cache memories,
memories
to name only a few.
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B
But enormous iimprovements iin computational
i
l
power require departure from the classic von
Neumann architecture.
architecture
Adding processors is one approach.
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CPU
Main
Memory
I/O
Module
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Console
Controller
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DEC - PDP-8
PDP 8 Bus Structure
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OMNIBUS
The Omnibus - a backplane of undedicated slots;
I/O
Module
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Summary of hardware complexity
Small scale integration: 1965 ;
Transistor - 1958-1964
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Vacuum tube - 1946-1957 ;
Up to 100 devices on a chip
Medium scale integration: -1971;
3,000 - 100,000 devices on a chip
Large scale integration :1971-1977;
100-3,000 devices on a chip
Very large scale integration: 1978 -1991; 100,000 - 100,000,000 devices on a chip
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Ultra large scale integration : 1990s;
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Multi-core
Multi
core Architectures 2000s ;
Over 100,000,000
100 000 000 devices on a chip
Over 10^9
10 9 devices on a chip
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Architecture vs. Organization
Often used interchangeably in book titles and as keywords.

keywords
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Thin line of difference should be clear as we progress through

the course material.
An instruction set is a list of all the instructions,

that a processor can execute.
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Typical Categories of Instructions:
Arithmetic - add, subtract

Logic - and, or and not
Data - move,
move input
input, output
output, load and store
Control flow - goto, if ... goto, call and return.
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An instruction set, or instruction set

architecture (ISA), is the part of the computer
architecture related to programming, including the
native data types, instructions, registers,
addressing modes
modes, memory architecture
architecture, interrupt
and exception handling, and external I/O; also
includes a specification of the set of opcodes
(machine language) - the native commands for a
particular processor.
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Computer System: Layers of Abstraction
Application Program
Algorithms
Language
Software
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Hardware
IInstruction
t ti Set
S t Architecture
A hit t
(and I/O Interfaces)
Microarchitecture
Circuits
Devices
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Computer Architecture
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Logical aspects of system implementation as

seen by the programmer; such as, instruction sets
(ISA) and formats, opcode, data types, addressing
modes and I/O.
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Instruction set architecture (ISA) is different

from microarchitecture, which consist of various
processor
p
ocesso des
design
g tec
techniques
ques used to implement
pe e t
the instruction set.
Computers with different microarchitectures
can share a common instruction set.
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For example, the Intel Pentium and the AMD

Athlon implement
p
nearly
y identical versions of the
x86 instruction set, but have radically different
internal designs.
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Computer architecture is the conceptual design
and fundamental operational structure of a computer
system It is a functional description of requirements
system.
and design implementations for the various parts of a
p
computer.
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It is the science and art of selecting and

g hardware components
p
to create
interconnecting
computers that meet functional, performance and cost
goals.
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It deals with the architectural attributes like

physical address memory, CPU and how they should be
designed and made to coordinate with each other
keeping the goals in mind.
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Analogy:
l
building
b ildi
the
h d
design
i
and
d architecture
hi
off
house architecture may take more time due to
planning and then organization is building house by
bricks or by latest technology keeping the basic layout
and architecture of
house
mind.
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Computer architecture comes before

computer organization.
organization
Computer organization (CO) is how

operational attributes are linked together and
contribute
t ib t to
t realise
li
the
th architectural
hit t
l
specifications.
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CO encompasses all physical aspects of

computer systems
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e.g. Circuit design, control signals, memory types.
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Microarchitecture, also known as

Computer organization is a lower level, more
concrete and detailed, description of the system
that involves how the constituent parts of the
system
t
are interconnected
i t
t d and
d how
h
they
th
interoperate in order to implement the ISA.
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The size of a computer's cache, for example, is

an organizational issue that generally has nothing
to do with the ISA.
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Another example: it is an architectural design

issue whether a computer will have a multiply
instruction. It is an organizational issue whether
that instruction will be implemented by a special
multiply unit or by a mechanism that makes
repeated use of the add unit of the system.
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Instruction Set Architecture (ISA) The Hardware-Software Interface
The most important abstraction of computer design

Application
pp Programs
Application
Compiler
I/O System
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Processor
Operating System
Software
Instruction Set Architecture

Interface between SW & HW
Logic - gates, state machines, etc.

Circuit - transistors, etc.
Hardware
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Layout - mask patterns, etc.
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Important Building Blocks
Memory
Microprocessor
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Mass Storage (Disk)
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Network Interface
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Typical Motherboard (Pentium III)

Floppy Conn
Conn.
S Bridge
S.
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Power Conn.
Conn
IDE Disk Conn.

Memory
AGP
Processor
PCI Cards
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N. Bridge
Rear Panel Conn.
Accelerated Graphics Port;

Peripheral
p
Component
p
Interconnect;;
Integrated Drive Electronics;
Basic input/output system
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AGP PCI IDE

BIOS -
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BIOS ROM
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Why design issues matter:

- Cannot assume infinite speed and memory.
- Speed mismatch between memory and processor
- handle
h dl b
bugs and
d errors (b
(bad
d pointers,
i t
overflow
fl
etc.)
t )
- multiple processors, processes, threads
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- shared memory
- disk access
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- better performance with reduced power

-
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Enhancing Performance
(speed)
Pipelining
On board cache
On board L1 & L2 cache
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Branch prediction
Data flow analysis (in compilers)
Speculative execution
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DRAM and Processor

Characteristics
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Typical I/O Device Data Rates
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Performance Analysis
N *S
T
R
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A basic performance equation:
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T processor time required to execute a program (not total time used);

N - Actual number of machine instructions (including that due to loops);
R Cycle/sec
y
S Average No. of clock cycles/instruction;

Earlier measures
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MIPS (Millions of Instructions per sec.)

MFLOPS Million floating point operations per sec.
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CPI Cycles
y
p
per Instruction;;
IPC Instructions per cycle = 1/CPI;
Speedup = (Earlier execution time) / (Current execution time);

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The Unix time <a.out> command gives:
g A:
e.g.
system (kernel) CPU time and
the elapsed real-time.
or
ld
User CPU time;
0.327u 0.010s 0:01.15;
%-age
g elapsed
p
time in CPU:
e.g.
g B:
0.327 0.01
0.45%
75
90.7u 12.9s 0:12.39;;
%-age
g elapsed
p
time in CPU:
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A better situation, for exploitation

of CPU time.
90.7 12.9
65%
159
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CPU execution
ti ti
time ffor a program =
CPU clock cycles

CPU clock cycles * clock cycle time
Clock rate
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CPU execution time for a program =
or
ld
CPU clock cycles

y
CPU clock
l k cycles
l * clock
l k cycle
l time
ti
Clock rate
CPU clock cycles = No. of instructions * Avg. clock cycles/instruction
n
CPU clock cycles N i * CPI i

i 1
CPI = cycles/instruction; N No. of instructions;
CPU execution time for program
TU
= Instruction Count x CPI x Clock Cycle Time
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A better measure:
Exec _ Time( A)
E _ Time
Exec
Ti ( B)
1 n
Exec _ time Timei
n i 1
seconds
sec onds
d
IInstructio
t ti ns clock
l k cycle
l
d
*
*
program Instruction clock cycle
program
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Performance - SPECS
Graphics/Workstations
MPI/OMP
(Orthogonal Multi-Processor)
Mail Servers
Network File System
SIP
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Power
computer processor (CPU),

number of computer processors,
MPI Library,
i ti
interconnect,
i t
t
communication
memory architecture,
compilers, and
shared file system.
system
Java Client/Server
SPEC MPI2007 focuses on performance

of compute intensive applications using
the Message-Passing Interface (MPI),
which means these benchmarks
emphasize the performance of:
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CPU
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(Session Initiation Protocol)

SOA
Not for Graphics, O/S and I/O.
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(Service Oriented Architecture)

Virtualization
Web Servers
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MPI2007 is SPEC's benchmark suite for evaluating MPI-parallel,

g point,
p
, compute
p
intensive performance
p
across a wide range
g of cluster
floating
and SMP (Symmetric multi-processing) hardware.
CFP2006 is used for measuring
g and comparing
p
g compute-intensive
p
floating point performance.
SPEC rating (ratio) = TR / TC;
TR = Running time of the Reference Computer;
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TC = Running time of the Computer under test;
1/ n
SPEC SPECi
i 1
JN
n No. of programs in the SPEC Suite.
Higher the SPEC score,

better the performance
performance.
www.alljntuworld.in
Benchmark
104.milc
Language
C
JNTU World
Application Area
Quantum Chromodynamics
107.leslie3d
Fortran
113.GemsFDTD
Fortran
115.fds4
C/Fortran
121 pop2
121.pop2
C/Fortran
122.tachyon
126.lammps
C++
Molecular Dynamics
127.wrf2
C/Fortran
Weather Forecasting
128.GAPgeofem
C/Fortran
Heat Transfer using FEM
129 tera tf
129.tera_tf
Fortran
3D Eulerian Hydrodynamics
or
ld
TU
JN
Computational Fluid Dynamics CFD
Computational Electromagnetics
CFD: Fire dynamics simulator
Climate Modeling
Graphics: Ray Tracing
130.socorro
C/Fortran
Molecular Dynamics
132.zeusmp2
C/Fortran
Computational Astrophysics
137.lu

Fortran
Implicit CFD
www.alljntuworld.in
JNTU World
- Reduced Power dissipation

- Reduced Space Area
or
ld
From first to fifth/sixth generation systems, the following factors were

also
l taken
t k into
i t consideration,
id
ti
to
t improve
i
the
th performance.
f
- More increase in Speed and Registers (GPRs) for operation
- More memory size

- Use of Cache
TU
- Set of cores on CPU
- pipelining and special MMX hardware.
JN
www.alljntuworld.in
JNTU World
or
ld
Increase in CPU p
performance,, may
y come from three factors:
Increase in clock rate
Improvement in processor design to lower CPI
Compiler enhancements for lower average CPI
Better memory organization
JN
TU
www.alljntuworld.in
JNTU World
Key terminologies:
or
ld
Control Path
ALU, FPU, GPU etc.
Microcontroller
Pipelining
CPU design
Cache
Von-Neumann architecture
Superscalar
Hardware description language
Out-of-order
Out of order execution
Datapath
Register renaming
TU
Multi-core
M lti
(
(computing)
ti )
Dataflow architecture
multi-threading
Stream processing
RISC, CISC
Addressing Modes
Vector processor
Instruction set
JN
Instruction-level parallelism (ILP)
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JNTU World
Flynns taxonomy
MMX instructions
JN
TU
or
ld
SIMD, MIMD
JNTU World
or
ld
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END of INTRO
JN
TU
Lets start some calculations

- binary arithmetic

Computer Organization

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Computer Organization

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CS260 - Computer Organization

Introduction: Function and structure of a computer,

Processing Unit: Organization of a processor - Registers, ALU and Control unit,

Memory Subsystem: Semiconductor memories, Memory cells - SRAM and DRAM

4. J .P. Hayes, "Computer Architecture and Organization", McGraw-Hill, 1998.

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Computer Level Hierarchy

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Translation: The entire high level program is translated into an

Interpretation: Another program reads the high level program

Program translation uses a collection of tools to perform the translation:

Assembler: Translates assembly language instructions into object code.

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Computer System: Layers of Abstraction

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From Theory to Practice

In theory, computer can compute anything

In practice, solving problems involves

cell phone, handheld video game, ...

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Transformations Between Layers

How do we solve a problem using a computer?

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Deeper and Deeper

Process Engineering & Fabrication:

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Descriptions of Each Level

stated using "natural language"

Instruction Set Architecture (ISA)

Descriptions of Each Level (cont

detailed organization of a processor implementation

combine basic operations

properties of materials, manufacturability

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Many Choices at Each Level

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How do we represent information using electrical signals?

How do we build circuits to process information?

Processor and Instruction Set

Assembly Language Programming

I/O, Traps, and Interrupts

How does processor communicate with outside world?

Structure and Function of a COMPUTER SYSTEM:

The hierarchical nature of complex systems is

The behavior at each level depends only

At each level,, the designer

Function: The operation of each individual

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Central Processing Unit (CPU) based CO

The organization of a simple computer with

There are four main functions of a computer:

MAIN STRUCTURAL BLOCKS/PARTS:

I/O: Moves data between the computer and its external

Arithmetic and Logic Unit (ALU): Performs

Register: Provides storage internal to the CPU.

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Structure - Top Level

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Structure - The CPU

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Structure - The Control Unit

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