Logistics
Today
CSE370, Lecture 17
CSE370, Lecture 17
Like a truth-table
010
001
000
011
000
110
010
001
100
3-bit up-counter
111
CSE370, Lecture 17
Ti = 1 iff Ni Ci
T0 := 1
T1 := C0
C1
0
0
1
1
0
0
1
1
C0
0
1
0
1
0
1
0
1
N2
0
0
0
1
1
1
1
0
N1
0
1
1
0
0
1
1
0
CSE370, Lecture 17
N0
1
0
1
0
1
0
1
0
T2
0
0
0
1
0
0
0
1
C0
T1 T0
0 1
1 1
0 1
1 1
0 1
1 1
0 1
1 1
100
3-bit up-counter
110
101
current state
0 000
1 001
2 010
3 011
4 100
5 101
6 110
7 111
next state
001 1
010 2
011 3
100 4
101 5
110 6
111 7
000 0
CSE370, Lecture 17
T0
1 1
1 1
1 1
1 1
C1
T2 := C0 C1
C2
0
0
0
0
1
1
1
1
011
101
111
T flip-flops
C2
T1
C0
C0
0 0
1 1
0 0
1 1
T Q
C2
T
CLK
C1
C2
T2
C0
C1
0 0
0 1
0 0
1 0
C1
CSE370, Lecture 17
Timing issues
For sequential logic, timing is critical because for the same inputs,
the output could be different at different times (like T-flip flops). In
order to achieve desired outputs, timing has to be taken into
consideration.
Transistors, chips, and even wires have their own delays. Because
of this, nothing could ever be perfectly synchronized. It is important
to understand how fast a clock can tick based on these delays and
what the common issues are in making computers to run fast and
accurately.
CLK
Qff
D
CSE370, Lecture 17
Slave D latch
CSE370, Lecture 17
The master-slave D
(polarity reversed from previous class)
Qlatch
CLK
Master D latch
Q
Q
Input
CLK
CLK
Q
Q
Output
D
CLK
CLK
Qff
master-slave D flip-flop
D
Qlatch
Qmasterslave
CLK
CSE370, Lecture 17
Setup time tsu: Amount of time the input must be stable before the
clock transitions high (or low for negative-edge triggered FF)
Hold time th: Amount of time the input must be stable after the clock
transitions high (or low for negative-edge triggered FF)
Clock width tw : Minimum clock width that must be met in order for FF
to work properly
Propagation delays tp-lh and tp-hl: Propagation delay (high to low, low to
high) (longer than hold time)
tsu
D
Q
CLK
tsu
10
Cascading flip-flops
CSE370, Lecture 17
IN
D Q
Q0
>
th
D Q
Q1
>
In
tsu
tsu
Q0
tp-hl
tp-lh
th
tw
CLK
Q1
Clk
th
th
CLK
Q
CSE370, Lecture 17
tp-hl
tp-lh
11
CSE370, Lecture 17
12
System considerations
Q0
Q1
CLK0
CLK1
Original state:
Next state:
13
CSE370, Lecture 17
14
Synchronous
Asynchronous inputs
Asynchronous
IN = 0, Q0 = 1, Q1 = 1
Q0 = 0, Q1 = 0 (should be Q1 = 1)
CSE370, Lecture 17
Avoid latches
Most common: Master-slave D
IN
Asynchronous
Synchronous
Combinational
Logic
Combinational
Logic
Clock
CSE370, Lecture 17
15
3.3V
0V
1
0
Q'
1
0
3.3V
S
3.3V
0V
CSE370, Lecture 17
16
Synchronizer failure
Debouncing
CSE370, Lecture 17
CLK
logic 0
17
CSE370, Lecture 17
logic 1
18
asynchronous
input
Async
Input
synchronized
input
D Q
Q0
D Q
Q1
Clock
19
Summary:
Timing issues with asynchronous inputs
Solutions:
CSE370, Lecture 17
D Q
D Q
21
CSE370, Lecture 17
Q0
Clock
Clock
Clk
CSE370, Lecture 17
Async
Input
D Q
Q1
Clock
20