PWL Analysis Problems

1)
For each circuit shown, determine
the diode currents.

Answer: Suppose, for the circuit on

the left, D1 is open. Then D2 must
be closed, since otherwise the open
diode would have a forward-bias
voltage. But then the current is 18/15 = 1.2 ma, the voltage drop across the 10K is 12 volts, and
D1 has a forward-bias voltage! Hence D1 must actually be closed. The current in the 10K resistor
is 0.9 ma, the current in the 5K resistor (and D2) is 1.8 ma, so that the current in D1 must be 0.9
ma. Verify the diode current polarities are consistent with the assumed diode states.
For the circuit on the right if we suppose that D3 is closed the current in the 5K (and D1) is 1.8 ma,
and the current in the 10K (and D2) is 0.9 ma. Then D3 must be closed, and carry a current of 0.9
ma.

2)

For the circuit shown, below left verify that the three-segment input PWL characteristic is as
drawn below, right.

Answer
For the segment corresponding to D1 ON and D2 off i = (V10)3. The current through the 2 resistor is 5a, and so the
current through D1 (directed to the left) is 5 - i ampere.
Hence the assumed diode state is valid provided i 5a. The
forward voltage across D2 is v+5, and the assumed state for
D2 is valid provided v -5v. This validates the segment
shown in the problem.

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The University of Michigan-Dearborn

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Copyright M H Miller: 2000

revised

For the segment corresponding to D1 OFF and D2 ON

determine that the current i = (v+10)/3. (Try replacing
the two shunt branches by a Thevenin equivalent circuit.)
Require 2i-100. or i 5, for the assumed state of D1 to
be consistent. (Equivalently require v5.) The assumed
state of D2 will be consistent since consistency for D1
requires i > 0, and v 5v.
The middle segment, which connects the extremes, must be consistent if the other two are. However
this can be verified numerically also. For the middle
segment v = i.

3)
Determine the input volt-ampere relation I vs. V, a
and the transfer relation V(2) vs. V for the PWL circuit
shown to the right.

Answer

For V-> - we may anticipate both D1 and D2 are likely

to be OFF. In this condition V = 3I+3. This presumes
I+3 0, or I -3a for consistency with the assumed state of
D1. For consistency with the assumed state of D2 require
2I 6 or I 3.
Hence V=3I+3
for I -3a (or
V -6v.
As I increases past -3a (and V -6v) D1 will close, i.e.,
necessarily change state. In this case V= 2I; note that the
end point of the preceding segment (-6, -3) is the start
point of the present segment. Since D1 already has
switched states it will not switch again with further
increases in V. For D2 to remain OFF requires 2I-6
0 or I 3a (and V 6v); this marks the endpoint of
the segment.
The next (and last) segment corresponds to both
diodes ON, for which I = 2V - 9; the condition for D1
and D2 both ON is V 6v (or I 3a).
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The University of Michigan-Dearborn

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Copyright M H Miller: 2000

revised

4) Carefully sketch and clearly label the input volt-ampere

relation for the circuit shown to the right.

Answer

If v -> - anticipate subject to verification that D1 will be

open and D2 will be closed. Then
v = i. For validity of D1 open require vd 0 or v 3. For
validity of D2 closed require
id = i + 1 0, or v -1. Hence diodes are in assumed
states for v -1

As v increases monotonically expect D2 to change state before D1.v = (i+1)(1) + (i)(1) = 2i + 1.

Still require v 3 for D1 to be open-circuit. For D2 to be open-circuit require vd = (i+1)(1) = [(v1)/2] + 1 0, or v -1. Hence diodes as assumed for -1v3.
v = {i - [(v-3)/2] + 1}(1) + {i - [(v-3)/2]}(1)
=i+2
provided
id = (v-3)/2 0 or v 3
and also provided
vd = {i - [(v-3)/2] + 1}(1) 0
or, solving, v -1.
The controlling condition is v 3

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The University of Michigan-Dearborn

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Copyright M H Miller: 2000

revised

5)
An idealized diode PWL circuit involves two diodes, resistors, sources; a description of the input
resistance was calculated. However the circuit diagram was not saved and spilled coffee obliterates part
of the solution. Microscopic examination reveals that one segment of the solution extends from - to the
coordinates (V, I) = (-5, 2), and another segment extends from (+5, 2) to +. Determine an algebraic
expression for as many of the remaining segments as possible.
Answer
Because there are only two diodes there are at most three segments for the solution. Continuity
(KVL and KCL) requires the one missing segment to extend from (-5,2) to (+5,2).
6) The purpose of this illustration
is to suggest the utility of PWL
analysis. To this end a simplified
bipolar transistor amplifier circuit
is drawn on the left of the figure
below. A PWL equivalent circuit
approximating the transistor
nonlinear terminal volt-ampere
behavior in the circuit to the right
replaces the transistor. All this is
discussed in some detail in later
work. The purpose here is to
apply the methodology described
to analyze the PWL circuit to determine the voltage gain Vout/Vin as a function of Vin.
Answer
The PWL circuit involves two (idealized) diodes, and so there are no more than three segments to
the transfer characteristic. Note that D1 can be forward-biased only for Vin 0.7v. Moreover if D1
is reverse-biased then for Vin 15v D2 also must be reverse-biased. Hence assume as a starting
point that both D1 and D2 are reverse-biased; the effective circuit under these conditions
is drawn to the left, below. Under these circumstances IB will be zero, since KCL requires IB + 120
IB = 0. This condition will be maintained provided both diodes remain reverse-biased; this requires
(for D1) Vin 0.7v and (for D2) that Vin 15v. The dominant condition is of course Vin 0.7v,
and for this condition Vout = 15v.
The next segment of the circuit characteristic then may be expected to correspond to D1 closed and
D2 open, i.e., for Vin 0.7v. The circuit for these circumstances is drawn below, right.

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The University of Michigan-Dearborn

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Copyright M H Miller: 2000

revised

Analysis of this (linear) circuit is straightforward. For example the first expression below is KVL
applied to the loop formed by Vin, the 1K resistor, the 0.7v source, and the 560 resistor. The
second expression is KVL applied to the 5.6K branch. Eliminate The current variable IB to obtain
the third expression. Of course this expression is valid only for Vin 0.7v. Note that Vout = 15v at
Vin = 0.7v; this is the intersection of this segment with the preceding one.
Note that as Vin increases Vout decreases, and eventually D2 will
become forward biased; this condition, i.e., both D1 and D2
closed corresponds to the third and last segment of the
characteristic.
Write a KCL expression at the common node of D1 and D2

and solve for

Vout = 0.34 Vin + 1.33
A computer solution (PSpice) for the voltage transfer characteristic Vout vs Vin using a precision
nonlinear transistor model is plotted in the figure below along with the lines corresponding to each of
the calculated PWL segments.

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The University of Michigan-Dearborn

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Copyright M H Miller: 2000

revised

PWL Transfer Function Problems

1)

The idealized diode PWL circuit drawn to the right

synthesizes the square root voltage transfer function
Vout = Vin for 0 Vin 25. The PWL
approximation to the transfer function used agrees
exactly with the theoretical expression at Vin = 0, 1, 4,
9, 16, and 25 volts respectively. Derive the circuit
shown by way of verifying the synthesis.

Note: A practical version of this circuit is described in later notes on diodes.

An equation for the Vout vs Vin PWL line segment starting at (Vin = n2, Vout = n) and
ending at (Vin = (n+1)2,Vout = n+1) is
Answer

where n is an integer (= 0,1,2,3,). Hence we need to design a PWL admittance for which the
current is

Note that the voltage used is Vout, since across the admittance is Vout, i.e., the PWL characteristic
needed involves I vs Vout. The change in admittance from one segment to the next is 2(n+1) -2n = 2
Sieman, and successive segments are activated at voltages of Vout = 1,2,3, volts. The circuit
diagram shows resistance values scaled by a constant factor R.
For the I = Vout synthesis described above (in the notes) verify that the nth segment begins at
V = n2, I =n and ends at V = (n+1)2, I = n+1, so that the segment is described by V = (2n+1)I - n(n+1).
(This expression is the dual of that for problem 1.) Verify further that the change in slope from the
preceding segment corresponds to an additional 2 series resistor, and so the nth segment corresponds
to the addition of a 2 re
2)

As noted the equation for the I vs. V PWL line segment starting at (Vin = n2, I = n) and
ending at (Vin = (n+1)2, I = n+1) is V = (2n+1)I - n(n+1) where n is an integer (= 0,1,2,3,). For
Answer

n=0, i.e. the segment starting at V=0, V = I and corresponds to a 1 resistor. The change in slope
between a segment starting at V= n and one starting at V=n+1is 2 , i.e. each successive segment
activated adds a 2 resistor in series with the previous branch. To activate a segment starting at
(V = n2, I = n) insert a voltage source (as shown) with strength 2I = 2n..

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The University of Michigan-Dearborn

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Copyright M H Miller: 2000

revised

3) Synthesize a circuit whose conductance is described

by the PWL characteristic to the right.

Answer
Start the synthesis with the leftmost segment, and work right. The equation of
the line corresponding to the part of the characteristic less than -5v is v=2i+5
(obtained from the slope and the endpoint at (-5, -5). This corresponds to the
equivalent circuit to the right.
The admittance increases in the next segment indicating that for v -5 a
branch shunting the preceding must become active. The equation for the
middle segment is v = 1(determined, for example, from the two end points).
Since the previous branch remains active and provides 1/2 Siemen only an
additional conductance of 1/2 Siemen is needed. As indicated this second
branch is to become active at v=-5v; this constraint is provided by the diode
and source. Both branches are shown in the figure.
The final segment is described by the equation v = 2i -5.
The change to this segment is to initiate at (5,5), and
since the admittance decreases a resistance is to be added
in series. Both of the previous branches remain active
providing 1, so an additional series 1 is needed as
shown in the figure. Note that D2 is open and the series
resistance active only if i - 5 0, i.e., i 5.

4)
A PWL approximation to a Zener diode characteristic (this
device is considered in detail later) is drawn to the right.
Synthesize a circuit to provide this conductance. Note: Vz is
usually specified as a positive number.

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The University of Michigan-Dearborn

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Copyright M H Miller: 2000

revised

Answer
The solution is simpler than it might seem to be at first. The branch on
the left corresponds to the left segment of the Zener characteristic. The
diode assures no current for v Vz. The other branch is inactive for V
Vf, and when activated fixes the terminal voltage at Vf whatever current
(> 0) is drawn. For -Vz V Vf there is no current path.

Introductory Electronics Notes

The University of Michigan-Dearborn

10-8

Copyright M H Miller: 2000

revised