Chapter 3 B PDF

ESE 570 MOS TRANSISTOR
THEORY Part 2
GCA (gradual channel approximation) MOS Transistor Model
Strong Inversion Operation
Kenneth R. Laker, University of Pennsylvania, updated 27Jan14
Two-Terminal MOS Capacitor -> nMOS Transistor

VGS << VT0
NMOS TRANSISTOR IN CUTOFF REGION
VG
VD
VS
-
Substrate or
Bulk B
Depletion
region
Immobile
acceptor
ions
Two-Terminal MOS Capacitor -> nMOS Transistor

VGS = VT0n +
Onset of INVERSION
VG
QI
-
VD
QB0
-
MOS Transistor Regions of Operation
n
-
n
-
VDS = VD VDSAT = VGS - VT0
VDS - VDSAT
VGD = VGS VDS < VT0

-
z n+
-
- VCS(y) = VDSAT
n+
-
MOSFET CURRENT VOLTAGE CHARACTERISTICS

VG = VGS > VT0 and VGD > VT0
VD = small
n+ z
n+
yy
x
2
dy
1
V
sec
cm
dR=
.=
2
W n Q I y
cm C
n = U0 = electron mobility = cm2/{V sec}
VG = VGS > VT0

VD = VDS
n+
n+
VCS(y)
VCS(y = 0) = VS = 0
VCS(y = L) = VDS
Ey >> Ex, Ez
Mobile charge in inverted channel:
QI(y) = -Cox [VGS VCS(y) - VT0]
I 1
=
V R
QI(y) = -Cox [VGS VCS(y) - VT0]
VCS(y = 0) = VS = 0
VCS(y = L) = VD
dVCS
0 VCS(y) VDS
dVCS
VGS - VCS - VT0 dV

CS
2
CS
(VGS VT0)VCS - V /2
VCS = VDS
VCS = 0
KP -> Transconductance Parameter

2
cm C 1
C /s A
KP=n C ox =
= 2 = 2
2
Vs V cm
V
V
10
ID(VDS = VDSAT) and VDSAT = VGS - VT0
Assumptions:
11
@VDS = VDSAT = VGS - VT0
n C ox W
2
I D sat =
V GS V T0
2 L
ID(VDS = VDSAT) = ID(sat)
LINEAR
SAT
IN GENERAL
ID(sat)
12
VDSAT
+
n+
V DS V DSAT
1
1
1V DS
L 1V DS
1
for V DS 1
L
13
Compatible Eqs. ?
ID = f(VGS, VDS)
0
0
0
14
DISCONTINUOUS!
@ VDS = VDSAT
15
V DS 1
16
V T =V T0 2 F V SB 2 F
V DS 1
17
(VT = VTn > 0)
V GD V T
VGS > VT, VDS < VGS - VT
VGS > VT, VDS VGS - VT
(VT = VTp < 0)
V GD V T
V GD V T
VGS < VT, VDS > VGS - VT
VGS < VT, VDS VGS - VT

V GD V T
18
D
G
=> SAT
19
=> SAT
20
n+
n+
21
V GS
E ox =
volts /cm
t ox
E=
q
N A x volts /cm
si
22
V GS
E ox =
volts/cm
t ox
Year
E=
q
N A x volts/cm
si
1993 1995 1997 1999 2001
Feature Size (m) 0.80
0.60
0.35
0.25
0.18
2003
2005 2007
0.13
0.09
0.045
Historical reduction in min feature size for typical CMOS process

23
24
LD
n+
LD
+
n+
25
(nMOS, pMOS)
Model
Depletion Region Capacitances

26
CGS0(overlap) = CoxWLD
CGD0(overlap) = CoxWLD
CGB0(overlap) = CoxWovLM
SPICE: CoxLD = CGS0 = CGD0 in F/m; CoxWov = CGB0 in F/m
Wov
n+
LD
n+
Wov
27
CBG0 Gate-to-Bulk Overlap Capacitance

CBG0
Weff
SiO2
poly
n+
p
Wov
CGB0 = CoxWovLM
SiO2
Wov
(conservative
estimate)
28
Cgb, Cgs and Cgd
n+
n+
Leff
Leff
n+
n+
MOSFET Saturation Region
n+
n+
Leff
29
Gate-to-Bulk, - Drain & - Source Oxide

Capacitances Summary
+ 2CGB0
0 + 2CGB0
0 + 2CGB0
Application of Oxide Capacitance Model:

1. Approximate: For hand calculations, assume that C gb, Cgd and Cgs are connected in
parallel for each region of operation, i.e.
Cg(tot) = CoxWLeff + 2CGB0 + CGD0 + CGS0
Cut-off Region;
Cg(tot) = CoxWLeff + 2CGB0 + CGD0 + CGS0
Linear Region;
Cg(tot) = 2/3 CoxWLeff + 2CGB0 + CGD0 + CGS0 Saturation Region.
and use the maximum value Cg(tot) = CoxWLeff + 2CGB0 + CGD0 + CGS0
30
Depletion Region Capacitances -> Cdb, Csb
n+
n+
31
Assume Weff = W
32

n+
V = Ext Bias --> VSB, VDB
Qj = depletion-region charge
A = junction area
dQ j
A C j0
AS , AD CJ (F)
C j V =
=
=
m
MJ
dV
V
V
1
1
PB
0
where
Si
q Si N A N D 1
2
(F/cm
)
CJ =C j0 = =
xd
2 N AN D 0
ND
m = MJ = grading coefficient
m = for abrupt junction
[AS, AD -> Source, Drain

Areas in SPICE]
[CJ -> Cj0 in SPICE]
[PB -> O0 in SPICE]
[MJ -> m in SPICE]
33
SUMMARY n+, p Junctions

C j V =
where
A C j0
AS , ADCJ
(F)
=
m
MJ
V
V
1
1
PB
0
q Si N A N D 1
CJ =C j0 =
2 N A N D 0
SPICE
Parameters
(F/cm2)
Cj(0) = A Cj0 when V = 0

[AS, AD -> Source, Drain
Areas in SPICE]
[CJ -> Cj0 in SPICE]
[PB -> O0 in SPICE]
[MJ -> m in SPICE]
34
n+, p Junctions
C j V =
A C j0
AS , ADCJ
=
m
MJ
V
V
1
1
PB
0
voltage
dependent
EQUIVALENT LINEAR LARGE SIGNAL CAPACITANCE

V
Q Q j V 2 Q j V 1
1
C eq =
=
=
C j V dV
V
V 2 V 1
V 2 V 1
V
2
voltage
0
V 2 1m
V 1 1m
C j V C eq =A C j0
[1 1 ] independent
V 2V 1 1m
0
0
approximation
0 < Keq < 1 --> Voltage Equivalence Factor
where V1 V V2
V = Ext Bias --> VSB, VDB for nMOS
VBS, VBD for pMOS
C j V = A C j0 K eq = AS , ADCJK eq
35
[PS, PD -> Source, Drain

Perimeters in
SPICE]
(F/cm2) [CJSW -> C in SPICE]
jsw
[PBSW -> O0SW in SPICE]
[MJSW -> m(sw) in SPICE]
(F/cm)
dQ jsw
C jsw V =
=
dV
[XJ -> xj in SPICE]
P C jsw
PS , PDCJSW
=
msw
MJSW
V
V
1
PBSW
0sw
1m sw
(F)
1m sw
V2
V1
Recall for n+, pjunctions
0sw
K eq sw=
[1
V 2 V 1 1m
sw
dQ j
A C j0 0sw
AS , ADCJ 0sw
C j V =
=
=
(F)
m
MJ
V junction V
m(sw) = dV
for an abrupt
1
1
PB
0
36
dQ jsw
C jsw V =
=
dV
P C jsw
PS , PDCJSW
=
MJSW
V msw
V
1
PBSW
0sw
voltage
dependent
voltage
independent
approximation
where
V1 V V2
V = Ext Bias --> VSB, VDB for nMOS

VBS, VBD for pMOS
37
4
CJ = 1.35 x 10-8 F/cm2
CJSW = 5.83 x 10-12 F/cm
PB = 0.896 V
PBSW = 0.975 V
XJ = 1 x 10-4 cm
MJ = MJSW =
D n+
n+
38
C j V = A C j0 K eq = ADCJK eq
1 MJ
V2
PB
K eq =
[1
V 2V 1 1MJ
PB
1 MJ
V1
1
PB
CJ = 1.35 x 10-8 F/cm2

CJSW = 5.83 x 10-12 F/cm
PB = 0.896 V
PBSW = 0.975 V
XJ = 1 x 10-4 cm
MJ = MJSW = 1/2
1/2
20.896 V
5V
0.5 V 1 /2
=
[1
1
]=0.52
5V 0.5 V
0.896 V
0.896 v
C jsw V =P C jsw K eq sw =PDCJSWK eq sw

1 MJSW
V2
PBSW
K eq sw=
[1
V 2 V 1 1MJSW
PBSW
1 /2
1 MJSW
V1
1
PBSW
1/ 2
= 20.975 V [1 5 V 1 0.5 V ]=0.53K eq

5V 0.5 V
0.975V
0.975 v
39
CJ = 1.35 x 10-8 F/cm2

CJSW = 5.83 x 10-12 F/cm
PB = 0.896 V
PBSW = 0.975 V
XJ = 1 x 10-4 cm
MJ = MJSW = 1/2
C j V = A C j0 K eq = ADCJK eq =55 x 10 cm 1.35 x 10 F / cm 0.52=3.86 fF

C jsw V =P C jsw K eq sw =PDCJSWK eq sw
= 2.5 x 103 cm5.83 x 1012 F / cm0.53=7.72 fF
C db = ADCJK eqPDCJSWK eq sw =11.58 fF
40
MOSFET CAPACITANCE SUMMARY

OXIDE CAPACITANCES
Cgb = COX WLeff + CGB0
Cgd = (1/2) COX WLeff + CGD0
Cgs = (2/3) COX WLeff + CGS0
Leff = LM - 2LD
DEPLETION CAPACITANCES
Csb = Cj(VSB) + Cjsw(VSB)
Cdb = Cj(VDB) + Cjsw(VDB)
C j V =
AS , AD CJ
AS , AD CJK eq
Assume: AS = AD
MJ
V
1
1MJ
1MJ
V
V
PB
PB
K eq =
[1 2
1 1
]
V 2V 1 1MJ
PB
PB
C jsw V =
PS , PDCJSW
PS , PDCJSWK eq sw Assume: PS = PD
MJSW
V
1
PBSW
V 2 1MJSW
V 1 1MJSW
PBSW
K eq sw=
[1
]
V 2 V 1 1MJSW
PBSW
PBSW
41
Short Channel Effects Leff xj

Velocity saturation limit
Reduced electron, hole mobility
Reduced threshold voltage V
T0
Narrow Channel Effects W xdm
Increased threshold voltage V
T0
Sub-threshold Current VGS < VT0
Non-zero drain current when V
< VT0
GS
42
SHORT CHANNEL ISSUES
v sat
cm
V
cm2
0 =
/ =
sec cm V sec
I D sat =W v sat C ox V GS V T
n0
n eff
1V GS V T
(Lvl 3)
43
SHORT CHANNEL ISSUES - CONT.

Short Channel Effect Leff xj (source, drain diffusion depth)
G
S
n+
pn+
depletion
region
D
n+
QB0
Leff
xj
pn+
depletion
region
VGS induced
depletion
region
Q ox Q B0
V T0 long channel =V FB 2 F
C ox C ox
n+
n+
Leff
QB0(sc)
QB0(sc) << QB0
VT0 (short channel) = VT0 (long channel) - VT0

22
44
NARROW CHANNEL ISSUES

Narrow Channel Effect W xdm (depletion region depth)
field-oxide
gate-oxide
Gate Extension
design rule
field-oxide
QB0(nc)
QB0(nc) > QB0
Q ox Q B0
V T0 long channel =V FB 2 F
C ox C ox
45
I D subthreshold =I S e
V GS
n kT / q
V DS
1e
kT /q
1V DS
Si t ox
sub-threshold swing coefficient: n1
ox t Si
C ox W kT 2
I S
L
q
[SPICE Parameter: N0 -> n sub-threshold swing coefficient

NOTE:
ID (sub-threshold) is leakage current for strong-inversion operation
ID (sub-threshold) is primary current for weak-inversion operation
+
J. Rabaey, A. Chandrakasan and B. Nikolic; Digital Integrated Circuits 2nd Edition,

Prentice Hall, 2003, pp99.
46
(MOSIS: Level 3 model used for min feature size 1 m)
(MOSIS: BISIM3 model used for min feature size < 1 m)

47
Complexity of SPICE Models vs. Time

BSIM4v6.5 (2009)
EKV = Enz-Krummenacher-Vittoz
(EKV) model is for low-power
analog circuit simulation.
SPICE Parameter Calculator Rochester Institute of Technology

http://people.rit.edu/lffeee/Spice_Parameter_Calculator.XLS
48
MOS SPICE MODEL PARAMETERS

Name
Model Parameters
LEVEL
Model type (1, 2, or 3)
L
W
LD
WD
Channel
Channel
Lateral
Lateral
VTO
U0
KP
GAMMA
PHI
LAMBDA
Zero-bias threshold voltage

Mobility
Transconductance
Bulk threshold parameter
Surface potential
Channel-length modulation
(LEVEL = 1 and 2)
RD
RS
RG
RB
RDS
RSH
NRS
IS
JS
PB
length
width
diffusion length
diffusion width
Drain ohmic resistance

Source ohmic resistance
Gate ohmic resistance
Bulk ohmic resistance
Drain-source shunt resistance
Drain-source diffusion sheet
Resistance
Number of squares of RD, RS
Bulk p-n saturation current
Bulk p-n saturation/current area
Bulk p-n potential
Units
m
m
m
m
V
cm**2/Vs
A/V**2
V**1/2
V
1/V
Ohms
Ohms
Ohms
Ohms
Ohms
Ohms/sq.
A
A/m**2
V
49
MOS SPICE MODEL PARAMETERS - CONT.

Name
Model Parameters
Units
LEVEL
CBD
CBS
CJ
CJSW
MJ
MJSW
FC
CGSO
CGDO
CGBO
Bulk-drain zero-bias p-n cap (not used)

F
Bulk-source zero-bias p-n cap (not used)
F
Bulk p-n zero-bias bottom cap/area
F/m**2
Bulk p-n zero-bias perimeter cap/length
F/m
Bulk p-n bottom grading coefficient
Bulk p-n sidewall grading coefficient
Empirical bulk p-n forward-bias cap coefficient
Gate-source overlap cap/channel width
F/m
Gate-drain overlap cap/channel width
F/m
Gate-bulk overlap cap/channel width
F/m
NSUB
NSS
NFS
TOX
TPG
XJ
Substate doping density

Surface-state density
Fast surface-state density
Oxide thickness
Gate material type:
+ 1 = opposite of substrate,
- 1 = same as substrate,
0 = aluminum
Metallurgical junction depth
1/cm**3
1/cm**2
1/cm**2
m
m
50
MOS SPICE MODEL PARAMETERS - CONT.
Name
Model Parameters
Units
LEVEL
UCRIT
DELTA
THETA
ETA
KAPPA
Mobility degradation critical field

V/cm
(LEVEL=2)
Empirical mobility degradation exponent
(LEVEL=2)
Maximum carrier drift velocity (Level=2)
m/s
Empirical channel charge coefficient
(LEVEL=2)
Empirical Fraction of channel charge
attributed to drain (Level=2)
Empirical channel width effect on VT
Empirical mobility modulation (LEVEL=3)
1/V
Empirical static feedback on VT (LEVEL=3)
Empirical saturation field factor (LEVEL=3)
KF
AF
Flicker noise coefficient

Flicker noise exponent
UEXP
VMAX
NEFF
XQC
51
Level 3 SPICE Parameters
KP (in A/V2) = k'n (k'p)

VT0 (in volts) = VTn (VTp)
U0 (in cm2/{Vs}) = n (p)

52
G D S
53
54

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ESE 570 MOS TRANSISTOR

Kenneth R. Laker, University of Pennsylvania, updated 27Jan14

Two-Terminal MOS Capacitor -> nMOS Transistor

NMOS TRANSISTOR IN CUTOFF REGION

Kenneth R. Laker, University of Pennsylvania, updated 27Jan14

Two-Terminal MOS Capacitor -> nMOS Transistor

Kenneth R. Laker, University of Pennsylvania, updated 27Jan14

MOS Transistor Regions of Operation

Kenneth R. Laker, University of Pennsylvania, updated 27Jan14

MOS Transistor Regions of Operation

Kenneth R. Laker, University of Pennsylvania, updated 27Jan14

MOS Transistor Regions of Operation

VDS = VD VDSAT = VGS - VT0

VGD = VGS VDS < VT0

Kenneth R. Laker, University of Pennsylvania, updated 27Jan14

MOSFET CURRENT VOLTAGE CHARACTERISTICS

Kenneth R. Laker, University of Pennsylvania, updated 27Jan14

VG = VGS > VT0

QI(y) = -Cox [VGS VCS(y) - VT0]

VGS - VCS - VT0 dV

Kenneth R. Laker, University of Pennsylvania, updated 27Jan14

KP -> Transconductance Parameter

ID(VDS = VDSAT) and VDSAT = VGS - VT0

Kenneth R. Laker, University of Pennsylvania, updated 27Jan14

@VDS = VDSAT = VGS - VT0

Kenneth R. Laker, University of Pennsylvania, updated 27Jan14

Kenneth R. Laker, University of Pennsylvania, updated 27Jan14

Kenneth R. Laker, University of Pennsylvania, updated 27Jan14

Kenneth R. Laker, University of Pennsylvania, updated 27Jan14

Kenneth R. Laker, University of Pennsylvania, updated 27Jan14

(VT = VTn > 0)

VGS > VT, VDS VGS - VT

(VT = VTp < 0)

VGS < VT, VDS VGS - VT

Kenneth R. Laker, University of Pennsylvania, updated 27Jan14

Kenneth R. Laker, University of Pennsylvania, updated 27Jan14

Kenneth R. Laker, University of Pennsylvania, updated 27Jan14

1993 1995 1997 1999 2001

Feature Size (m) 0.80

Historical reduction in min feature size for typical CMOS process

Kenneth R. Laker, University of Pennsylvania, updated 27Jan14

Kenneth R. Laker, University of Pennsylvania, updated 27Jan14

Depletion Region Capacitances

Kenneth R. Laker, University of Pennsylvania, updated 27Jan14

CBG0 Gate-to-Bulk Overlap Capacitance

Kenneth R. Laker, University of Pennsylvania, updated 27Jan14

Cgb, Cgs and Cgd

MOSFET Saturation Region

Kenneth R. Laker, University of Pennsylvania, updated 27Jan14

Gate-to-Bulk, - Drain & - Source Oxide

Application of Oxide Capacitance Model:

Depletion Region Capacitances -> Cdb, Csb

Kenneth R. Laker, University of Pennsylvania, updated 27Jan14

Depletion Region Capacitances -> Cdb, Csb

Kenneth R. Laker, University of Pennsylvania, updated 27Jan14

Depletion Region Capacitances -> Cdb, Csb

V = Ext Bias --> VSB, VDB

Kenneth R. Laker, University of Pennsylvania, updated 27Jan14

[AS, AD -> Source, Drain

SUMMARY n+, p Junctions

Cj(0) = A Cj0 when V = 0

Kenneth R. Laker, University of Pennsylvania, updated 27Jan14

EQUIVALENT LINEAR LARGE SIGNAL CAPACITANCE