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IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 47, NO. 1, JANUARY 2000

A New On-Chip Interconnect Crosstalk Model and

Experimental Verification for CMOS VLSI Circuit
Design
Yungseon Eo, William R. Eisenstadt, Senior Member, IEEE, Ju Young Jeong, and Oh-Kyong Kwon, Member, IEEE

AbstractA new, simple closed-form crosstalk model is

proposed. The model is based on a lumped configuration but
effectively includes the distributed properties of interconnect
capacitance and resistance. CMOS device nonlinearity is simply
approximated as a linear device. That is, the CMOS gate is
modeled as a resistance at the driving port and a capacitance at a
driven port. Interconnects are modeled as effective resistances and
capacitances to match the distributed transmission behavior. The
new model shows excellent agreement with SPICE simulations.
Further, while existing models do not support the multiple line
crosstalk behaviors, our model can be generalized to multiple
lines. That is, unlike previously published work, even if the
geometrical structures are not identical, it can accurately predict
crosstalk. The model is experimentally verified with 0.35- m
CMOS process-based interconnect test structures. The new model
can be readily implemented in CAD analysis tools. Thereby, this
model can be used to predict the signal integrity for high-speed
and high-density VLSI circuit design.
Index TermsCrosstalk, distributed-model, effective-capacitance, effective-resistance, interconnects, lumped-model,
signal-integrity.

I. INTRODUCTION

ODAYS high-performance VLSI processes integrate

more than several million transistors in an IC using deep
submicron lithography. Increased chip size as large as 2 2 cm
or more is being realized. These circuits are switching in less
than a nanosecond, which means both device and parasitics
have several gigahertz bandwidth. Such technologies will keep
improving in the future. Thus, the chip size and density keep
increasing and the minimum feature size continues to decrease.
Moreover, such high-performance VLSI circuits will have
a lower noise margin due to lower power and higher speed
operation.
In such circuits, interconnect lines become one of the crucial
design issues for both signal delay and crosstalk because it is
necessary to guarantee the signal integrity at the design stage. As
Manuscript received July 23, 1998; revised June 1, 1999. The review of this
paper was arranged by Editor D. P. Verret.
Y. Eo is with the Department of Electronic Engineering, Hanyang University,
Kyungki-Do 425-791, Korea (e-mail: eo@iel.hanyang.ac.kr).
W. R. Eisenstadt is with the Department of Electrical and Computer
Engineering, University of Florida, Gainesville, FL 32611-6130 USA (e-mail:
wre@tec.ufl.edu).
J. Y. Jeong is with the Department of Electronic Engineering, University of
Suwon, Suwon, Korea (e-mail: jyeong@mail.suwon.ac.kr).
O.-K. Kwon is with the Department of Electronic Engineering, Hanyang University, Seoul 134, Korea.
Publisher Item Identifier S 0018-9383(00)00236-7.

technologies advance, their importance will be more apparent

because the dominant signal distortions and logic failures will
not be due to gates but due to the interconnect lines [1], [2]. In
the complicated multilayered interconnect system, signal coupling and delay strongly affect circuit performance. Thus, accurate interconnect characterization and modeling are essential
for todays VLSI circuit design.
In general, transmission lines have been accurately modeled
as distributed circuits [3][5]. While the distributed circuit
model is very accurate, it requires an impractical amount of
simulation time. Therefore, most large scale IC CAD tools
cannot support such distributed circuit models. In order to
improve the accuracy of CAD tools such as router or timing
verification tools, a simple but accurate closed-form model
for crosstalk noise should be included within them, since the
analog simulation CAD tools are too slow for million transistor
circuit analysis.
Recently, Sakurai derived a good interconnect crosstalk
network
model [6]. He modeled the transmission line as an
and presented its step response as a power series [7]. Since
the series is too complicated to be analytically solved, he used
a first-order approximation and then extended the simple expression to two coupled lines. Finally, he derived the crosstalk
model in a closed form. This model is good for its intended
applications such as two lines and high input impedance gates.
However, it overestimates or underestimates the amount of
crosstalk signal for more general structures. Moreover, there is
a need to extend the model to more than two coupled lines.
In this work, we propose an efficient crosstalk model for
CMOS circuits based on realistic assumptions. CMOS circuits
are simply modeled as resistance at the driving port and capacitance at the load port. The model is extended to n-coupled lines
for multiline circuit analysis. Our new model shows excellent
agreement with HSPICE [8] simulations in which a segmented
transmission line model is employed. To solidify the developed
model, 0.35 m CMOS process-based test patterns were designed and fabricated. Then, high-speed time-domain measurement data were compared with the model in order to show good
agreements with the model. This model is based on an asymmetrical interconnect system. The model readily predicts the worst
case crosstalk for general structures of n-coupled lines. How-based model, inductive effects
ever, since our model is an
were not considered.
The paper is organized as follows. First, a fundamental
model of the interconnect transmission line is described. Next,
the simple crosstalk model of two coupled lines is derived,

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130

followed by the extension to the general coupled line system.

Then, the model is verified with segmented SPICE model
simulations which accurately simulate the distributed effect of
an IC transmission line. Afterwards, the model validity is solidified by comparing the high-speed TDR/TDT (time-domain
reflectometry and time-domain transmission) experiments with
the model. Finally, conclusions are presented.

(a)

II. INTERCONNECT MODEL FUNDAMENTALS

In general, since interconnect lines are modeled as distributed
transmission lines, their mathematical formulation results in the
Telegraphers equation. If the excitation signal is not sinusoidal
but a general function, a transmission line response is presented
in terms of space and time derivatives

(b)
Fig. 1. Schematic circuits composed of CMOS inverters and interconnects.
The driving ports are modeled as resistance and the driven ports are modeled as
capacitances, respectively: (a) schematic diagram and (b) circuit model.

(1)
(2)
To analytically solve these equations, the details of the transmission system must be understood. Although the full solution gives a more accurate signal representation, it takes a large
amount of computation time. Thus, the full solution cannot be
applied to more complicated interconnect circuits. In the CMOS
on-chip crosstalk noise analysis, dielectric loss ( ) and inductance ( ) can be neglected in the first-order approximation although the inductance cannot always be neglected [9]. In general, the impedance conditions (i.e., source impedance , the
, and load impedance,
) have a substanline resistance
, the intial influence on the crosstalk noise. If
ductance effect can be neglected within 10% error. However,
and
, the inductive coupling noise
if
cannot be neglected and may become significant. This is not the
case for practical CMOS circuits because the driver resistance is
moderate and the receiver is a high impedance capacitive load.
Thus, the inductive coupling noise in CMOS circuits can be neglected as a first-order approximation. Then
(3)
In the multiconductor system, such signals and parameters
can be presented in matrix form. In many papers [10][13],
the equations were rigorously solved for two coupled lines.
These solutions are very accurate because they are based
on rigorous physical and mathematical analysis. In contrast,
since the solution equations are frequency-domain functions
or time-domain convolution integrals, time-consuming inverse
Fourier transforms or convolution integrals are necessarily
required to predict the time-domain responses. Moreover, they
require many other computations and matrix manipulations.
Hence, these approaches cannot simulate interconnect lines
for complicated circuit designs with thousands of transmission
lines and multiple interconnect layers. A simple but accurate
model is required for such complicated VLSI circuit design.
The most basic building block in CMOS circuits is the inverter. Thus, our model assumes that both driving stage and
driven stage is composed of inverters. A more complicated cir-

Fig. 2. Physical coupling mechanism through the distributed RC network of

coupled lines.

cuit analysis can be achieved by modifying this simple structure.

Inverter circuits are a combination of nonlinear devices. However, an inverter is approximately modeled as resistance in the
driving stage of interconnect and capacitance in its driven stage
as shown in Fig. 1 [14]. The resistance for a moderate size in) ranges from 40 to 400 .
verter (
III. EFFECTIVE RESISTANCE AND CAPACITANCE
In general, the amount of crosstalk at the quiet line is strongly
influenced by the termination conditions and transmission line
parameters as discussed in Section II. A capacitive coupling current at the quiet line is divided into two parts (forward current
wave and backward current wave), as shown in Fig. 2. Then,
these waves are reflected whenever the impedance is changed
(i.e., at the driver and at the receiver) and their directions are
reversed. When the noise pulse arrives at the far end, it doubles
). A
because of the high impedance capacitance (
large amount of the backward crosstalk (near end crosstalk) is
reflected from the near end to the far end because of
and adds up with the forward crosstalk. For a long line [in which
) is less than the round trip delay (
) of
a rise time (
the wave], the near end crosstalk voltage is independent of the
line length but depends on the input driving voltage. In contrast, the far end crosstalk is proportional to the slope of driving
signal and the length of the coupled line. Thus, the longer the
line length, the bigger the forward noise (far-end) buildup. Furthermore, far-end crosstalk has a wider noise signal than that of

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Fig. 3. Step response of lumped and distributed interconnect models. The

Elmore model shows good approximation of distribution model.

Fig. 4. Coupled interconnect model with an effective transmission line. The

resistance and capacitances are grouped for the analysis with the effective
transmission line parameters.

(a)

(b)

(c)

Fig. 5.

Coupled interconnect structure for MEDICI simulation.

the near end while the near end crosstalk noise is a sharp spike.
Thus, the worst-case crosstalk noise for practical CMOS circuit
interconnects is at the far end.
In addition, although signal coupling is due mainly to the coupling capacitance, other parameters such as the self-capacitance

Fig. 6. Two coupled line crosstalk simulation with HSPICE and interconnect
model [6]. The model presented here slightly overestimates but [6]
underestimates the crosstalk: (a) 1mm long line, (b) 5mm long line, and (c)
1-cm long line.

and self-resistance of the interconnect lines are strongly related

to signal propagation speed, risetime, and signal coupling. Thus,
the effective self-resistance and self-capacitance must be reconsidered. A simple lumped interconnect model does not match

EO et al.: A NEW ON-CHIP INTERCONNECT CROSSTALK MODEL

132

rapid charging or discharging than the lumped model. The distributed model has a shorter time constant than that of the simple
lumped model.
In the distributed circuit representation of a single line, the
time delay is not a closed-form solution but it is bounded (even
for the uniform
interconnects). In order to take the distributed transmission line effect of interconnect line into account, Wyatt gives the approximated step response as follows
[15], [16]:
-

(a)

(4)

is not a lumped-line time constant but a disHere, the

tributed-line time constant. The
- s first-order approximation is an Elmore time constant [7] which is a dominant pole
network. The Elmore time constant
approximation for an
) of an N-segment interconnect line is given by
(
-

(5)

(b)
Fig. 7. Equivalent circuit model of triple-coupled lines for model verification.
The far end of the center line is the test point for crosstalk: (a) cross section of
the triple coupled lines and (b) circuit model.

and are the line self-resistance and line self-capaciwhere

-intertance of a segment, respectively. Thus, the distributed
connect time constant ( - ) for a long line is totally different
-interconnect time constant
from the lumped
. In general, the distributed phenomena
network can be described well by 10-segment model
of the
) [17]. Since the
in both phase and magnitude (i.e.,
crosstalk voltage is a strong function of the self-capacitance
and self-resistance, the lumped interconnect model parameters
can be modified by using the Elmore time constant. That is, assuming the contribution to the system delay of the interconnect
self-resistance and self-capacitance is identical and N is greater
than ten, (5) can be represented by
-

(6)
Thus, the effective self-resistance and self-capacitance of the
distributed transmission line are considered as
and
Fig. 8. Crosstalk simulation for triple lines with two signal sources. The new
model for triple interconnect lines show good agreements with HSPICE.

the transmission characteristics of long lengths of integrated circuit interconnects. In fact, the distributed model for signal propagation on a single transmission line shows much a faster risetime than that of the lumped model. This can be shown in the
SPICE simulation in Fig. 3. The distributed model shows a more

(7)

and
can be regarded as effective lumped
That is, in (7),
values that model the distributed transmission line.
IV. SIMPLE LUMPED

MODEL OF TWO COUPLED LINE

CIRCUITS

The simplest model of interconnects is a network composed

of capacitances. However, since such model does not take the

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(a)

(b)

(c)
Fig. 9. Model and SPICE simulation for five line structures; third line victim with different switching scenarios: (a) equivalent circuits for five-line structure with
the third line victim, (b) table for different switching scenarios, and (c) model and SPICE for 1cm long lines.

interconnect resistance into account, its response will show a

waveform that has sharper risetime and more rapid falltime than
the actual response. Thus, this simple capacitance model clearly
underestimates the amount of crosstalk and gives incorrect wave
shapes. Therefore, including the previously derived effective interconnect resistance and capacitance, the lumped equivalentnetwork becomes Fig. 4. For the time being, we assume a symmetrical structure with the identical input resistances of
and identical output loads of
. The general model will be derived in the next section. Then, solving the
network equations under symmetrical conditions, the modeled

crosstalk of the two coupled lines with effective transmission

parameters will yield (see the Appendix)

(8)

EO et al.: A NEW ON-CHIP INTERCONNECT CROSSTALK MODEL

134

(a)

(b)

(c)
Fig. 10. Model and SPICE simulation for five line structures; second line victim with different switching scenarios: (a) equivalent circuits for five-line structure
with the second line victim, (b) table for switching scenarios, and (c) model and SPICE for 1-cm long lines.

where
, ,
, , and
are a driver resistance, an interconnect self-resistance, a coupling capacitance, an interconnect
self-capacitance, and a load capacitance, respectively. In general, if the signal path is very short, its crosstalk is not dominated
by interconnect lines but by gate performances. For the short
lines, the effective resistance and capacitance become meaningless and the transistor should be more accurately modeled
considering its threshold voltage [15]. However, for such short
lines, nobody is interested in crosstalk. In contrast, for moderate
length transmission lines or the long transmission lines encoun-

tered in important critical path analyses, interconnect effects

will dominate the total switching response. Under these moderate and long line conditions, the new interconnect models are
tested with SPICE simulations.
To calculate the numerical interconnect parameters, MEDICI
[18] was employed which solves Poissons equations. It assumed interconnect dimensions as shown in Fig. 5 for two coupled lines where the oxide dielectric constant is assumed as 3.9.
In this metal dielectric cross section, the load capacitance is 76
fF and transistor gate resistance is 82.76 , while the single iso-

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TABLE I
QUANTITATIVE ERRORS BETWEEN MODEL AND SPICE SIMULATION FOR THE VARIOUS STRUCTURES OF INTERCONNECTS. THE SPICE
COLUMN AND THE MODEL COLUMN SHOW THE MAXIMUM CROSSTALK VALUES

This new model is always efficient even if the capacitance

is not symmetrical. Although the physical configurations and
their terminations are different, the model can be modified for
such structures. In order to derive a general model, we consider
the th and th line of multiple coupled lines where the selfcapacitances and load capacitances of th line and th line are
not equal to each other, i.e.,
and
Letting the effective self-capacitances with load capacitance be
Fig. 11. Cross-coupled test structure (top view). G-S-G means (ground signal
ground). The squares in the ground lines are contact points between the metal
and the silicon substrate.

and
and letting the effective self-resistance with transistor on-resistance be

lated line capacitance is 1.046 pF/cm. The capacitance matrix

of two coupled lines is
pF/cm
Since the sheet resistance of metal is 3050 m /sq for todays
advanced process technology, the resistance can be calculated
based on these values. Here, we assume that the sheet resistance is 50 m /sq. Under these conditions, the simulation of
two coupled lines is shown in Fig. 6. Compared with ten-segment SPICE simulation, our model agrees much better for all
1mm and 1cm interconnects than [6]. Ref. [6] sometimes underestimates and sometimes overestimates the real value. As it
is shown, our model always overestimates the SPICE value a bit
because it assumes an abrupt risetime (i.e., unit step function).
However, this overestimation is useful since other very small
noise sources are present such as inductive coupling noise.

and
The crosstalk voltage
for the th and th line can be
derived as follows (see the Appendix)
(9)
where the parameters are shown in (9a), at the bottom of the
page.

and

However, if the driver resistances of the th and th line are equal

), the above equations are
to each other (i.e.,
reduced to the following:

V. EXTENSION TO THE MULTIPLE LINE CIRCUITS

The model in the previous section can be readily extended to
multiple line interconnect structures. In the multiple lines, the
resistances of the interconnects are approximately equal to those
of the single line if their cross sections are identical. However,
the multiple line self-capacitances are not so simple as those
of a single line. Although their cross-sectional structures are
exactly identical, the centerline self-capacitance and outer line
self-capacitance are not equal because of different electric field
distributions. Moreover, the centerline acts as shielding material
for the outer line coupling.

(10)
where

and

EO et al.: A NEW ON-CHIP INTERCONNECT CROSSTALK MODEL

Fig. 12.

136

Circuit representation of the cross-coupled structure measurement system with high-speed sampling oscilloscope (TDR/TDT measurement system).

In addition, if
(i.e., symmetrical structure), the expression is reduced to simpler expression of (8). In general, for
the multiple lines, the superposition principle can be applied to
the multiple sources. Thus, if the th line has signal source and
th line is victim line, all the parameters of th and th line are
presented with superscripts as

where
(13)
Then
(14)
Hence, the total crosstalk voltage with -independent signal
sources for n-multiple line systems becomes

where (see (10a) at the bottom of the page)

by

and

are given

(15)
The above (15) can be applied to general multiple lines and multiple source interconnect systems.

and

VI. SIMULATION-BASED VERIFICATION OF THE MODEL

It should be noticed that in the multiple lines
for two lines

(11)

for more than two lines

(12)

For a transmission line modeled as an

network, a ten-seg-ladder network can be accurate in both magnitude and
ment
phase [17]. Thus, the model in this paper has been compared
-ladder SPICE model. Note that the
with a ten-segment
analytic model has been derived under the assumption that
input excitation is a unit step function. Intuitively, the sharper

and

(9a)

and

(10a)

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IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 47, NO. 1, JANUARY 2000

Equivalent circuit model for cross-coupled structure.

risetime induces more signal coupling and crosstalk. For the

simulation and verification of model, i.e., expression (15), we
defined triple transmission lines. Triple interconnect lines are
the most widely used test circuit to predict circuit failures due to
crossstalk. Although our model can be applied to heterogeneous
structures, we assume that all the line structures have identical
conductors in order to compare with other models. The triple
lines with the same layout width and length are shown in Fig.
7. The capacitance parameters are calculated by using MEDICI
for lines that are 1 cm long. Transistor resistances are assumed
as 82.7 and load capacitances are simply modeled as gate
capacitance of 76 fF. For the structure, the triple line parameter
matrices are as follows:
cm

TABLE II
MEASURED CAPACITANCE FOR THE TEST PATTERNS. LINE LENGTH IS 8000 m
LONG. THE LINE THICKNESS AND WIDTH ARE 1.2 AND 1 m, RESPECTIVELY.
THE FRINGING CAPACITANCE WAS CALCULATED WITH MODEL IN [20]

(16)

pF cm

(17)

The capacitance matrix elements are as follows. The on-diag.

onal elements represent the self-capacitance of each line,
The off-diagonal elements show the coupling capacitance be. Using these example values, the model
tween each lines,
and SPICE show an excellent agreement as reported in Fig. 8.
Thus, our new model shows good agreement with SPICE simulation. That is, the model is within 10% error of the SPICE
simulation in the worst case. Moreover, unlike other models,
our model never underestimates the response value. Therefore,
there are no catastrophic failures due to the underestimation. In
order to illustrate our model in more detail, many different interconnect structures were analyzed. Since the metal aspect ratio
controls the interconnect resistance, the aspect ratios of 2 and
1/2 were analyzed as a thick and thin metal case. Currently, the
aspect ratio of the advanced process technologies is larger than
1.22 [19]. Thus, the thick metal aspect ratio is very aggressively
assumed to be 2 (double the metal thickness of Fig. 7). The cir-

cuit model is the same as in previous triple line model. In this

case, the resistance matrix is (16) multiplied by 1/2 and the capacitance matrix was determined by using MEDICI as follows:
pF cm
The coupling capacitance is significantly increased. For this
case, SPICE simulation and our model shows very good agreement, as summarized in Table I (thick triple). Furthermore, if
the line spacing is a half of Fig. 7 and the line thickness is the
same, the coupling capacitance becomes much larger than the
self-capacitance. In this case, the capacitance matrix is
pF cm
Even for this case, the model and SPICE simulation show good
agreement, as shown in Table I (narrow spaces). In another example of more general five-line structures, the physical line di-

pF cm

(18)

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(a)

138

itance matrix, the outer line self-capacitance and coupling capacitance are different from those of the inner lines. Thus, their
crosstalk noise is clearly different from the triple lines. Moreover, since the different switching scenarios of input line sources
may cause different crosstalk phenomena, each switching scenario must be investigated. The first case, the third line (centerline) is victim line and all other lines are switching. The equivalent circuits are shown in Fig. 9(a) and the signal transition
of input source is shown in Fig. 9(b). Note that, because of the
shielding effects, the lines within the dotted box in Fig. 9(a) have
a dominant affect on the crosstalk. The model and SPICE simulation for different lengths are compared with lines undergoing
several switching scenarios. SPICE simulation shows the worst
case crosstalk is case_A_1. As another example for the same
structure, the second line is victim line and all other lines are
switching as culprit lines. It is shown in Fig. 10. The worst case
crosstalk is case_B_1 where all the lines except line 2 go from
logic 0 to logic 1. For the comparison of different switching scenarios, SPICE simulation and crosstalk model results are shown
in Table I. Our model shows good agreements in Table I with
both case_A_1 and case_B_1 which are the worst switching scenarios. In summary, the other combinations of the switching scenarios have agreement that is almost identical to these two special cases. Thus, the proposed model can accurately estimate the
crosstalk for general multiline systems
VII. EXPERIMENTAL VERIFICATION OF THE MODEL

(b)

(c)
Fig. 14. Crosstalk model and TDT measurements of cross-coupled
interconnect lines; line length is 8000 m long. Both line thickness and width
is 1 m. (a) Line space is 0.8 m. (b) Line space is 1.0 m. (c) Line space is
1.2 m.

mensions and spaces are identical to the triple line structure of

Fig. 7. However, the electrical field distribution around the interconnects is different from the triple-line structure and the capacitance matrix for the five-line structure becomes (18), shown
at the bottom of the previous page. As we can see in the capac-

In order to solidify the model validity, high-speed TDR/TDT

measurements were performed with cross-coupled test patterns,
as shown in Fig. 11. They were designed and fabricated by using
a 0.35- m CMOS process technology. Lines are over oxide in
which the dielectric constant is assumed as 3.9. The oxide thickness is 0.8 m. The line spaces of the patterns are 0.8, 1.0, and
1.2 m, respectively. The line length is 8000 m long. The line
width and thickness of them are 1.0 and 1.2 m, respectively.
The silicon substrate is doped with the P-type of the concentration of 10 cm and it is about 300 m thick.
For the measurements, an HP54121T sampling oscilloscope
is connected to a Cascade Microtech Probe Station. The input
step pulse of the HP5121T has 100 mV magnitude and 40 ps
risetime. The far-end crosstalk of the cross-coupled structures
can be measured with the GSG (ground-signal-ground) pairs of
microwave probe tips.
The circuit representation of the measurement system is
shown in Fig. 12. However, it is inherently difficult to directly
compare the model with the test structure measurement data
because there is the terminal resistance at port 2. Thus, finding
the effective load resistance (Rx) by using one of the patterns,
the circuit can be modified into the similar circuit as in the
model. The modified circuit is shown in Fig. 13. Once the
Rx is determined, then the model can be compared with the
experimental data of other patterns. The Rx was measured
in this system. Furthermore, since the
as about 90100
field-solver-based parameter extraction cannot reflect the
process variations, the resistances and capacitances for the
test patterns were also measured with HP4275 Impedance
Analyzer. The measured RC parameters are shown in Table II.

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(A3)

Under these conditions, the model is compared with the TDT

measurement at the test point. The model and measurement
data are compared in Fig. 14. As shown in Fig. 14, they show
good agreements.

B. Derivation of (9)
For asymmetrical lines, letting

VIII. CONCLUSION
A simple crosstalk model was developed. To develop the
model, the inverter was assumed to have a linear resistance at
the driver and linear capacitance at the receiver. Since all the
transmission line coupling was induced through the distributed
coupling capacitances, effective lumped parameters were
introduced. For the model, we introduced the Elmore time
constant and derived effective transmission line parameters.
That is, the effective self-capacitance and self-resistance were
deduced from the approximated Elmore delay model so that the
model was simplified. The simple two-coupled line model was
extended to multiple lines. The extended model is also in very
simple closed-form. The results show excellent agreement with
SPICE simulation. Moreover, the simulation results of triple
lines and five lines with different switching scenarios (which
are usually used for the worst case crosstalk) verify that our
model gives excellent agreement with the segmented SPICE
model. Furthermore, in order to establish the model validity,
0.35 m CMOS process-based test patterns are designed and
TDR/TDT measurements were performed. The model shows
good agreements with the measurements. Thus, our model can
be used for the complicated high performance VLSI circuit
design since the signal integrity analysis for complex circuits
related to crosstalk can be easily predicted. Moreover, since
the model can be readily implemented into the existing CAD
models, it can be directly used in the industry.
APPENDIX

and
, of the node

,
in Fig. 4

(A1)
Then, the far end crosstalk voltage is given by

(A2)
Therefore, the time domain signal of (8),
the inverse Laplace transform.

in Fig. 4, the
fore

is given in (A3) at the top of the page. There-

(A4)
Now, combining (A3) with (A4),

becomes
(A5)

where the denominator of (A5) is

(A6)
Thus, letting the roots of (A6) to be
be represented as

and , the

can
(A7)

, can be deterThe time domain crosstalk noise of (9),

mined by performing the inverse Laplace transform of (A7).
REFERENCES

A. Derivation of (8)
Letting
the frequency-domain voltage,
is given by

and

, is found by

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Yungseon Eo received the B.S. and M.S. degrees

in electronic engineering from Hanyang University,
Seoul, Korea, in 1983 and 1985, respectively, and
the Ph.D. degree in electrical engineering from the
University of Florida, Gainesville, in 1993.
From 1986 to 1988, he worked at Korea Telecommunication Authority Research Center, Seoul,
where he performed telecommunication network
planning and software design. From 1993 to
1994, he performed s-parameter-based BJT device
characterization and modeling for the high-speed
circuit design at Applied Micro Circuits Corporation, San Diego, CA. From
1994 to 1995, he was with the Research and Development Center of LSI
Logic Corporation, Santa Clara, CA, where he had worked in the area of
signal integrity characterization and modeling of high-speed CMOS circuits
and interconnects. Since 1995, he has been with the Department of Electronic
Engineering as an Assistant Professor of Hanyang University, Ansan, Korea.
His research interests are high-frequency characterization and modeling of
integrated circuits and interconnects, and high-speed VLSI circuit packaging.

140

William R. Eisenstadt (S78M84SM92) received the B.S., M.S., and Ph.D. degrees in electrical
engineering from Stanford University, Stanford, CA,
in 1979, 1981, and 1986, respectively.
In 1984, he joined the faculty of the University
of Florida, Gainesville, where he is now an Associate Professor. His research is concerned with highfrequency characterization, simulation, and modeling
of integrated cicuit devices, packages, and interconnect. In addition, he is interested in large-signal microwave-circuit and analog-circuit design.
Dr. Eisenstadt received the NSF Presidential Young Investigator Award in
1985.

Ju Young Jeong was born in Seoul, Korea, in 1958.

He received the B.S. degree in electronic engineering
from Sogang University, Seoul, in 1982, the M.S. degree in electrical engineering from Florida Institute
of Technology, Melbourne, in 1984, and the Ph.D. degree in electrical engineering from Rensselaer Polytechnic Institute, Troy, NY, in 1990.
From 1990 to 1991, he was with Samsung
Advanced Institute of Technology, Kihung, Korea,
where he developed low-temperature electronic
devices. From 1991 to 1994, he was with Pan
Korea Corporation as a director of research and development. In 1995, he
joined the University of Suwon, Kyungki-do, Korea, as an Assistant Professor
of electronic engineering. His current research interests include submicron
MOSFET device fabrication technique and related physics and flat panel
plasma display driving system.

Oh-Kyong Kwon (S83M88) received the B.S. degree in electronic engineering from Hanyang University, Seoul, Korea, in 1978 and the M.S. and Ph.D.
degrees in electrical engineering from the Stanford
University, Stanford, CA, in 1986 and 1988, respectively.
From 1987 to 1992, he was with the Semiconductor Process and Design Center, Texas
Instruments Inc., Dallas, TX, where he was engaged
in the development of multichip module (MCM)
technologies and smart power integrated circuit
technologies. In 1992, he joined Hanyang University as an Assistant Professor
in the Department of Electronic Engineering, and was promoted to an Associate
Professor in 1996. His research interests include interconnect and electrical
noise modeling for system-level integration, wafer-scale chip size packages,
smart power integrated circuit technologies and the driving methods and
circuits for flat panel displays. He has authored and coauthored more than 40
papers in international journals and 21 U.S. patents.
Dr. Kwon has served as an IEDM subcommittee member of solid state devices
since 1997. He served on the organizing committee for the International Display
Research Conference in 1998.