044 LAB03 Single Transistor Amplifier

M044 Laboratory 03 Intro to Power Amplifiers
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M044 Laboratory 3 Single Transistor Amplifier

Contents
Attachments
ADS Workspace contents table

Introduction
1 Extraction of S Parameters From Component Model
2 Annotating S Parameters out of Simulation
3 Matching Input Port on Single Frequency with L Network
4 Matching Output Port on Single Frequency with L Network
5 Matching Output Port with PI Network
6 Single Transistor Amplifier
7 Experiment Match with Band Pass Filters : Filters-Bandpass
8 Experiment Match with Band Pass Filters : Smart Components
9 Amplifier with 2 Parallel Transistors
9.1 Without Couplers
9.2 With Built-In Wilkinson
9.3 With Tapered TL
9.4 Changing Transistor
9.5 With Pre-driver Same Transistor
References
1. FLL200IB-2 transistor datasheet

2. Laboratory guide text section 1
3. s_parameters_FLL200IB2_680MHz.txt
4. s_parameters_650M_700M_real_imag.txt
5. FLL200IB2.mat
6. cell_1.iff
7. Laboratory guide text for section 2
8. what happens when looking the wrong direction
9. Literature references [POZAR][GONZ][MEDLEY]
10. packed workspace wrkspc_Lab03_singleTRTamp
15.- Fujitsu Semiconductors contact details
20. checking_stability.m
ADS and this text AVAILABLE FROM

DROPBOX and SCRIBD
SCRIBD: search for workspace name
Please only consider cells

circuits
and graphs
clearly tagged with their respective icons and their workspace path
next to each icon. I am sure the reader understands that cleansing this workspace down to only the cells circuits and .dds detailed
in this text would take time needed on other tasks.
Red font for pending points I need assistance on.
I have also numbered questions along this text that I consider important for me to be solve in order to gain expertise to be
considered as candidate for ADS certification.
MATLAB code % MATLAB comments
ADS WORKSPACES CONTENT TABLE
wrkspc_Lab03_singleTRTamp
_________________________________________________________________________________________________
John Bofarull Guix # 6453430 jb01183@surrey.ac.uk jgb2012@sky.com
attached: 12 documents as detailed in header
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INTRODUCTION
The purpose of this lab is to show how to set up many of the simulations required in the design of a power amplifier.
The frequency of operation will be 680MHz. The features demonstrated include
matching,
use of Wilkinson combiner and
increasing dynamic range.
Since Laboratory 3 is the preamble to the 1st Assignment, I have included questions and explorations that I really need clarified in order to score
in the assignment, as well as to increase ADS know-how also to be considered as candidate for ADS certification by already certified professor Mr
Aaen.
Thanks for time and attention helping me increase expertise through this enhanced Laboratory assignment over this wonderful tool that ADS is.
EXTRACTION OF S PARAMETERS FROM COMPONENT MODEL

.. \wrkspc_Lab03_singleTRTamp\cell_1
Attachment 01 FLL200IB-2 transistor datasheet from manufacturer link1

and link2.
Laboratory guide text section for this point moved to attachment 02.
Observation: the manufacturer does not supply Smith chart plot of any
S parameter below 1.5GHz and the really abridged S parameters table
shows 1st measurement at 500MHz and next measurement at 1GHz,
not precisely generous revealing S parameters, which seems to be a
common practice among RF power transistor S parameters datasheets
made public over the internet.
The
online
S
parameters
http://www.fcsi.fujitsu.com/sparam/data/FLL200IB-1.s2p
have been removed from the Internet. Tried contacting Fujitsu
semiconductors by email asking for SPICE model with more parameters
contact details attachment 15.
Observation: the chosen transistor has the highest I_DS=4.8 Amperes
available from the ADS local library.
.. \wrkspc_Lab03_singleTRTamp\cell_1\schematic
In attachment 20
MATLAB preflight check
script
checking_stability.m
according to [POZAR].
Check using S
parameters from 650MHz
to 700MHz.
RESULT:
FL200IB-2 datasheet
satisfies K>1 and ||<1
along [650 700] MHz
cell1.dds
||
2.455690293791103
2.465129259840324
2.474626050123512
2.484181263207540
2.493795504015673
2.503469383950904
2.513203521021564
2.522998539968183
2.532855072392898
2.542773756889909
2.552755239178566
0.839398434120398
0.838851733257579
0.838305079867575
0.837758474319088
0.837211916980958
0.836665408222161
0.836118948411808
0.835572537919141
0.835026177113540
0.834479866364511
0.833933606041697
|s11| |s22| in dB, |s11| linear, and s11 linear on Smith Chart
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cell1.dds
cell1.dds
cell1.dds
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|s21| dB, |s21| linear, (s21)
|s12| dB, |s12| linear, (s12)
Comment:
Also of importance for RF transistors is to know
consumption and DC levels. The ADS chosen model
simplifies
V_DS to just 10V
I_DS to 4.6A
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s11 s22 in degree, |s22| linear, and s22 linear on Smith Chart
.. \wrkspc_Lab03_singleTRTamp\FET_IV_Gm_PowerCalcs\schematic
temperature to 27C
which seems understandable when wanting

students to focus on the RF aspects of the amplifier
design, but at the same time it prevents
optimization playing with such parameters.
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I have also learnt how to build a simple table with all S parameters mod arg, but havent found a way to build such table with real imag yet:
.. \wrkspc_Lab03_singleTRTamp\FET_IV_Gm_PowerCalcs\ FET_IV_Gm_PowerCalcs.dds
ADS has the FET_IV_Gm_PowerCalcs template available from
the Schematic window menu: DesignGuide > Amplifier > DC and
Bias Point Simulations > FET I-V curves, class A power Eff, Load,
Gm vs Bias
Observation: The above inspection of the FLL200IB-2 transistor ADS model

reveals quite a limited amount of SPICE parameters compared to the SPICE
model of transistor FLC301XP.
This point is mentioned because as attempting to gain as much power as
possible out of the transistor on the lower margin of the transistor bandwidth
while keeping stability and avoiding too much noise indeed, some literature
sources mention that the S parameters are not that accurate as expected
when the output power show distortion.
Perhaps then is when a more detailed SPICE model may be useful but at this
point it is not available.
Observation: I replaced FLC301XP with FLL200IB-2 and got exactly same
consumption figures, because I did not find the equivalent FET model block
for FLL200IB-2 so ADS applied the FLC301XP model block to the FLL200IB-2
circuit component.
Exploration: Because of such simple
transistor SPICE model, the noise simulation
in the S-parameters block cannot be used
because the simulation throws a warning
regarding temperature discrepancy: Since I
dont know how to include Temperature in
this transistor model I cannot develop this
point any further.
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ANNOTATING S PARAMETERS OUT OF SIMULATION
You should then easily be able to obtain the S-parameters s11 and s22 for 680MHz which can be applied to matching. You
should note these down.
In the simulation window, 1st selecting all s linear parameters,
File > Export > Write selected Item to tab delimited ASCII. Result in file s_parameters_FLL200IB2_680MHz.txt in attachment 03.
RESULT:
freq
mag(S(1,1))
6.79999999999999980E8
freq
phase(S(1,1))
6.79999999999999980E8
freq
mag(S(2,2))
6.79999999999999980E8
freq
phase(S(2,2))
6.79999999999999980E8
9.41480000000000140E-1
1.46536000000000000E2
8.87640000000000030E-1
1.61672000000000020E2
freq
mag(S(2,1))
6.79999999999999980E8
freq
phase(S(2,1))
6.79999999999999980E8
freq
mag(S(1,2))
6.79999999999999980E8
freq
phase(S(1,2))
6.79999999999999980E8
1.04556000000000000E0
4.93439999544557840E1
-6.37999999999999990E0
-6.37999999999999990E0
Because the Zin block needs a complex(real,imag) input let's add real and imag for all s parameters to the ASCII export:
File > Export > Write selected Item to tab delimited ASCII: s_parameters_650M_700M_real_imag.txt in attachment 04.
RESULT:
freq
real(S(1,1))
6.79999999999999980E8
freq
imag(S(1,1))
6.79999999999999980E8
freq
real(S(2,2))
6.79999999999999980E8
freq
imag(S(2,2))
6.79999999999999980E8
-7.85413166722421780E-1
5.19144245792108630E-1
-8.42611725840274950E-1
2.79124074698821630E-1
s11_real_680M = -0.785431660000000;
s11_imag_680M = 0.519144245000000;
s11_680=complex(s11_real_680M,s11_imag_680M);
freq
real(S(2,1))
6.79999999999999980E8
freq
imag(S(2,1))
6.79999999999999980E8
freq
real(S(1,2))
6.79999999999999980E8
freq
imag(S(1,2))
6.79999999999999980E8
Z0=50;
Zin_680=Z0*(1+s11_680)./(1-s11_680)
6.81199075472449600E-1
7.93198293729556700E-1
4.69076794785627000E-3
-5.24496005098489350E-4
Zin_680 =
1.643165750828499 +15.016273433890269
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Exploration: Attempt to export to MATLAB variables file format

FLL200IB2.mat attachment 05.
in the Palette named 'Simulation-HB' there is a block to export output to
MATLAB shown here on the right hand side added to cell_1 schematic.
MATLAB R2016a fails import claiming
Pending: this may be a student version limitation, pending to ask

KEYSIGHT
Exploration: how to export the SPICE Netlist
In the schematic window: File > Export >
this is how ADS circuit netlist looks like, that is not readable
but not encrypted
with options
Pending: this may be a student version limitation, pending to ask KEYSIGHT
the S parameters seem to be included in the cell_1.iff

attachment 6 export but direct inspection of the file is not
readable.
.. \wrkspc_Lab03_singleTRTamp\cell_1_fullband.dds
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Observation: Running a full band sweep the S parameters Smith Chart resembles those provided in FLL200IB-2 datasheet, why did the manufacturer
omit data on Smith charts below 1GHz?
Observation: So, although it is obvious that this transistor has been developed to best amplify @ 2.1GHz it may be suitable for broadband or
narrowband amplifying along other bands. The 680MHz band the designer (I am not the designer, just the post grad student completing this ADS
laboratory assignment) may have in mind an amplifier for a mobile communications base stations.
According to the UK Frequencies Allocation Table from OFCOM: region 1 [470 790] MHz for broadcast 5.149 5.291A 5.294 5.296 5.300 5.302(sup)
5.304 5.306 3.111A 5.312 5.312A, region 2 [614 698] MHz assigned to Broadcasting Fixed Mobile (Base Stations) 5.293 5.309 5.311A and region 3
[610 890]MHz Fixed mobile 5.313A 5.317A and broadcasting 5.149 5.305 5.306 5.307 5.311A 5.320.
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MATCHING INPUT PORT ON SINGLE FREQUENCY WITH L NETWORK

Laboratory guide text for this section moved to

attachment 07.
Refined Parameter Sweep step down to 0.05 to get
closer to real(Zin)=50
.. \wrkspc_Lab03_singleTRTamp\cell_2_C1_match.dds
C1 may take values 13.15 pF or 17.6 pF, both bring real(Zin)=Z0. Now modifying the same circuit
.. \wrkspc_Lab03_singleTRTamp\cell_2_C2
.. \wrkspc_Lab03_singleTRTamp\cell_2_C2_match.dds
RESULT: C1=13.15pF C2=3.55pF
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.. \wrkspc_Lab03_singleTRTamp\cell_2_L1
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.. \wrkspc_Lab03_singleTRTamp\cell_2_L1.dds
RESULT: C3=17.6pF L1=15.6nH
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MATCHING OUTPUT PORT ON SINGLE FREQUENCY WITH L NETWORK
For output port match, the Laboratory guide wants us to follow a different method: directly plug a shunt capacitor 10pF, find the value of the
series inductor and then tweak the output capacitor and recalculate L repeatedly.
At the output you should connect a
capacitor in parallel with the terminal
(which you should initially set to about
10pF) and a series inductor, with L_out
nH. As before you will now need to set
L_out as the varying inductance to see how
the output match is changed. Again the
frequency should be fixed to a single point
of 680MHz. Your step size should be 0.1
from 0.1 to 10.
To help best select the appropriate values
of Capacitance and simulate the best
L_out, you should set up the results to plot
both the Smith chart and also s11 in dB
versus L_out. That way, by varying the
output capacitance manually, it will
what happens if watching the wrong direction in attachment 08. Attachment 09 [POZAR][GONZ][MEDLEY]
enable you to keep re-simulating and
gaining a result that will find an optimum on Smith chart regions that each L-network can and cannot match.
value of L_out with a fixed capacitor value
to give an output match.
.. \wrkspc_Lab03_singleTRTamp\cell_3_series_L1
.. \wrkspc_Lab03_singleTRTamp\cell_3_series_L1.dds
trying different values of C3 and C4 I manage to move the Smith chart plot and bring reasonably close to origin the marker, for then fine tune with
built-in cell21
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L=3.5 nH and C=10pF make imag(Zin)=0 and reading the Smith chart real(Zin)=
Getting closer L=0.65nH and C=20pF, marker m1 on Smith chart quite close to origin and there is reactive left behind.
L=0.9nH C=18.5pF
refining the step from 0.05 to 0.005
RESULT: L=0.895 nH C = 18.5 pF

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MATCHING OUTPUT PORT WITH PI NETWORK

.. \wrkspc_Lab03_singleTRTamp\cell_4.dds
Yet, the sharp edge of imag(Zin) implies a lot of undesired sensitivity to small changes of the component value. So I am adding a 3rd component,
kind of pi match network at the output.
By testing different values of C3 and C4 in the following circuit, I manage to move the Smith chart 680MHz marker reasonably close to origin, for
then fine tune with ADS Tune function in cell21
C30[pF]
5
L30[nH] on dB(s(1,1))
1.81
L30[nH] on Smith Chart

2.48
C31[pF]
10
C30[pF]
10
L30[nH] on dB(s(1,1))
1.81

2.48
C31[pF]
10
C30[pF]
10
L30[nH] on dB(s(1,1))
1.81

2.48
C31[pF]
15
So the optimum combination cannot be far from C3@10pF L1 between 1.81nH and 2.48nH and C4@12pF
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Refl=-.8426+1j*.2791
Z0=50;Zin=Z0*(1+Refl)/(1-Refl)
Zin =
3.053902370344761 + 8.036114268730719i
tuned values stored from Tune window
.. \wrkspc_Lab03_singleTRTamp\cell_4_1_L10.dds
fine tuning with ADS function Tune has as RESULT:
C31=11.2pF C30=11pF L30=1.6nH
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SINGLE TRANSISTOR AMPLIFIER

Now that you have found the optimum values, you can construct a full amplifier as
below with your optimised matching networks and test its S-parameters to see that
it can resonate at 680MHz.
You may find however, that it turns out to be slightly off the actual desired
resonance, in which case you can make minor adjustments (i.e. tweaks) to the input
network. Be careful only to tweak it a small amount because you will otherwise
disrupt the whole amplifier if you move any one too much.
comment: to avoid mixing components I have labelled them according to the area they are located:
gen match: C1=13.5pF C2=3.55pF load match: L10=0.895 nH C10 = 18.5 pF
gen match: C3=17.6pF L1=15.6nH load match: L10=0.895 nH C10 = 18.5 pF
or
gen match: C1=13.5pF C2=3.55pF load match (pi): C30=11pF L30=1.6nH C31=11.3pF
gen match: C3=17.6pF L1=15.6nH load match (pi): C30=11pF L30=1.6nH C31=11.3pF
C30 next to transistor C31 next to load
In the past I learnt about applying component numerals, not solely sequentially, but hopping decades or hundreds to precisely avoid mixing
components, that may happen when PCBs become populated with many components.
.. \wrkspc_Lab03_singleTRTamp\cell_3_2
Since the Laboratory text did not make any comment regarding the bias I have included DC chokes VDS and VGS from an ADS design template.
Applying gen match: C1=13.5pF C2=3.55pF load match: L=0.895 nH C = 18.5 pF
comment: component numerals do not coincide as now C1 is closer to generator while C1 in the
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.. \wrkspc_Lab03_singleTRTamp\cell_3_2.dds
Checking the other input set
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Since Load and Source are fairly matched, the expression

of transducer gain
is reduced to s21*conj(s21) that at 680MHz is a modest GTmax_dB_680M=10*log10(s21_680M*conj(s21_680M))

= 0.3869 dB
RESULT:
abs(s11') [dB]
-27.457
abs(s22')
-21.828
G[dB]
16.581
GTmax=10*log10(s21*conj(s21)) [dB]
0.3869
Using pi network found in point 5 cell21
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Getting there, in most of GSM 3G Radio Access base stations port adaptation specifications hang around -20dB, in some places a bit more stringent,
in some other places -19dB may be accepted by the operator. So far I have a lot of adaptation for s11 (IDU) but a bit short for s22 (ODU mast
Antenna).
Ideally the markers should be on as flat as possible line, but with 2 or 3 components per matching network, operator time tuning the device is also
a cost variable to take into account.
RESULT:
L1 [nH]
15.5
C1 [pF]
18.2
C30 [pF]
14.7
L30 [nH]
2.39
C31 [pF]
10.6
GAIN 10*log10(s21*conj(s21))
EXPERIMENT MATCH WITH BAND PASS FILTER : FILTERS-BANDPASS

..\wrkspc_Lab03_singleTRTamp\cell_3_5
these filters out-of-the-box from palette seem convenient but dont match a bit
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EXPERIMENT MATCH WITH BAND PASS FILTERS : SMART COMPONENT

Question: again this not matching a bit, would like to know what step I
am missing / what I am doing wrong
tried N=9 and the Design Wizard refused to start, N=5 seems ok
the sub-circuit automatically generated by the smart-components wizard but doesnt seem to work at all
pending question: while on the left graph dB(S(2,1))=13.709 on the right hand side Smith Chart, S(2,1)= 4.847 / 10.483 that is the ADS display
window to show mod(s21)=4.847 angle(s21)=10.483 yet when I check (4.847^2+10.483^2)^.5 ans = 11.549315910477123 which is not the
expected 13.7 dB.
Also checked ((4.847*cos(10.483))^2+(4.847*sin(10.483))^2)^.5=4.847 this does not make sense either.
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AMPLIFIER WITH 2 PARALLEL TRANSISTORS
Finally, you can double the maximum output power by re-constructing the
Wilkinson combiner that you constructed in the previous lab and adding it into a
new amplifier design. To do this you would be safest to undertake the following
steps.
1.
2.
3.
4.
5.
6.
Save your work on the amplifier to access it again later.

If your Wilkinson combiner is in a separate project, close down your current
project and open the project where your Wilkinson combiner is.
Note down the transmission line specs from your Wilkinson combiner
including the MSUB details and the MLIN dimensions.
Re-open the project with your amplifier if you need to.
Make a new file where you can make two amplifiers, using copy and paste as
you would do with a drawing package.
Add in the components for the Wilkinson combiner at the output and input.
You should then end up with a construction like that shown below. Values have been
covered up where necessary. You can likewise test the S-parameters. If you have
time you should also change the dimensions slightly on one of the Wilkinson
transmission lines, which will create phase imperfections and then see what impact
it has on the gain as well as the reflection coefficients.
9.1.- WITHOUT COUPLERS
Just for simulation purposes
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9.2.- WITH BUILT-IN WILKINSON

..\wrkspc_Lab03_singleTRTamp\cell_3_11_2_builtinWLK
..\wrkspc_Lab03_singleTRTamp\cell_3_11_2_builtinWLK
removed DC decopling 4 capacitors, no effect same Gain.

Changed both Wilkinsons option ResponseType to Binomial and Chebyshev no effect on Gain
changed WLK options Rmax from 0.1 down to 0.01, Wgap from 50mil to 500mil
narrowed markers A and B to [650 700] and moved marker m2 from somewhere 800Mhz down to 675MHz, no effect
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..\wrkspc_Lab03_singleTRTamp\DA_WDCoupler
9.3.- WITH TAPERED TL

..\wrkspc_Lab03_singleTRTamp\cell_3_11_3_T
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..\wrkspc_Lab03_singleTRTamp\cell_3_11_3_T
increasing V_DS from 5V to 15V doesnt change Gain. It may be transistor model limitation.
The DC sweep has been limiting V_DS so far, even if only a simulation its good bear in mind that with Voltage and current
heat comes up and faulty or badly handled transistor will stop working.
9.4.- CHANGING TRANSISTOR

..\wrkspc_Lab03_singleTRTamp\
DONT HAVE EQUIVALENT TRANSISTOR
Question: the chosen transistor is the only one with I_DS=4.8 Amperes from the local ADS library, how do I get an equivalent transistor model
that can be readily embedded in the circuit?
Question: how can one download the Samsung Samtec and Samyoung libraries, that apparently would be available from
http://www.keysight.com/main/editorial.jspx?cc=GB&lc=eng&ckey=1490117&id=1490117 but these 3 tags do not seem to have link like the rest
of the table tags do have.
Question: How to use NXP SimKits mentioned in http://www.nxp.com/products/software-and-tools/models-and-test-data/compact-modelssimkit:COMPACT-MODELS
Question: how do I have the Raytheon transistor model and transistor block working, rewording how to fix the following compilation error
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9.5.- WITH PREDRIVER SAME TRANSISTOR

..\wrkspc_Lab03_singleTRTamp\cell_3_11_5_DRV
..\wrkspc_Lab03_singleTRTamp\cell_3_11_5_DRV
Now it works! pumping more (its a FET but the analogy for BJT
helps) at the inlet helps almost double in dB the gain, at the cost
of a 3rd transistor, but although no line-up budget, one may
guess that the output stage transistors, the transistors in parallel
need less Dynamic range.
Question: would like to be proficient at applying these simulations

Question: how, if possible, may one extract a list of all cells, dds,
symbols, everything in a workspace from within ADS, wthiout going to
the actual workspace folder, run cmd, dir *.* /o:e /b > list.txt
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REFERENCES
[POZAR]
Microwave Engineering, David Pozar, 4th ed ISBN 978-0-470-63155-3
[GONZ]
Microwave Transistor Amplifiers, Guillermo Gonzalez, 2 nd ed, Prentice Hall 1996 ISBN -0-13254335-4
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ATTACHMENTS
1.- FUJITSU RF transistor FLL200IB-2 datasheet in attached separate file
2.- Laboratory Guide section 1
Load ADS as normal. Before you do anything further, please note that you will have to set up the library to be able to use the necessary transistor in this setup. In
the project manager window click on the new workspace button as indicated below by the red circle.
Now a setup wizard will follow. You must note the following steps carefully:
1.
2.
3.
For the first page you dont need to do anything. Therefore click Next.
For the second page, enter a suitable workspace name like Amplifiers_wrk to create workspace directories. Then click Next.
You will then come to a page that looks like the one below. Tick the box:
S_Parameter_vendor_kit
$HPEESOF_DIR/custom/c omponentLibsS_Pa and
click next. -
4. For the remaining stages just click Next every time and then click Finish.
You have now set up a workspace just as you have done for previous labs. Open a schematic design window just as you have done before in the previous lab, which
you can do by going to Window->New Shcematic.
In the schematic window, click Insert->Component->Component Library
You will then see a window that looks very much like this one below. In the left hand list of libraries, click on Read Only Libraries as shown below where the
blue bar is.
In the search box, you can now type in the required transistor you are going to simulate. The one you require is the following:
sp_fuj_FLL200IB-2_19920501
As you type the above in, you should find your required transistor appears on the list. Click on it, then drag it over to the schematic window. As you move the
pointer onto the canvas, a ghost image of the
transistor like this: moves with it. Place it in a convenient location by letting go of the mouse button. The biasing of the transistor is all internal, so there is no need
to worry about that. Next you will need to test its S-parameters so that the data found can be applied to determine a matching network. In a way that you did in the
previous exercise, you should set up your S-parameter test as follows.
_________________________________________________________________________________________________
25 / 35
3.-
___
12/11/2016 11:44.
S parameters 650MHz to 700MHz module angle
file: s_parameters_FLL200IB2_680MHz.txt
freq
mag(S(1,1))
6.50000000000000000E8
9.41900000000000050E-1
6.54999999999999980E8
9.41829999999999860E-1
6.59999999999999960E8
9.41759999999999840E-1
6.65000000000000040E8
9.41690000000000000E-1
6.70000000000000020E8
9.41620000000000170E-1
6.75000000000000000E8
9.41549999999999980E-1
6.79999999999999980E8
9.41480000000000140E-1
6.84999999999999960E8
9.41409999999999950E-1
6.90000000000000040E8
9.41340000000000110E-1
6.95000000000000020E8
9.41269999999999740E-1
7.00000000000000000E8
9.41200000000000080E-1
freq
phase(S(1,1))
6.50000000000000000E8
6.54999999999999980E8
6.59999999999999960E8
6.65000000000000040E8
6.70000000000000020E8
6.75000000000000000E8
6.79999999999999980E8
6.84999999999999960E8
6.90000000000000040E8
6.95000000000000020E8
7.00000000000000000E8
1.48330000000000030E2
1.48030999999999980E2
1.47732000000000060E2
1.47433000000000010E2
1.47134000000000010E2
1.46835000000000000E2
1.46536000000000000E2
1.46237000000000040E2
1.45938000000000010E2
1.45639000000000010E2
1.45339999999999980E2
freq
mag(S(2,2))
6.50000000000000000E8
6.54999999999999980E8
6.59999999999999960E8
6.65000000000000040E8
6.70000000000000020E8
6.75000000000000000E8
6.79999999999999980E8
6.84999999999999960E8
6.90000000000000040E8
6.95000000000000020E8
7.00000000000000000E8
8.90700000000000180E-1
8.90189999999999950E-1
8.89680000000000250E-1
8.89170000000000190E-1
8.88660000000000140E-1
8.88149999999999910E-1
8.87640000000000030E-1
8.87130000000000150E-1
8.86620000000000100E-1
8.86110000000000220E-1
8.85600000000000340E-1
freq
phase(S(2,2))
6.50000000000000000E8
6.54999999999999980E8
6.59999999999999960E8
6.65000000000000040E8
6.70000000000000020E8
6.75000000000000000E8
6.79999999999999980E8
6.84999999999999960E8
6.90000000000000040E8
6.95000000000000020E8
7.00000000000000000E8
1.62410000000000030E2
1.62287000000000000E2
1.62164000000000000E2
1.62041000000000010E2
1.61918000000000010E2
1.61795000000000000E2
1.61672000000000020E2
1.61549000000000010E2
1.61426000000000030E2
1.61302999999999970E2
1.61180000000000010E2
freq
mag(S(2,1))
6.50000000000000000E8
6.54999999999999980E8
6.59999999999999960E8
6.65000000000000040E8
6.70000000000000020E8
6.75000000000000000E8
6.79999999999999980E8
6.84999999999999960E8
6.90000000000000040E8
6.95000000000000020E8
7.00000000000000000E8
1.06529999999999990E0
1.06200999999999990E0
1.05871999999999990E0
1.05542999999999990E0
1.05213999999999990E0
1.04884999999999980E0
1.04556000000000000E0
1.04227000000000030E0
1.03898000000000000E0
1.03569000000000000E0
1.03240000000000000E0
freq
phase(S(2,1))
6.50000000000000000E8
6.54999999999999980E8
6.59999999999999960E8
6.65000000000000040E8
5.12699999544557720E1
5.09489999544557650E1
5.06279999544557760E1
5.03069999544557510E1
_________________________________________________________________________________________________
26 / 35

6.70000000000000020E8
4.99859999544557620E1
6.75000000000000000E8
4.96649999544557730E1
6.79999999999999980E8
4.93439999544557840E1
6.84999999999999960E8
4.90229999544557680E1
6.90000000000000040E8
4.87019999544557700E1
6.95000000000000020E8
4.83809999544557810E1
7.00000000000000000E8
4.80599999544557650E1
freq
phase(S(1,2))
6.50000000000000000E8
6.54999999999999980E8
6.59999999999999960E8
6.65000000000000040E8
6.70000000000000020E8
6.75000000000000000E8
6.79999999999999980E8
6.84999999999999960E8
6.90000000000000040E8
6.95000000000000020E8
7.00000000000000000E8
-5.44999999999999930E0
-5.60499999999999860E0
-5.76000000000000070E0
-5.91500000000000090E0
-6.07000000000000030E0
-6.22500000000000140E0
-6.37999999999999990E0
-6.53499999999999840E0
-6.68999999999999770E0
-6.84499999999999800E0
-6.99999999999999910E0
freq
mag(S(1,2))
6.50000000000000000E8
6.54999999999999980E8
6.59999999999999960E8
6.65000000000000040E8
6.70000000000000020E8
6.75000000000000000E8
6.79999999999999980E8
6.84999999999999960E8
6.90000000000000040E8
6.95000000000000020E8
7.00000000000000000E8
4.59999999999999960E-3
4.62000000000000100E-3
4.63999999999999970E-3
4.66000000000000010E-3
4.68000000000000060E-3
4.69999999999999930E-3
4.71999999999999890E-3
4.74000000000000200E-3
4.75999999999999980E-3
4.77999999999999940E-3
4.80000000000000160E-3
___
12/11/2016 11:44.
4.- S parameters 650MHz to 700MHz real imag

file: s_parameters_650M99_700M_Re_Imag.txt
freq
real(S(1,1))
6.50000000000000000E8
-8.01638024996697140E-1
6.54999999999999980E8
-7.98987057248149310E-1
6.59999999999999960E8
-7.96314717472233720E-1
6.65000000000000040E8
-7.93621081673978510E-1
6.70000000000000020E8
-7.90906226427747420E-1
6.75000000000000000E8
-7.88170228875063120E-1
6.79999999999999980E8
-7.85413166722421780E-1
6.84999999999999960E8
-7.82635118239087380E-1
6.90000000000000040E8
-7.79836162254874310E-1
6.95000000000000020E8
-7.77016378157914290E-1
7.00000000000000000E8
-7.74175845892409060E-1
freq
imag(S(1,1))
6.50000000000000000E8
6.54999999999999980E8
6.59999999999999960E8
6.65000000000000040E8
6.70000000000000020E8
6.75000000000000000E8
6.79999999999999980E8
6.84999999999999960E8
6.90000000000000040E8
6.95000000000000020E8
7.00000000000000000E8
4.94522079263802810E-1
4.98661640042566570E-1
5.02787000962750060E-1
5.06898051705295580E-1
5.10994682357674710E-1
5.15076783416832470E-1
5.19144245792108630E-1
5.23196960808154450E-1
5.27234820207836210E-1
5.31257716155122670E-1
5.35265541237966240E-1
freq
real(S(2,2))
6.50000000000000000E8
6.54999999999999980E8
6.59999999999999960E8
6.65000000000000040E8
6.70000000000000020E8
6.75000000000000000E8
6.79999999999999980E8
6.84999999999999960E8
6.90000000000000040E8
6.95000000000000020E8
7.00000000000000000E8
-8.49053920229632730E-1
-8.47988294269098470E-1
-8.46919426518678260E-1
-8.45847326380643060E-1
-8.44772003269071630E-1
-8.43693466609783020E-1
-8.42611725840274950E-1
-8.41526790409658610E-1
-8.40438669778594160E-1
-8.39347373419227340E-1
-8.38252910815125500E-1
_________________________________________________________________________________________________
27 / 35

freq
imag(S(2,2))
6.50000000000000000E8
6.54999999999999980E8
6.59999999999999960E8
6.65000000000000040E8
6.70000000000000020E8
6.75000000000000000E8
6.79999999999999980E8
6.84999999999999960E8
6.90000000000000040E8
6.95000000000000020E8
7.00000000000000000E8
2.69172677927557610E-1
2.70839599915863040E-1
2.72503187844240640E-1
2.74163435480952080E-1
2.75820336619256690E-1
2.77473885077437600E-1
2.79124074698821630E-1
2.80770899351799840E-1
2.82414352929852530E-1
2.84054429351567080E-1
2.85691122560659540E-1
freq
real(S(2,1))
6.50000000000000000E8
6.54999999999999980E8
6.59999999999999960E8
6.65000000000000040E8
6.70000000000000020E8
6.75000000000000000E8
6.79999999999999980E8
6.84999999999999960E8
6.90000000000000040E8
6.95000000000000020E8
7.00000000000000000E8
6.66506226572780310E-1
6.69078930692778510E-1
6.71602005480083970E-1
6.74075502306971150E-1
6.76499474996352570E-1
6.78873979815965180E-1
6.81199075472449600E-1
6.83474823105324610E-1
6.85701286280858560E-1
6.87878530985837600E-1
6.90006625621229740E-1
freq
imag(S(2,1))
6.50000000000000000E8
6.54999999999999980E8
6.59999999999999960E8
6.65000000000000040E8
6.70000000000000020E8
6.75000000000000000E8
6.79999999999999980E8
6.84999999999999960E8
6.90000000000000040E8
6.95000000000000020E8
7.00000000000000000E8
8.31043645026970520E-1
8.24741550185879650E-1
8.18436793304852020E-1
8.12129732302422270E-1
8.05820724435441350E-1
7.99510126282858380E-1
7.93198293729556700E-1
7.86885581950225800E-1
7.80572345393286500E-1
7.74258937764857790E-1
7.67945712012772490E-1
freq
real(S(1,2))
6.50000000000000000E8
6.54999999999999980E8
6.59999999999999960E8
6.65000000000000040E8
6.70000000000000020E8
6.75000000000000000E8
6.79999999999999980E8
6.84999999999999960E8
6.90000000000000040E8
6.95000000000000020E8
7.00000000000000000E8
4.57920551846369680E-3
4.59791122780755050E-3
4.61657271879323260E-3
4.63518956354960210E-3
4.65376133461173770E-3
4.67228760492619610E-3
4.69076794785627000E-3
4.70920193718724180E-3
4.72758914713162430E-3
4.74592915233441910E-3
4.76422152787834730E-3
freq
imag(S(1,2))
6.50000000000000000E8
6.54999999999999980E8
6.59999999999999960E8
6.65000000000000040E8
6.70000000000000020E8
6.75000000000000000E8
6.79999999999999980E8
6.84999999999999960E8
6.90000000000000040E8
6.95000000000000020E8
7.00000000000000000E8
-4.36894517786188350E-4
-4.51234242053132120E-4
-4.65678356909637080E-4
-4.80226727661889010E-4
-4.94879218065153560E-4
-5.09635690324991230E-4
-5.24496005098489350E-4
-5.39460021495511550E-4
-5.54527597079963110E-4
-5.69698587871075990E-4
-5.84972848344707950E-4
___
12/11/2016 11:44.
5.- FLL200IB2.mat in separate file

6.- cell_1.iff type and also in separate file
FRAMEWORK2
ICON/fileads_rflib/ads_rflib:file00
ICON/ads_rflib:filedesignsp_fuj_FLL200IB-2_19920501/ads_rflib:file/sp_fuj_FLL200IB-2_19920501:design00
SCIONPAGE/ads_rflib:file/sp_fuj_FLL200IB-2_19920501:designADS_ITEM_NAME=sp_fuj_FLL200IB2_19920501ADS_ITEM_LABEL=Fujitsu FLL200IB-2 Fet: Vds=10V
Ids=4800mAADS_ITEM_ATTR=0ADS_ITEM_ATTR_EX=32ADS_ITEM_DIALOG_NAME=Component
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%d:%t %# %44?0%:%31?%C%:_net%c%;%;%e %r%b%8?%29?%:%30?%p %:%k%?[%1i]%;=%p
_________________________________________________________________________________________________
28 / 35
___
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%;%;%;%e%eADS_ITEM_NET_DATA=S2PADS_ITEM_SCHEM_NAME=LIBSYM_NFET_SPADS_ITEM_ART_DATA=ADS_ITEM_ART_T
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SCIONOBJMsp_fuj_FLL200IB-2_19920501Lib=sp_fujLib_ADS_UNIT=-2Lib_ADS_LABEL=S-Parameter
LibraryLib_ADS_ATTR=513Lib_ADS_FORMSET=stringLib_ADS_INDEX=1Lib_ADS_FORM_NAME=stringFile=sp_fuj_FLL200IB2_19920501File_ADS_UNIT=-2File_ADS_LABEL=S-Parameter data
fileFile_ADS_ATTR=513File_ADS_FORMSET=stringFile_ADS_INDEX=2File_ADS_FORM_NAME=stringBias=Fet: Vds=10V
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ENDPAGE
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TEXT10120,5,IN/100NORMAL53.75-45S
TEXT10220,19.375,IN/100NORMAL300.625SP
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TEXT80140,12.5,IN/100NORMAL0-65.625@LABEL
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ICON/filesymbols/symbols:file00
ICON/symbols:filedesignwrkspc_Lab03_singleTRTamp_lib__cell_1/symbols:file/wrkspc_Lab03_singleTRTamp_lib__cell_1:design00
CIRCUITPAGE/symbols:file/wrkspc_Lab03_singleTRTamp_lib__cell_1:design1252512.5ONin/100HPEESOF_DESIGN_CODE=1
CON5201OTHER FONT250-87.5GROUND262.5-87.5250-87.5FTNCON_ID=G1
CONEND
CMP/S_Parameter:file/sp_fuj_FLL200IB-2_19920501:design002001000SNP1NNOFFLib=sp_fujFile=sp_fuj_FLL200IB2_19920501Bias=Fet: Vds=10V Ids=4800mAFrequency={0.50 - 4.00} GHzTemp=27
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LABELNum100,16.88,IN/10000leftNum64.37529.375DISPLAYUSERPATH1
CMP/ads_simulation:file/Term:design03612.51750Term2NNOFFNum=2 Z=50 ohNoise=YesVdc=Temp=
LABELlabel100,16.88,IN/10000leftlabel639.375158.125DISPLAYUSERPATHTerm
LABELname100,16.88,IN/10000leftname639.375137.5DISPLAYUSERPATHTerm2
LABELZ100,16.88,IN/10000leftZ639.37596.25DISPLAYUSERPATH50 Ohm
LABELNum100,16.88,IN/10000leftNum639.375116.875DISPLAYUSERPATH2
CMP/ads_simulation:file/S_Param:design005503500SP1NNOFFSweepVar="freq"UseSweepPlan=SweepPlan=Start=650
meghzStop=700 meghzStep=5 meghzCenter=Span=Lin=Dec=Log=Reverse=Pt=Sort=LINEAR START
STEPOutputPlan=list()UseEquationNestLevel=OutputPlan_BooleanYesEquationNestLevel=2
EquationName=list()CalcS=yesCalcY=noCalcZ=noCalcGroupDelay=GroupDelayAperture=0.0001
FreqConversion=NoFreqConversionPort=1 UseFiniteDiff=StatusLevel=2
CalcNoise=NoSortNoise=NoiseSortByNameNoiseThresh=100 BandwidthForNoise=1 hzFreq=
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Other=UseSavedEquationNestLevel=OutputPlan_BooleanYesSavedEquationNestLevel=2
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LABELlabel100,16.88,IN/10000leftlabel570.625278.125DISPLAYUSERPATHS_Param
LABELname100,16.88,IN/10000leftname570.625257.5DISPLAYUSERPATHSP1
LABELStep100,16.88,IN/10000leftStep570.625195.625DISPLAYUSERPATH5 MHz
LABELStop100,16.88,IN/10000leftStop570.625216.25DISPLAYUSERPATH700 MHz
LABELStart100,16.88,IN/10000leftStart570.625236.875DISPLAYUSERPATH650 MHz
CMP/ads_simulation:file/MatlabOutput:design00753500MatlabOutput1NNOFFFileName="FLL200IB_2.mat"Analysis=AllUseCustomControl=noFilterExpression=""
LABELlabel100,16.88,IN/10000leftlabel-54.375281.25DISPLAYUSERPATHMatlabOutput
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LABELFileName100,16.88,IN/10000leftFileName-54.375240DISPLAYUSERPATH"FLL200IB_2.mat"
WIRE0SQUARE,ON,BUSONgnd!
WIRESEGWIRES37.5-12.537.5-87.5
WIRESEGWIRES37.5-87.5250-87.5
WIRESEGWIRES250-87.525050
_________________________________________________________________________________________________
29 / 35
___
12/11/2016 11:44.
WIRE0SQUARE,ON,BUSONN__2
WIRESEGWIRES20010037.5100
WIRESEGWIRES37.510037.587.5
WIRE0SQUARE,ON,BUSONN__6
WIRESEGWIRES250150250175
WIRESEGWIRES250175612.5175
WIRESEGWIRES250-87.5612.5-87.5
WIRESEGWIRES612.5-87.5612.575
ENDPAGE
7.- GUIDE 02
For matching, the following routine needs to be applied whereby a new schematic file needs to be made within the same
project directory to create an optimised input matching network. Note why we must use only reactive components, i.e.
capacitors and inductors, in order to do this.
First of all, a black box representing the input impedance needs to be inserted. Go to the Eqn Based-Linear
component library and select the 1-port S-parameter component: . When you
have inserted this, complete the circuit like the diagram on the next page so that you can complete the circuit. Note that
you should enter C_opt pF for the value of the capacitor, this is important.
You can now insert the Zin component, using the
button in the Simulation-S_param library.
Here you should set the name to Zin1, while also defining it as zin(s11,PortZ1). Then you can enter the value for the
variables S-in and C_opt using the
button on the top menu bar.
Note S-parameter inputs have been blacked out in the image so you will work out the correct values for yourself! Note
also that your variables should be entered as type Name=Value in order to work.
Finally the S-parameters simulator should be entered this time as usual. However, this should not sweep across the
frequency range. Instead, just enter a fixed value of 680MHz as a single point frequency. Note that the start and stop
frequencies will then not appear in the design work as above.
Finally enter the Parameter Sweep by using the button from the Simulation-S_param library. In it you will need to enter
C_opt as the sweeping variable and SP1 as the simulation variable. You should enter start values of 1, stop value of 20 and
a step of 0.1.
You should end up with a schematic that looks something like this.
Finally you can run the simulation. You next want to plot the real value of input impedance versus C_opt. To do this in
the results window you need to:
1.
2.
3.
4.
5.
Click Rectangular Plot.

Select Zin, click >>Add Vs..>>
Select Real Part, click OK
Select C_opt as independent variable, click OK
Click OK to dismiss the dialogue box.
When you have found the value of C_opt to give you a real input impedance of 50, you now need to apply a capacitor to
_________________________________________________________________________________________________
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___
12/11/2016 11:44.
cancel out the reactive component. You should modify your test port by inserting a series capacitor as follows. You should
also enter the chosen value for C_opt as you no longer need to simulate this. It has been blanked out so that you cannot shortcut the previous task.
Now you need to enter the chosen parallel capacitor value and move C_opt pF as the variable capacitor value, to the new
location in a new design file shown below. You can now run the simulation again. Again the parallel capacitor value has
been blanked out to make you find it.
To determine the most suitable capacitor value, the most appropriate means to do this using a similar procedure as for the
previous capacitance value, is to plot s11 in dB versus C_opt. Then you can find the optimum capacitance for where s11 falls
to a suitably low value to be matched. Ask a demonstrator if you are unsure about whether you have selected a suitable value.
You have now got a suitable matching network to apply to your amplifier.
Now that appropriate values for the L-section matching network have been found, you can apply them to a modified version
of your original amplifier circuit to form one like that on the next page. As before, the final values of the input and output
capacitors are covered up on purpose.
8.- What happens when looking the wrong direction
_________________________________________________________________________________________________
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starting reducing C1 doesnt improve anything, but starting C3 10pF 6pF already shifts slightly down s11 notch while not
losing
gain
RESULT: C1=3.5 pF C2= 13.2 pF L1= 1 nH C3= 6 pF achieving s11 below -20dB gain above 10dB but s22-load mismatch
9.- Literature references
(next attachment is number 15)
From [POZAR]
On the right hand side [MEDLEY] table covering all cases:

Attachment 8 contains another attempt with topology
The Laboratory text suggests topology (4) that cannot match
s22 at 680MHz therefore I am bringing the series inductance
next to the port and instead lets start with topology (1).
_________________________________________________________________________________________________
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15.- Fujitsu Semiconductors contact details
(next attachment is number 20)
Fujitsu contact details Headquarters Fujitsu Electronics Europe GmbH

European Headquarters
Tel: +49 (0) 61 03 69 00
Fax: +49 (0) 61 03 69 01 22
info.feeu@de.fujitsu.com by 16:00 EU time all gone home
Address:
Pittlerstrasse 47
63225 Langen
Germany
Germany
Fujitsu Electronics Europe GmbH
Local Sales Office
Tel: +49 (0) 61 03 69 00
Fax: +49 (0) 61 03 69 01 22
Address:
Carl-Zeiss-Ring 11
85737 Ismaning
Germany
The online result of local Fujitsu office in Berkshire is no longer correct:
Address: Building 3, Concorde Park, Concorde Rd, Maidenhead SL6 4FJ

Phone: 01628 504600
no Fujitsu office based in UK
query submitted on November 10th 2016 at https://www.fujitsu.com/jp/group/fsl/en/contact/inquiry-e.html

Hi my name is John Bofarull Guix, RF Engineering student at the University of Surrey. Currently attempting to simulate amplifier with your RF
transistor FL200IB-2 but I have found the following problems:
1.- the ADS model is quite limited.
Could you please make available the complete Spice model of this FET transistor that includes your measurements on the following SPICE
parameters:Idsmod Tau Alpha Cgs Cgd Rgd Rd Rg Rs Cds Crf Rc Is
I am asking because when searching for FL200IB in your Semiconductors website it seems to be the case that you do not keep online any reference
or datasheet.
The FL200IB-2 datasheets I have found online come from vendors and internet archive sites which leaves room to think that you have discontinued
this product.
If such is the case, would you please be so kind to confirm that Fujitsu no longer manufacturers such transistor, and if you have any equivalent
replacement.
Thanks in advance awaiting answer
10. packed workspace wrkspc_Lab03_singleTRTamp in separate .zip file and without compression
available from DROPBOX
Attachment 20.- checking_stability.m
Z0=50;f=[6.5e8:5e8:7e8];
s11_real=[-8.01638024996697140E-1
-7.98987057248149310E-1
-7.96314717472233720E-1
-7.93621081673978510E-1
-7.90906226427747420E-1
-7.88170228875063120E-1
-7.85413166722421780E-1
-7.82635118239087380E-1
-7.79836162254874310E-1
-7.77016378157914290E-1
-7.74175845892409060E-1]
s11_imag=[4.94522079263802810E-1
4.98661640042566570E-1
5.02787000962750060E-1
5.06898051705295580E-1
5.10994682357674710E-1
5.15076783416832470E-1
5.19144245792108630E-1
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5.23196960808154450E-1
5.27234820207836210E-1
5.31257716155122670E-1
5.35265541237966240E-1]
s22_real=[-8.49053920229632730E-1
-8.47988294269098470E-1
-8.46919426518678260E-1
-8.45847326380643060E-1
-8.44772003269071630E-1
-8.43693466609783020E-1
-8.42611725840274950E-1
-8.41526790409658610E-1
-8.40438669778594160E-1
-8.39347373419227340E-1
-8.38252910815125500E-1]
s22_imag=[2.69172677927557610E-1
2.70839599915863040E-1
2.72503187844240640E-1
2.74163435480952080E-1
2.75820336619256690E-1
2.77473885077437600E-1
2.79124074698821630E-1
2.80770899351799840E-1
2.82414352929852530E-1
2.84054429351567080E-1
2.85691122560659540E-1]
s21_real=[6.66506226572780310E-1
6.69078930692778510E-1
6.71602005480083970E-1
6.74075502306971150E-1
6.76499474996352570E-1
6.78873979815965180E-1
6.81199075472449600E-1
6.83474823105324610E-1
6.85701286280858560E-1
6.87878530985837600E-1
6.90006625621229740E-1]
s21_imag=[8.31043645026970520E-1
8.24741550185879650E-1
8.18436793304852020E-1
8.12129732302422270E-1
8.05820724435441350E-1
7.99510126282858380E-1
7.93198293729556700E-1
7.86885581950225800E-1
7.80572345393286500E-1
7.74258937764857790E-1
7.67945712012772490E-1]
s12_real=[4.57920551846369680E-3
4.59791122780755050E-3
4.61657271879323260E-3
4.63518956354960210E-3
4.65376133461173770E-3
4.67228760492619610E-3
4.69076794785627000E-3
4.70920193718724180E-3
4.72758914713162430E-3
4.74592915233441910E-3
4.76422152787834730E-3]
s12_imag=[-4.36894517786188350E-4
-4.51234242053132120E-4
-4.65678356909637080E-4
-4.80226727661889010E-4
-4.94879218065153560E-4
-5.09635690324991230E-4
-5.24496005098489350E-4
-5.39460021495511550E-4
-5.54527597079963110E-4
-5.69698587871075990E-4
-5.84972848344707950E-4]
s11=complex(s11_real,s11_imag);
det=s11.*s22-s12.*s21;
K=(1-s11.*conj(s11)-s22.*conj(s22)+(abs(det)).^2)./(2*abs(s12.*s21))
abs(det)
% transducer gain
GTmax_dB_680M=10*log10(s21_680M*conj(s21_680M))
s11_imag_680M = 0.519144450000000;
s11_imag_680M = 0.519144245000000;
Zin_port1_680=Z0*(1+s11_680)./(1-s11_680)
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s11_real_680M = -0.785431660000000;
s11_imag_680M = 0.519144245000000;
Zin_port2_680=Z0*(1+s22_680)./(1-s22_680) % 1.642714218137484 +15.015986600420064i
s22_real_680M = -0.84261172 ;
s22_imag_680M = 0.27912407 ;
Zin2_680=Z0*(1+s22_680)./(1-s22_680) % 3.053374808339239 + 8.036676280198153i
VOID TEMPLATE
_________________________________________________________________________________________________
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044 LAB03 Single Transistor Amplifier

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M044 Laboratory 03 Intro to Power Amplifiers

M044 Laboratory 3 Single Transistor Amplifier

ADS Workspace contents table

1. FLL200IB-2 transistor datasheet

ADS and this text AVAILABLE FROM

Please only consider cells

ADS WORKSPACES CONTENT TABLE

attached: 12 documents as detailed in header

M044 Laboratory 03 Intro to Power Amplifiers

EXTRACTION OF S PARAMETERS FROM COMPONENT MODEL

Attachment 01 FLL200IB-2 transistor datasheet from manufacturer link1

attached: 12 documents as detailed in header

M044 Laboratory 03 Intro to Power Amplifiers

|s21| dB, |s21| linear, (s21)

|s12| dB, |s12| linear, (s12)

which seems understandable when wanting

attached: 12 documents as detailed in header

M044 Laboratory 03 Intro to Power Amplifiers

Observation: The above inspection of the FLL200IB-2 transistor ADS model

attached: 12 documents as detailed in header

M044 Laboratory 03 Intro to Power Amplifiers

ANNOTATING S PARAMETERS OUT OF SIMULATION

attached: 12 documents as detailed in header

M044 Laboratory 03 Intro to Power Amplifiers

Exploration: Attempt to export to MATLAB variables file format

Pending: this may be a student version limitation, pending to ask

Pending: this may be a student version limitation, pending to ask KEYSIGHT

the S parameters seem to be included in the cell_1.iff

attached: 12 documents as detailed in header

M044 Laboratory 03 Intro to Power Amplifiers

attached: 12 documents as detailed in header

M044 Laboratory 03 Intro to Power Amplifiers

MATCHING INPUT PORT ON SINGLE FREQUENCY WITH L NETWORK

Laboratory guide text for this section moved to

RESULT: C1=13.15pF C2=3.55pF

attached: 12 documents as detailed in header

M044 Laboratory 03 Intro to Power Amplifiers

RESULT: C3=17.6pF L1=15.6nH

attached: 12 documents as detailed in header

M044 Laboratory 03 Intro to Power Amplifiers

MATCHING OUTPUT PORT ON SINGLE FREQUENCY WITH L NETWORK

attached: 12 documents as detailed in header

M044 Laboratory 03 Intro to Power Amplifiers

refining the step from 0.05 to 0.005

RESULT: L=0.895 nH C = 18.5 pF

attached: 12 documents as detailed in header

M044 Laboratory 03 Intro to Power Amplifiers

MATCHING OUTPUT PORT WITH PI NETWORK

L30[nH] on Smith Chart

L30[nH] on Smith Chart

L30[nH] on Smith Chart

attached: 12 documents as detailed in header

M044 Laboratory 03 Intro to Power Amplifiers

tuned values stored from Tune window

fine tuning with ADS function Tune has as RESULT:

C31=11.2pF C30=11pF L30=1.6nH

attached: 12 documents as detailed in header

M044 Laboratory 03 Intro to Power Amplifiers

SINGLE TRANSISTOR AMPLIFIER

attached: 12 documents as detailed in header

M044 Laboratory 03 Intro to Power Amplifiers

attached: 12 documents as detailed in header

M044 Laboratory 03 Intro to Power Amplifiers

Since Load and Source are fairly matched, the expression

is reduced to s21conj(s21) that at 680MHz is a modest GTmax_dB_680M=10log10(s21_680M*conj(s21_680M))