A Hardware-effective Digital Decimation Filter

Implementation for 24-bit ~L ADC

Yafei Ye,Ting Li, Zhihua Wang

Liyuan Liu, Dongmei Li

Institution of Microelectronics
Tsinghua University
Beijing, China
ye-yafei@163.com

Department of Electronic Engineering

Tsinghua University
Beijing, China
lidmei@tsinghua.edu.cn
The system block diagram of this digital decimation filter
is illustrated in Figure 1. The decimation filter uses multistage structure to relax the filter design. The front of the
decimation filter is the comb ones including four cascade
comb sub-filters. The following FIR filters consist of two halfband FIR sub-filters. Each of the sub-filters decimates the
signal by a factor of 2. Thus the decimation filter realizes a
down-sampling of 64.

Abstract-A hardware-effective digital decimation filter

implementation used in the 24-bit LU: ADC for audio application
is described in this paper. Composing of four comb filters and
two half-band Finite Impulse Response (FIR) filters, the digital
decimation filter uses multistage structure to relax the filter
design. Since the multipliers are the most hardware consuming
components in the digital filters, the coefficients of the FIR
filters are coded by Canonical Signed Digit (CSD) which can
make the filter multiplier-free. Meanwhile, time-multiplexing
method is adopted in the filter to further reduce the hardware
consumption. The proposed design is synthesized in 180nm
CMOS process and occupies a die area of 1.44 mnr', This
implementation is well suited for VLSI and can be applied to
many other high resolution LU: ADC.
I.

The two half-band FIR filters determine the overall

performance of the decimation filter, thus they should be
carefully designed. In order to achieve the requirement of 24bit ~L ADC, the noise should be attenuated under -140 dB
level. Hence two half-band filters need a cut-off frequency of
0.2fs, a stopband rejection of at least -100 dB and a narrow
transition bandwidth. Those requirements will make the order
of the filter especially high. In the traditional ways, the high
order half-band filter will take up a large area. In this design
both half-band filters employ the multiplier-free structure. The
function of the half-band FIR filter is based on the procedure
described by Saramaki[1].

INTRODUCTION

With the increasing demand for high precision audio AID

and DIA in consumer electronics, the ~L ADC which can be
easily integrated within the digital system is becoming
increasingly popular. The digital decimation filter is an
important part of the ~L ADC, which can effectively filter the
high-frequency quantization noise and does not cause signal
distortion. Because the decimation filter usually occupies
more than half the chip area, improving and optimizing the
design of decimation filter becomes a key factor in reducing
area consumption. A high hardware-efficiency implementation
of a digital decimation filter for 24-bit ~L ADC is described in
this paper.

In session II, the design of the decimation filter will be

described. Session III presents the simulation results while the
IV shows the layout of the decimation filter. The conclusion
will be drawn in session V.
II.

A. Architecture
Figure 1. shows the detail diagram of the decimation filter.
The comb filters use the traditional structure to simplify the
filter design. The half-band structure is chosen because about
half of the total coefficients are zeros. The two half-band
filters and the back stages of the comb filters work at low
frequency compared to the master clock, thus it allows the
operation units to be multiplexed.
B.

Comb Filters
The structure of Cascaded Integrator Comb (CIC) is
adopted in the design of comb filters [2]. The first two stages
are 4th-order comb filters, and the rest two stages are 5th-order
comb filters. The 4th-order and 5th-order comb filters'

Figure 1. Block diagram of the multi-stage decimation filter

978-1-4577-1610-2/11/$26.00 2011 IEEE

DIGITAL DECIMATION FILTER

13

TABLE!.

frequency response are shown in the Figure 2. (a) and Figure

2. (b) respectively.

THE INS (4:0) CHANGES AS THE ST(3:0) SIGNAL

St(3:0)

In5(4:0)

0000
0001
0010

00000
00011
00101
00111
01001
01011
10000

0011
0100
0101
Others

c.

The FIR filters perform the final decimation by 4 and

determine the overall performance of the decimation filter.
Because the high order FIR filter is difficult to design by
traditional methods, this work is based on the cascading the
identical sub-filters. The two half-band filters use the same
structure which is shown in Figure 4. (a). The F2 is the subfilter of the half-band filter, which is shown in Figure 4. (b)[5].

Figure 2. Frequency response of the comb filters

The transfer function of the 4th-order comb filter is:

H4

(1+ Z-1)4

== (1

+ Z-4) + 4(Z-1 + Z-3) + 6z-

Half-band Filters

(1)

The transfer function of the 5th-order comb filter is:

(2)

IN
@fs

Because all the coefficients of comb filters are integers,

it's easy to realize the filter by simple shifters and adders. The
implementation of these stages are similar, thus the fourth
stage comb filter is chosen to illustrate the scheduling of the
comb filters[3][4].

Decimation structure.

(a)

IN

OUT

F2 filter.

(b)
Figure 4. Block diagram of the half-band filter

The half-band filter's frequency response is shown in the

Figure 5. The filter achieves 110dB of attenuation in the stopband which satisfies the requirement of the decimation filter.
Figure 3. Proposed structure of the fourth stage comb filter

Figure 3. shows the structure of the fourth stage comb

filter. This stage filter works under 1/16 of the master clock,
so only one adder is needed by using time-multiplexing
method. In this stage all the actions of the shift are toward the
left. St is a counter signal. When the rising edge of the clock
occurs, St is updated by 8t+ 1. Ins (4:0) is the global control
signal, which is generated by the module of InsGen. TABLE I.
shows the Ins (4:0) changes as the 8t(3:0) signal.

Figure 5. Frequency response of the half-band filters

14

TABLE III.

Since multipliers are the most power consuming

components in the digital filters, the coefficients of this filter
are coded by CSD which can make the filter multiplier-free,
so the hardware consumption is significantly reduced [6]. The
coefficients and their signed-digit decompositions are
summarized in the TABLE II. All the coefficients of the filter
use only 3 signed digits, so any of the multiplication can be
replaced by 2 binary additions. Thus, the proposed half-band
filter only needs 3 X 3 + 5(3 X 6+6-1)=124 additions.
TABLE II.

COEFFICIENTS AND THEIR SIGNED-DIGIT DECOMPOSITIONS

Value

Decomposition

f11

0.9453

2_2-4+2-7

f12

-0.6406

_2- 1_2-3 _2-6

f13

0.1953

f21

0.6211

2-1+2-3_2-8

f22

-0.1895

_2-2+2-4_2-9

f23

0.0957

2-3 _2-5+2-9

f24

-0.0508

_2-4+2-7 +2-8

f25

0.0269

2-5 _2-8 _2- 11

f26

-0.0142

_2-6+2-9 _2- 11

Coefficients

THE INS (11 :0) CHANGES AS THE ST(4:0) SIGNAL

5t(4:0)

In5(11 :0)

00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011

000000000011
000100011101
001000101110
001100110011
010001001101
001000101101
001001010110
010101100011
011001111101
001010000101
001001010110
011110010011

5t(4:0)
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
Others

In5(11 :0)
100010101101
000100011101
001001010110
100110110011
101011001101
001011011101
001001010110
101111100011
100011110101
001001001101
001001010110
000000000111

The proposed structure of the half-band filter is shown in

Figure 7. In this stage, all the actions of the shift are also
toward the right. There are only 2 adders to complete all the
operations. TABLE IV. summarizes the Ins (11:0) changes as
the St (5:0) signal.

2-2 _2- 4+2-7

The first stage half-band filter and the second stage halfband filter works at 1/32 and 1/64 of the master clock
frequency respectively. Take the second stage as an example,
there are 64 clock cycles to complete the operation. By the
operation units multiplexing, each sub-filter needs 1 adder and
the half-band filter only needs 5 X 1+2=7 adders. Through the
use of this structure and the hardware multiplexing method,
the hardware consumption is greatly reduced.

Figure 7. Proposed structure of the half-band filter

TABLE IV.

THE INS (11:0) CHANGES AS THE ST(5:0) SIGNAL

5t(5:0)

In5(11 :0)

100001
100010
100011
100100
100101
100110

000000000100
000001001100
010100010110
101001011110
101010100000
101001101000
000000000001

Others

D. Parallel-fa-Serial Conversion

Because 24-bit parallel output needs to occupy 24 PADs,

the decimation filter introduces a module which converts the
24-bit parallel data into serial data to reduce the hardware
consumption. The working principle of this module of
parallel-to-serial conversion is described in Figure 8. The port
of serial output is connected with the least significant bit of the
24-bit parallel data. When the rising edge of the clock occurs,
24-bit parallel data are shifted to the right one bit and the most

Figure 6. Proposed structure of the sub-filter F2

Figure 6. shows the proposed structure of the sub-filter F2.

In this sub-filter, all the actions of the shift are toward the right.
Ins (11:0) also is the global control signal. TABLE III.
summarizes the Ins (11:0) changes as the St (4:0) signal.

15

significant bit is padded with zero. After repeating this process

24 times, the procedure of converting 24-bit parallel data into
serial data is completed.

IV.

LAYOUT

Figure 8. Working principle of the parallel to serial

III.

SIMULATION

The decimation filter is simulated in the ModelSim SE

6.2e. The input data is generated from a 3rd-order single loop
~L modulator.
Figure 10. Layout of the digital decimation filter

Figure 10. shows the layout of the digital decimation filter.

This design is implemented in 180nm CMOS process. The
digital decimation filter is described by VHDL, which is
synthesized by using Synopsys Design Complier. The layout
of the filter is obtained through using Cadence SOC Encounter.
The total filter area is 1.44 mm",
V.

CONCLUSION

Low hardware consumption has been achieved in design

and implementation of a digital decimation filter for a 24-bit
~L ADC. The proposed architecture of the digital decimation
filter reduces the chip area significantly. The CSD multiplier
eliminates the use of high hardware consuming multiplies.
The time-multiplexing method is used to distribute the
computations in time and hence greatly reduce the number of
operation units.
[1]

[2]

[3]
Figure 9. Power spectral density
[4]

The power spectral density of the input and output are

shown in the Figure 9. (a) and Figure 9. (b) respectively. The
comparison of spectrum indicates the noise beyond signal
bandwidth is filtered and the SNDR in the signal band has no
attenuation. Thus, the proposed decimation filter can be well
qualified for a 24-bit ~L ADC.

[5]

T. Saramaki, "Design of FIR filters as a tapped cascaded

interconnection of indentical subfilters," IEEE Transactions on Circuits
and Systems, vol. 34, pp. 1011-1029,1987.
Hogenauer E "An Economical Class of Digital Filters for Decimation
and Interpolation," Acoustics, Speech and Signal Processing, IEEE
Transactions on, 1981.
Liyuan Liu, Run Chen, Dongmei Li, "A 20-Bit Sigma-Delta D/A for
Audio Applications in 0.13um CMOS," IEEE International Symposium
on Circuits and Systems, ISCAS 2007.
Liyuan Liu, Run Chen, Dongmei Li, "A cost-effective digital front-end
realization for 20-bit L~ DAC in 0.13 J.1m CMOS," IEEE Custom
Integrated Circuits Conference,CICC 2007 .
R.Schreier and G. C. Ternes, "Understanding Delta-Sigma Data
Converters," John Wiley & Sons, New York, 2004 .

[6] Henry Samueli, "An Improved Search Algorithm for the Design of
Multiplierless FIR Filters with Powers-of-Two Coefficients," in
IEEE Trans.on Circuits and Systems, vol.36, no.", Jul, 1989.

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