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TPS62135, TPS621351
SLVSBH3A JUNE 2016 REVISED SEPTEMBER 2016
3 Description
2 Applications
PACKAGE
TPS62135
VQFN
3.00 mm x 2.00 mm
TPS621351
VQFN
3.00 mm x 2.00 mm
space
Efficiency vs Output Current for Vo = 3.3 V
Simplified Schematic
TPS62135
VIN
10uF
EN
1 uH
100
90
SW
80
VOS
R1
FB
R2
70
22uF
Efficiency (%)
60
50
VSEL
PG
MODE
FB2
30
SS/TR
GND
20
VIN = 4 V
VIN = 5 V
VIN = 6 V
VIN = 8 V
VIN = 10 V
VIN = 12 V
VIN = 15 V
40
10
0
1E-5
0.0001
0.001
0.01
IOUT (A)
0.1
4
D001
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS62135, TPS621351
SLVSBH3A JUNE 2016 REVISED SEPTEMBER 2016
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Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Device Comparison Table.....................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
3
4
7.1
7.2
7.3
7.4
7.5
7.6
4
4
4
5
5
7
36
36
36
36
36
36
36
4 Revision History
Changes from Original (June 2016) to Revision A
Page
TPS62135, TPS621351
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FEATURES
OUTPUT VOLTAGE
MARKING
TPS62135RGX
adjustable
62135
TPS621351RGX
adjustable
621351
bottom view
top view
8
7
EN
PG
SS/TR
VOS
10
VIN
SW
GND
MODE
VSEL
FB 2
EN
VOS
SS/TR
FB
11
8
PG
GND
SW
VIN
10
FB
MODE
FB 2
VSEL
11
Pin Functions
PIN
NAME
NUMBER
I/O
DESCRIPTION
EN
This is the enable pin of the device. Connect to logic low to disable the device. Pull high to
enable the device. Do not leave this pin unconnected.
FB
Voltage feedback input, connect resistive output voltage divider to this pin.
FB2
Open drain of an internal switch to GND. Allows to turn on a resistor in parallel to the
feedback resistor R2 and increase the output voltage with VSEL = high.
GND
MODE
10
The device runs in PFM/PWM mode when this pin is pulled low. When the pin is pulled high,
the device runs in forced PWM mode. Do not leave this pin unconnected.
PG
SS/TR
Soft-Start / Tracking pin. An external capacitor connected from this pin to GND defines the
rise time for the internal reference voltage. The pin can also be used as an input for tracking
and sequencing - see Detailed Description section in this document.
SW
This is the switch pin of the converter and is connected to the internal Power MOSFETs.
VIN
Power supply input. Make sure the input capacitor is connected as close as possible
between pin VIN and GND.
VOS
Output voltage sense pin. Connect directly to the positive pin of the output capacitor.
VSEL
11
Voltage scaling control input. Turns on an internal switch from FB2 to GND when this pin is
set high.
Ground pin.
TPS62135, TPS621351
SLVSBH3A JUNE 2016 REVISED SEPTEMBER 2016
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7 Specifications
7.1 Absolute Maximum Ratings
over operating junction temperature range (unless otherwise noted)
(1)
MIN
MAX
UNIT
VIN
-0.3
20
SW, VOS
-0.3
VIN+0.3
23
-0.3
VIN+0.3
-40
150
-65
150
SW (transient)
EN, MODE, VSEL, PG, FB, FB2, SS/TR
(1)
(2)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltages are with respect to network ground pin.
Electrostatic discharge
VALUE
UNIT
2000
500
(2)
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
NOM
MAX
UNIT
VIN
17
VOUT
0.8
12
Effective inductance
0.6
2.9
CO
200 (2)
22
CI
(1) (3)
10
TJ
-40
(1)
(2)
(3)
F
+125
Due to the dc bias effect of ceramic capacitors, the effective capacitance is lower then the nominal value when a voltage is applied. This
is why the capacitance is specified to allow the selection of the smallest capacitor required with the dc bias effect for this type of
capacitor in mind. The nominal value given matches a typical capacitor to be chosen to meet the minimum capacitance required.
This is for capacitors directly at the output of the TPS62135x. More capacitance is allowed if there is a series resistance associated to
the capacitors. See also the systems examples Powering Multiple Loads for applications where many distributed capacitors are
connected to the output.
Larger values may be required if the source impedance can not support the transient requirements of the load.
TPS62135, TPS621351
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TPS62135,
TPS621351
(1)
UNIT
RGX (VQFN)
11 PIN
RJA
38.4
C/W
RJC(top)
2.0
C/W
RJB
7.6
C/W
JT
0.1
C/W
JB
7.6
C/W
RJC(bot)
3.2
C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report. Thermal data is taken according JEDEC 51-5 on a 4-layer pcb with 6 thermal vias.
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY
IQ
Operating Quiescent
Current
IQ
Operating Quiescent
Current
ISD
Shutdown Current
35
18
46
VUVLO
Undervoltage Lockout
Threshold
2.8
2.9
3.0
2.5
2.6
2.7
TSD
Thermal Shutdown
Temperature
160
C
Thermal Shutdown
Hysteresis
20
VIL
VIH
0.77
VIL
0.67
ILKG_EN
VTH_PG
Rising (%VOUT)
93%
Hysteresis
Falling (%VOUT)
3%
VOL_PG
IPG = -2 mA
ILKG_PG
VPG = 5 V
ISS/TR
0.9
ISS/TR tolerance
Tracking gain
VFB / VSS/TR
Tracking offset
V
0.3
0.8
0.83
0.7
0.73
100
nA
96%
98%
4.5%
0.07
0.3
100
nA
2.5
0.2
1
11
mV
TPS62135, TPS621351
SLVSBH3A JUNE 2016 REVISED SEPTEMBER 2016
www.ti.com
TEST CONDITIONS
MIN
TYP
MAX
UNIT
POWER SWITCH
RDS(ON)
VIN 4 V
100
180
VIN 4 V
39
67
4.4
5.2
6.5
4.4
5.2
6.5
ILIMH
High-Side MOSFET
Current Limit
dc value (1)
ILIML
Low-Side MOSFET
Current Limit
dc value (1)
ILIMNEG
dc value
1.5
0.7
OUTPUT
VFB
Feedback Voltage
ILKG_FB
VFB= 0.7 V
VFB
Feedback Voltage
Accuracy (2)
VIN VOUT +1 V
PWM mode
-1%
1%
-1%
2%
-1%
2.5%
VOUT < 1 V
-1%
2.5%
-2%
7.5%
VFB
Feedback Voltage
Accuracy with Voltage
Tracking
RDS(ON)
ILKG_FB2
70
nA
10
30
70
nA
Load Regulation
0.05
%/A
Line Regulation
0.02
%/V
Output Discharge
Resistance
TPS62135 only
100
tdelay
200
tramp
150
(1)
(2)
300
s
s
See also HICCUP Current Limit And Short Circuit Protection (TPS62135 only) and Current Limit And Short Circuit Protection
(TPS621351 only).
The output voltage accuracy in Power Save Mode can be improved by increasing the output capacitor value, reducing the output voltage
ripple (see Pulse Width Modulation (PWM) Operation).
TPS62135, TPS621351
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35
30
TA = 125oC
TA = 85oC
TA = 25oC
TA = -40oC
1.5
25
20
15
10
TA = 125oC
TA = 85oC
TA = 25oC
TA = -40oC
0.5
5
8
10
VIN (V)
12
14
16
18
D001
EN = low
EN = high
8
10
VIN (V)
12
14
16
18
D001
SW
CIN
VOS
EN
R3
R1
COUT
FB
R2
VSEL
PG
MODE
FB2
SS/TR
GND
CSS
Copyright 2016, Texas Instruments Incorporated
DESCRIPTION
MANUFACTURER
IC
1 H inductor
CIN
10 F, 25 V, Ceramic, 0805
COUT
COUT
COUT
CSS
R1
R2
R3
XFL4020-102; Coilcraft
TPS62135, TPS621351
SLVSBH3A JUNE 2016 REVISED SEPTEMBER 2016
www.ti.com
9 Detailed Description
9.1 Overview
The TPS62135 synchronous switched mode power converters are based on DCS-Control (Direct Control with
Seamless Transition into Power Save Mode), an advanced regulation topology, that combines the advantages of
hysteretic, voltage mode and current mode control. This control loop takes information about output voltage
changes and feeds it directly to a fast comparator stage. It sets the switching frequency, which is constant for
steady state operating conditions, and provides immediate response to dynamic load changes. To get accurate
DC load regulation, a voltage feedback loop is used. The internally compensated regulation network achieves
fast and stable operation with small external components and low ESR capacitors.
The DCS-Control topology supports PWM (Pulse Width Modulation) mode for medium and heavy load
conditions and a Power Save Mode at light loads. During PWM, it operates at its nominal switching frequency in
continuous conduction mode. This frequency is typically about 2.5 MHz with a controlled frequency variation
depending on the input voltage. If the load current decreases, the converter enters Power Save Mode to sustain
high efficiency down to very light loads. In Power Save Mode the switching frequency decreases linearly with the
load current. Since DCS-Control supports both operation modes within one single building block, the transition
from PWM to Power Save Mode is seamless without effects on the output voltage. An internal current limit
supports nominal output currents of up to 3.5 A. The TPS62135x family offers both excellent DC voltage and
superior load transient regulation, combined with very low output voltage ripple, minimizing interference with RF
circuits.
Soft
start
Thermal
Shutdown
UVLO
VIN
PG control
HS lim
comp
EN
SS/TR
gate
drive
power
control
control logic
SW
VSEL
FB2
comp
LS lim
VOS
ramp
FB
comparator
error
amplifier
DCS - Control
TM
EN
GND
Copyright 2016, Texas Instruments Incorporated
The discharge switch on the VOS pin is only available in the TPS62135.
TPS62135, TPS621351
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TPS62135, TPS621351
SLVSBH3A JUNE 2016 REVISED SEPTEMBER 2016
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TON =
VOUT
400[ns ]
VIN
(1)
TON = 100
VIN
[ns ]
VIN - VOUT
(2)
For very small output voltages, an absolute minimum on-time of about 50 ns is kept to limit switching losses. The
operating frequency is thereby reduced from its nominal value, which keeps efficiency high. Using TON, the
typical peak inductor current in Power Save Mode is approximated by:
IL P S M
( peak )
(V IN
- VO U T )
TO N
L
(3)
There is a minimum off-time which limits the duty cycle of the TPS62135x. When VIN decreases to typically 15%
above VOUT, the TPS62135x does not enter Power Save Mode, regardless of the load current. The device
maintains output regulation in PWM mode.
The output voltage ripple in power save mode is given by Equation 4:
DV =
L VIN 2
1
1
+
(4)
(5)
Copyright 2016, Texas Instruments Incorporated
TPS62135, TPS621351
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VL
t PD
L
(6)
where:
ILIMF is the static current limit as specified in the electrical characteristics
L is the effective inductance at the peak current
VL is the voltage across the inductor (VIN - VOUT) and
tPD is the internal propagation delay of typically 50 ns.
The current limit can exceed static values, especially if the input voltage is high and very small inductances are
used. The dynamic high side switch peak current can be calculated as follows:
VIN - VOUT
50ns
L
(7)
11
TPS62135, TPS621351
SLVSBH3A JUNE 2016 REVISED SEPTEMBER 2016
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12
TPS62135, TPS621351
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VOUT
- 1
R1 = R 2
VFB
(8)
100 F
200 F
400 F
(3)
(3)
(3)
10 F
22 F
47 F
0.68 H
1 H
(2)
1.5 H
2.2 H
3.3 H
(1)
(2)
(3)
DI L(max)
2
(9)
13
TPS62135, TPS621351
SLVSBH3A JUNE 2016 REVISED SEPTEMBER 2016
DIL (max) =
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VIN (max)
100ns
L (min)
(10)
where:
IL(max) is the maximum inductor current
IL is the Peak to Peak Inductor Ripple Current
L(min) is the minimum effective inductor value.
Calculating the maximum inductor current using the actual operating conditions gives the minimum saturation
current of the inductor needed. A margin of about 20% is recommended to add. A larger inductor value is also
useful to get lower ripple current, but increases the transient response time and size as well. The following
inductors have been used with the TPS62135x and are recommended for use:
Table 3. List of Inductors
TYPE
INDUCTANCE [H]
DIMENSIONS [LxBxH] mm
MANUFACTURER
XFL4020-102ME
1.0 H, 20%
5.4
4 x 4 x 2.1
Coilcraft
XAL4020-102ME
1.0 H, 20%
8.7
4 x 4 x 2.1
Coilcraft
XAL4020-152ME
1.5 H, 20%
7.1
4 x 4 x 2.1
Coilcraft
XFL4030-102ME
1.0 H, 20%
4.1
4 x 4 x 3.1
Coilcraft
1277AS-H-1R0M (DFE322512C)
1.0 H, 20%
3.1 (2)
Murata
(1)
(2)
The inductor value also determines the load current at which Power Save Mode is entered:
I load ( PSM ) =
1
DI L
2
(11)
(1)
14
TYPE
SIZE
MANUFACTURER
TMK212BBJ106MG-T
10
25
0805
Taiyo Yuden
EMK212BBJ226MG-T
22
16
0805
Taiyo Yuden
TPS62135, TPS621351
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(12)
where:
CSS is the capacitance required at the SS/TR pin and
tSS is the desired Soft-Start ramp time
The fastest achievable typical ramp time is 150 s even if the external Css capacitance is lower than 680 pF or
the pin is open.
10.1.5 Tracking Function
If a tracking function is desired, the SS/TR pin can be used for this purpose by connecting it to an external
tracking voltage. The output voltage tracks that voltage with the typical gain and offset as specified in the
electrical characteristics.
When the SS/TR pin voltage is above 0.7 V, the internal voltage is clamped and the device goes to normal
regulation. This works for rising and falling tracking voltages with the same behavior, as long as the input voltage
is inside the recommended operating conditions. For decreasing SS/TR pin voltage in PFM mode, the device
does not sink current from the output. The resulting decrease of the output voltage may therefore be slower than
the SS/TR pin voltage if the load is light. When driving the SS/TR pin with an external voltage, do not exceed the
voltage rating of the SS/TR pin which is VIN + 0.3 V. The SS/TR pin is internally connected with a resistor to GND
when EN = 0.
If the input voltage drops below undervoltage lockout, the output voltage will go to zero, independent of the
tracking voltage. Figure 4 shows how to connect devices to get ratiometric and simultaneous sequencing by
using the tracking function. See also Voltage Tracking in the systems examples. SS/TR is internally clamped to
approximately 3 V.
DEVICE 1
TPS62135
VIN = 12V
VIN
10uF
1 uH
VOUT = 3.3V
SW
VOS
EN
560k
22uF
FB
150k
VSEL
PG
MODE
FB2
SS/TR
GND
3.3nF
DEVICE 2
TPS62135
VIN = 12V
VIN
10uF
EN
1 uH
VOUT = 1.8V
SW
VOS
470k
22uF
FB
300k
VSEL
R5 = 56k
PG
MODE
FB2
SS/TR
GND
R6 = 15k
15
TPS62135, TPS621351
SLVSBH3A JUNE 2016 REVISED SEPTEMBER 2016
www.ti.com
The resistive divider of R5 and R6 can be used to change the ramp rate of VOUT2 to be faster, slower or the
same as VOUT1.
A sequential startup is achieved by connecting the PG pin of VOUT of DEVICE 1 to the EN pin of DEVICE2. PG
requires a pull-up resistor. Ratiometric start up sequence happens if both supplies are sharing the same SoftStart capacitor. Equation 12 gives the Soft-Start time, though the SS/TR current has to be doubled. Details about
these and other tracking and sequencing circuits are found in SLVA470.
Note: If the voltage at the FB pin is below its typical value of 0.7 V, the output voltage accuracy may have a
wider tolerance than specified. The current of 2.5 A out of the SS/TR pin also has an influence on the tracking
function, especially for high resistive external voltage dividers on the SS/TR pin.
10.1.6 Output Filter and Loop Stability
The devices of the TPS6213X family are internally compensated to be stable with L-C filter combinations
corresponding to a corner frequency to be calculated with Equation 13:
f LC =
1
2p L C
(13)
Proven nominal values for inductance and ceramic capacitance are given in Table 2 and are recommended for
use. Different values may work, but care has to be taken on the loop stability which is affected. More information
including a detailed LC stability matrix can be found in SLVA463.
The TPS62135x devices include an internal 15 pF feedforward capacitor, connected between the VOS and FB
pins. This capacitor impacts the frequency behavior and sets a pole and zero in the control loop with the resistors
of the feedback divider, per equation Equation 14 and Equation 15:
fzero =
fpole =
1
2p R1 15 pF
(14)
1
1
1
+
2p 15 pF R1 R 2
(15)
Though the TPS6213x devices are stable without the pole and zero being in a particular location, adjusting their
location to the specific needs of the application can provide better performance in Power Save mode and/or
improved transient response. An external feedforward capacitor can also be added. A more detailed discussion
on the optimization for stability versus transient response can be found in SLVA289 and SLVA466.
EN
1 uH
SW
VOS
R3
R 1 100k
FB
R2
VSEL
22uF
PG
MODE
FB2
SS/TR
GND
TPS62135, TPS621351
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VOUT
- 1
R1 = R 2
VFB
(16)
R1
R2
0.8 V
51 k
360 k
0.799 V
1.2 V
130 k
180 k
1.206 V
1.5 V
150 k
130 k
1.508 V
1.8 V
470 k
300 k
1.797 V
2.5 V
620 k
240 k
2.508 V
3.3 V
560 k
150 k
3.313 V
5V
510 k
82 k
5.054 V
9V
510 k
43 k
9.002 V
12 V
1000 k
62 k
11.99 V
100
100
90
90
80
80
70
70
Efficiency (%)
Efficiency (%)
60
50
40
VIN = 3 V
VIN = 5 V
VIN = 8 V
VIN = 10 V
VIN = 12 V
VIN = 15 V
30
20
10
0
1E-5
0.0001
Vout = 1.2 V
0.001
0.01
Output Current (A)
PFM
0.1
60
VIN = 3 V
VIN = 5 V
VIN = 8 V
VIN = 10 V
VIN = 12 V
VIN = 15 V
50
40
30
20
10
0
1E-5
0.0001
D001
TA= 25 C
Vout = 1.2 V
0.001
0.01
IOUT (A)
PWM
0.1
4
D001
TA= 25 C
17
TPS62135, TPS621351
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100
100
90
90
80
80
70
70
Efficiency (%)
Efficiency (%)
60
50
40
VIN = 3 V
VIN = 5 V
VIN = 8 V
VIN = 10 V
VIN = 12 V
VIN = 15 V
30
20
10
0
1E-5
0.0001
0.001
Vout = 1.8 V
0.01
IOUT (A)
0.1
VIN = 3 V
VIN = 5 V
VIN = 8 V
VIN = 10 V
VIN = 12 V
VIN = 15 V
60
50
40
30
20
10
0
1E-5
PFM
TA= 25 C
90
90
80
80
70
70
Efficiency (%)
Efficiency (%)
100
60
50
VIN = 4 V
VIN = 5 V
VIN = 6 V
VIN = 8 V
VIN = 10 V
VIN = 12 V
VIN = 15 V
40
30
20
10
0.001
Vout = 3.3 V
0.01
IOUT (A)
0.1
60
40
20
10
0
1E-5
80
70
70
Efficiency (%)
Efficiency (%)
90
80
60
50
40
Vout = 5 V
0.01
IOUT (A)
PFM
0.1
18
0.1
4
D001
PWM
TA= 25 C
60
50
40
VIN = 6 V
VIN = 8 V
VIN = 10 V
VIN = 12 V
VIN = 15 V
20
10
4
0
1E-5
0.0001
D001
TA= 25 C
0.01
IOUT (A)
30
VIN = 6 V
VIN = 8 V
VIN = 10 V
VIN = 12 V
VIN = 15 V
0.001
0.001
0.0001
0.0001
Vout = 3.3 V
90
0
1E-5
D001
TA= 25 C
50
100
10
VIN = 4 V
VIN = 5 V
VIN = 6 V
VIN = 8 V
VIN = 10 V
VIN = 12 V
VIN = 15 V
20
30
TA= 25 C
30
0.1
PWM
D001
PFM
0.01
IOUT (A)
100
0.0001
0.001
Vout = 1.8 V
0
1E-5
0.0001
D001
Vout = 5 V
0.001
0.01
IOUT (A)
PWM
0.1
4
D001
TA= 25 C
TPS62135, TPS621351
SLVSBH3A JUNE 2016 REVISED SEPTEMBER 2016
100
100
90
90
80
80
70
70
Efficiency (%)
Efficiency (%)
www.ti.com
60
50
40
30
60
50
40
30
20
20
VIN = 10 V
VIN = 12 V
VIN = 15 V
10
0
1E-5
0.0001
0.001
Vout = 9 V
0.01
IOUT (A)
0.1
VIN = 10 V
VIN = 12 V
VIN = 15 V
10
0
1E-5
PFM
TA= 25 C
1.215
D001
PWM
TA= 25 C
1.204
1.205
1.202
1.200
1.198
1.196
1.200
1.194
1.195
1.192
0.0001
0.001
Vout = 1.2 V
0.01
IOUT (A)
0.1
1.190
1E-5
PFM
TA= 25 C
0.001
0.01
IOUT (A)
0.1
4
D001
PWM
TA= 25 C
1.815
1.815
1.810
1.810
VOUT DC (V)
1.820
1.805
1.800
VIN = 3 V
VIN = 5 V
VIN = 8 V
VIN = 10 V
VIN = 12 V
VIN = 15 V
Vout = 1.8 V
0.0001
Vout = 1.2 V
1.820
0.0001
VIN = 3 V
VIN = 5 V
VIN = 8 V
VIN = 10 V
VIN = 12 V
VIN = 15 V
D001
VOUT DC (V)
1.206
1.210
1.780
1E-5
1.208
VOUT DC (v)
VOUT DC (V)
1.220
1.785
0.1
1.210
VIN = 3 V
VIN = 5 V
VIN = 8 V
VIN = 10 V
VIN = 12 V
VIN = 15 V
1.225
1.790
0.01
IOUT (A)
1.230
1.795
0.001
Vout = 9 V
1.190
1E-5
0.0001
D001
VIN = 3 V
VIN = 5 V
VIN = 8 V
VIN = 10 V
VIN = 12 V
VIN = 15 V
1.805
1.800
1.795
1.790
1.785
0.001
0.01
IOUT (A)
PFM
0.1
1.780
1E-5
0.0001
D001
TA= 25 C
Vout = 1.8 V
0.001
0.01
IOUT (A)
PWM
0.1
4
D001
TA= 25 C
19
TPS62135, TPS621351
www.ti.com
3.340
3.340
3.330
3.330
3.320
3.320
VOUT DC (V)
VOUT DC (V)
3.310
3.300
3.290
VIN = 4 V
VIN = 5 V
VIN = 8 V
VIN = 10 V
VIN = 12 V
VIN = 15 V
3.280
3.270
3.260
1E-5
0.0001
3.310
3.300
3.290
VIN = 4 V
VIN = 5 V
VIN = 8 V
VIN = 10 V
VIN = 12 V
VIN = 15 V
3.280
3.270
0.001
Vout = 3.3 V
0.01
IOUT (A)
0.1
3.260
1E-5
PFM
TA= 25 C
0.1
4
D001
PWM
TA= 25 C
5.050
VIN = 6 V
VIN = 8 V
VIN = 10 V
VIN = 12 V
VIN = 15 V
5.040
5.030
5.030
5.020
5.010
5.000
4.990
5.010
5.000
4.990
4.980
4.980
4.970
4.970
4.960
4.960
4.950
1E-5
0.0001
0.001
Vout = 5 V
0.01
IOUT (A)
0.1
VIN = 6 V
VIN = 8 V
VIN = 10 V
VIN = 12 V
VIN = 15 V
5.040
VOUT DC (V)
5.020
VOUT DC (V)
0.01
IOUT (A)
5.050
4.950
1E-5
0.0001
0.001
D001
PFM
TA= 25 C
Vout = 5 V
0.01
IOUT (A)
0.1
4
D001
PWM
TA= 25 C
9.100
9.100
VIN = 10 V
VIN = 12 V
VIN = 15 V
9.080
9.060
VIN = 10 V
VIN = 12 V
VIN = 15 V
9.080
9.060
9.040
VOUT DC (V)
9.040
VOUT DC (V)
0.001
Vout = 3.3 V
9.020
9.000
8.980
9.020
9.000
8.980
8.960
8.960
8.940
8.940
8.920
8.920
8.900
1E-5
0.0001
Vout = 9 V
0.001
0.01
IOUT (A)
PFM
0.1
8.900
1E-5
0.0001
D001
TA= 25 C
20
0.0001
D001
Vout = 9 V
0.001
0.01
IOUT (A)
PWM
0.1
4
D001
TA= 25 C
TPS62135, TPS621351
SLVSBH3A JUNE 2016 REVISED SEPTEMBER 2016
4.5
4.5
3.5
3.5
IOUT_max DC (A)
IOUT_max DC (A)
www.ti.com
3
2.5
2
1.5
1
2
1.5
TA = 25oC
TA = 85oC
TA = 125oC
0.5
0
3
11
VIN (V)
13
15
17
D001
11
VIN (V)
PWM
13
15
17
D001
Vout = 1.2 V
PWM
measurement taken until 4 A
Curves for TA= 25 C and TA= 85 C overlap
Vout = 1.8 V
4.5
4.5
3.5
3.5
IOUT_max DC (A)
IOUT_max DC (A)
2.5
TA = 25oC
TA = 85oC
TA = 125oC
0.5
3
2.5
2
1.5
1
2.5
2
1.5
1
TA = 25oC
TA = 85oC
TA = 125oC
0.5
TA = 25oC
TA = 85oC
TA = 125oC
0.5
0
3
Vout = 3.3 V
PWM
11
VIN (V)
13
15
17
D001
Vout = 5 V
11
VIN (V)
PWM
13
15
17
D001
4.5
4
IOUT_max DC (A)
3.5
3
2.5
2
1.5
1
TA = 25oC
TA = 85oC
TA = 125oC
0.5
0
9
10
Vout = 9 V
11
12
PWM
13
VIN (V)
14
15
16
17
D001
PFM
Io = 350 mA to 3.1 A;
TA= 25 C
21
TPS62135, TPS621351
SLVSBH3A JUNE 2016 REVISED SEPTEMBER 2016
www.ti.com
Vin = 6 V to 8.4 V;
Vout = 1.2 V
Vin = 12 V;
Vout = 1.2 V
PWM
PWM
Io = 1 A
TA= 25 C
Vin = 5 V;
Vout = 1.2 V
PFM
Io = 0.1 A
TA= 25 C
PWM
Rload = 1 k
TA= 25 C
Vin = 5 V;
Vout = 1.2 V
Io = 1 A
TA= 25 C
Io = 350 mA to 3.1 A
TA= 25 C
Vin = 6 V to 8.4 V;
Vout = 1.2 V
PFM
Vin = 5 V;
Vout = 1.2 V
PWM
Io = 1 A
TA= 25 C
TPS62135, TPS621351
www.ti.com
Vout = 1.8 V
PFM
Io = 350 mA to 3.1 A
TA= 25 C
Vin = 6 V to 8.4 V;
Vout = 1.8 V
PFM
Io = 1 A
TA= 25 C
PWM
Rload = 1 k
TA= 25 C
PWM
Io = 350 mA to 3.1 A
TA= 25C
Vout = 1.8 V
Vout = 1.8 V
Vin = 6 V to 8.4 V;
Vout = 1.8 V
PWM
Io = 1 A
TA= 25 C
Vout = 1.8 V
PFM
Io = 0.1 A
TA= 25 C
23
TPS62135, TPS621351
SLVSBH3A JUNE 2016 REVISED SEPTEMBER 2016
Vout = 1.8 V
PWM
www.ti.com
Io = 1 A
TA= 25 C
Vout = 3.3 V
PWM
Io = 1 A
TA= 25 C
PWM
Io = 1 A
TA= 25 C
Vout = 3.3 V
PFM
Io = 350 mA to 3.1 A
TA= 25 C
Vin = 6 V to 8.4 V;
Vout = 3.3 V
Io = 350 mA to 3.1 A
TA= 25 C
Vin = 6 V to 8.4 V;
Vout = 3.3 V
Vout = 3.3 V
PFM
PWM
Rload = 1 k
TA= 25 C
TPS62135, TPS621351
www.ti.com
Vout = 3.3 V
PFM
Io = 0.1 A
TA= 25 C
Vout = 5 V
PFM
Io = 350 mA to 3.1 A
TA= 25 C
PFM
Io = 1 A
TA= 25 C
Vout = 5 V
PWM
Io = 350 mA to 3.1 A
TA= 25 C
Io = 1 A
TA= 25 C
PWM
Vin = 6 V to 8.4 V;
Vout = 5 V
Vout = 3.3 V
Vin = 6 V to 8.4 V;
Vout = 5 V
PWM
Io = 1 A
TA= 25 C
25
TPS62135, TPS621351
SLVSBH3A JUNE 2016 REVISED SEPTEMBER 2016
Vout = 5 V
PWM
www.ti.com
Rload = 1 k
TA= 25 C
Vout = 5 V
PWM
Vout = 5 V
Io = 1 A
TA= 25 C
Vout = 9 V
Io = 300 mA to 2.7 A
TA= 25 C
PFM
Io = 300 mA to 2.7 A
TA= 25 C
26
PFM
Vin = 12 V to 15 V;
Vout = 9 V
PWM
Io = 0.1 A
TA= 25 C
Vout = 9 V
PFM
Io = 1 A
TA= 25 C
TPS62135, TPS621351
www.ti.com
Vin = 12 V to 15 V;
Vout = 9 V
PWM
Io = 1 A
TA= 25 C
Vout = 9 V
PFM
Io = 0.1 A
TA= 25 C
Vout = 9 V
PWM
Io = 1 A
TA= 25 C
2.5
3.0
2.0
Rload = 1 k
TA= 25 C
Vout = 9 V
PWM
1.5
1.0
IO = 0 A
IO = 1 A
IO = 2 A
IO = 3.5 A
0.5
0.0
2.5
2.0
1.5
1.0
IO = 0 A
IO = 1 A
IO = 2 A
IO = 3.5 A
0.5
0.0
Vout = 1.2 V
8
10
12
Input Voltage (V)
PWM
14
16
18
D001
TA= 25 C
Vout = 1.8 V
8
10
12
Input Voltage (V)
PWM
14
16
18
D001
TA= 25 C
27
TPS62135, TPS621351
www.ti.com
3.0
3.0
2.5
2.5
2.0
1.5
1.0
IO = 0 A
IO = 1 A
IO = 2 A
IO = 3.5 A
0.5
0.0
2.0
1.5
1.0
IO = 0 A
IO = 1 A
IO = 2 A
IO = 3.5 A
0.5
0.0
Vout = 3.3 V
8
10
12
Input Voltage (V)
14
16
18
10
12
Input Voltage (V)
D001
PWM
TA= 25 C
Vout = 5 V
PWM
14
16
18
D001
TA= 25 C
3.0
2.5
2.0
1.5
1.0
IO = 0 A
IO = 1 A
IO = 2 A
IO = 3 A
0.5
0.0
9
Vout = 9 V
10
11
12
13
14
Input Voltage (V)
15
16
17
D001
PWM
TA= 25 C
28
TPS62135, TPS621351
www.ti.com
EN
1 uH
SW
VOS
R1
C FF
FB2
R4
100k
FB
R3
22uF
R2
VSEL
PG
MODE
GND
SS/TR
(17)
29
TPS62135, TPS621351
SLVSBH3A JUNE 2016 REVISED SEPTEMBER 2016
www.ti.com
EN
1 uH
SW
VOS
22uF
FB
R4
VSEL
PG
MODE
FB2
SS/TR
GND
analog dimming
470pF
R5
(18)
spacing
The device now supplies a constant current set by resistor R4 from FB to GND. The minimum input voltage has
to be rated according the forward voltage needed by the LED used. More information is available in the
Application Note SLVA451.
spacing
10.3.2 Powering Multiple Loads
In applications where TPS62135x is used to power multiple load circuits, it may be the case that the total
capacitance on the output is very large. In order to properly regulate the output voltage, there needs to be an
appropriate AC signal level on the VOS pin. Tantalum capacitors have a large enough ESR to keep output
voltage ripple sufficiently high on the VOS pin. With low ESR ceramic capacitors, the output voltage ripple may
get very low, so it is not recommended to use a large capacitance directly on the output of the device. If there are
several load circuits with their associated input capacitor on a pcb, these loads are typically distributed across the
board. This adds enough trace resistance (Rtrace) to keep a large enough AC signal on the VOS pin for proper
regulation.
The minimum total trace resistance on the distributed load is 10 m. The total capacitance n x Cin in the use
case below was 32 x 47 uF of ceramic X7R capacitors.
30
TPS62135, TPS621351
www.ti.com
load
Rtrace
TPS62135
VIN = 12V
VIN
10uF
1 uH
Cin
VOUT = 1.8V
SW
VOS
EN
Rtrace
R3
R 1 100k
FB
R2
Cin
22uF
VSEL
PG
FB2
SS/TR
GND
load
Rtrace
Cin
MODE
load
load
Rtrace
Cin
load
Rtrace
Cin
load
VIN = 12V
VIN
10uF
1 uH
VOUT = 3.3V
SW
VOS
EN
560k
22uF
FB
150k
VSEL
PG
MODE
FB2
SS/TR
GND
3.3nF
DEVICE 2
TPS62135
VIN = 12V
VIN
10uF
EN
1 uH
VOUT = 1.8V
SW
VOS
470k
22uF
FB
300k
VSEL
R5 = 56k
PG
MODE
FB2
SS/TR
GND
R6 = 15k
31
TPS62135, TPS621351
SLVSBH3A JUNE 2016 REVISED SEPTEMBER 2016
www.ti.com
VIN
EN
L
SW
VOS
1 uH
R3
R 1 100k
COUT
FB
2 x 10uF
R2
VSEL
PG
MODE
FB2
SS/TR
GND
CSS
RSS
10k
32
TPS62135, TPS621351
www.ti.com
VIN
EN
L
SW
VOS
1 uH
R3
R 1 100k
FB
R2
VSEL
COUT
2 x 10uF
PG
MODE
FB2
SS/TR
GND
CSS
Copyright 2016, Texas Instruments Incorporated
Figure 79. Connecting CSS to the Internal Analog Ground by using FB2
33
TPS62135, TPS621351
SLVSBH3A JUNE 2016 REVISED SEPTEMBER 2016
www.ti.com
12 Layout
12.1 Layout Guidelines
A proper layout is critical for the operation of a switched mode power supply, even more at high switching
frequencies. Therefore the PCB layout of the TPS62135x demands careful attention to ensure operation and to
get the performance specified. A poor layout can lead to issues like poor regulation (both line and load), stability
and accuracy weaknesses, increased EMI radiation and noise sensitivity.
See Figure 80 for the recommended layout of the TPS62135x, which is designed for common external ground
connections. The input capacitor should be placed as close as possible between the VIN and GND pin of
TPS62135x. Also connect the VOS pin in the shortest way to VOUT at the output capacitor.
Provide low inductive and resistive paths for loops with high di/dt. Therefore paths conducting the switched load
current should be as short and wide as possible. Provide low capacitive paths (with respect to all other nodes) for
wires with high dv/dt. Therefore the input and output capacitance should be placed as close as possible to the IC
pins and parallel wiring over long distances as well as narrow traces should be avoided. Loops which conduct an
alternating current should outline an area as small as possible, as this area is proportional to the energy radiated.
Sensitive nodes like FB and VOS need to be connected with short wires and not nearby high dv/dt signals (for
example SW). As they carry information about the output voltage, they should be connected as close as possible
to the actual output voltage (at the output capacitor). The capacitor on the SS/TR pin as well as the FB resistors,
R1 and R2, should be kept close to the IC and connect directly to those pins and the system ground plane. The
same applies to R3 if FB2 is used to scale the output voltage.
The package uses the pins for power dissipation. Thermal vias on the VIN, GND and SW pins help to spread the
heat through the pcb.
In case any of the digital inputs EN, VSEL or MODE need to be tied to the input supply voltage at VIN, the
connection must be made directly at the input capacitor as indicated in the schematics.
The recommended layout is implemented on the EVM and shown in its User's Guide, SLVUAI7.
GND
GND
C1
C2
SW
VIN
PG
VOS
MODE
VSEL
GND
EN
SS/TR
FB
FB2
VIN
L1
R2
R3
R1
C3
VOUT
34
TPS62135, TPS621351
www.ti.com
35
TPS62135, TPS621351
SLVSBH3A JUNE 2016 REVISED SEPTEMBER 2016
www.ti.com
PRODUCT FOLDER
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
TPS62135
Click here
Click here
Click here
Click here
Click here
TPS621351
Click here
Click here
Click here
Click here
Click here
13.5 Trademarks
DCS-Control, AEE, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
13.7 Glossary
SLYZ022 TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
36
TPS62135, TPS621351
www.ti.com
37
www.ti.com
25-Sep-2016
PACKAGING INFORMATION
Orderable Device
Status
(1)
Eco Plan
Lead/Ball Finish
(2)
(6)
(3)
Op Temp (C)
Device Marking
(4/5)
TPS621351RGXR
ACTIVE
VQFN-HR
RGX
11
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
621351
TPS621351RGXT
ACTIVE
VQFN-HR
RGX
11
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
621351
TPS62135RGXR
ACTIVE
VQFN-HR
RGX
11
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
62135
TPS62135RGXT
ACTIVE
VQFN-HR
RGX
11
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
62135
(1)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Addendum-Page 1
Samples
www.ti.com
25-Sep-2016
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
24-Sep-2016
Device
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
TPS621351RGXR
VQFNHR
RGX
11
3000
180.0
8.4
2.25
3.25
1.05
4.0
8.0
Q1
TPS621351RGXT
VQFNHR
RGX
11
250
180.0
8.4
2.25
3.25
1.05
4.0
8.0
Q1
TPS62135RGXR
VQFNHR
RGX
11
3000
180.0
8.4
2.25
3.25
1.05
4.0
8.0
Q1
TPS62135RGXT
VQFNHR
RGX
11
250
180.0
8.4
2.25
3.25
1.05
4.0
8.0
Q1
Pack Materials-Page 1
24-Sep-2016
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TPS621351RGXR
VQFN-HR
RGX
11
3000
210.0
185.0
35.0
TPS621351RGXT
VQFN-HR
RGX
11
250
210.0
185.0
35.0
TPS62135RGXR
VQFN-HR
RGX
11
3000
210.0
185.0
35.0
TPS62135RGXT
VQFN-HR
RGX
11
250
210.0
185.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
RGX0011A
2.1
1.9
1 MAX
C
SEATING PLANE
0.05
0.00
0.08 C
2X 1.5
(0.2) TYP
6X 0.5
7
2X 0.5
3X
0.3
0.2
3
SYMM
1
8X
PIN 1 ID
11
SYMM
8X
0.45
0.35
0.3
0.2
0.1
0.05
C B
A
C ALL PADS
4221908/A 10/2015
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
RGX0011A
6X (0.5)
8X (0.25)
11
8X (0.6)
1
2X (0.5)
SYMM
(2.8)
(R0.05) TYP
3
3X (0.25)
3X (2.4)
SYMM
0.05 MAX
ALL AROUND
METAL
0.05 MIN
ALL AROUND
SOLDER MASK
OPENING
SOLDER MASK
OPENING
SOLDER MASK
DEFINED
PADS 1-3
METAL UNDER
SOLDER MASK
NOTES: (continued)
3. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271).
4. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
RGX0011A
6X (0.5)
8X (0.25)
11
8X (0.6)
6X
EXPOSED METAL
9X (0.66)
9X (0.25)
SYMM
(2.8)
(0.5) TYP
3
METAL UNDER
SOLDER MASK
TYP
(R0.05) TYP
SOLDER MASK
EDGE, TYP
(0.86) TYP
4
SYMM
4221908/A 10/2015
NOTES: (continued)
5. For alternate stencil design recommendations, see IPC-7525 or board assembly site preference.
www.ti.com
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Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other
changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest
issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and
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TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TIs terms
and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary
to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily
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