ESc201 : Introduction to Electronics

ESc201:IntroductiontoElectronics
Combinational Circuit Design

Dr. K
D
K. V
V. S
Srivastava
i
t
Dept. of Electrical Engineering
IIT Kanpur
1

Design Flow

System Description

system

x
0
0
0
0
1
1
1
1

Truth Table

y z
0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

f
0
1
0
1
0
1
0
1

Boolean Expression

f = x .y . z + x . y . z + x . y . z + x . y . z
Minimized
Boolean Expression

This design
approach
becomes
difficult to use

f = x . z + x. z
x
y
y

Gate Netlist

z
x
z

General Approach
Sub-Sub-system-1

S b
Sub-system-1
t
1

Sub-system-3

System
Sub-system-2

There are certain sub-systems or blocks that are used quite

often such as :
1. Decoders, Encoders
2 Multiplexers
2.
3. Adder/Subtractors, Multipliers
4. Comparators
5 Parity
5.
P it Generators
G
t
6. ..

Decoders
In general maps a smaller number of inputs to a larger set of
outputs
y0
A
B

2-to-4 line
decoder

y1
y2
y3

A Y0 Y1 Y2 Y3

0 0 1

0 0 0

0 1 0

1 0 0

1 0 0

0 1 0

1 1 0

0 0 1
4

Example
M-1

M-1

M-2

2-to-4
decoder

M-2

M-3

M-3

M4
M-4

M4
M-4

Decoder with Enable Input

E B

2/4

A
B

2/4

y0

x 0

0 0 0

y1
y2

1 0 0 1

0 0 0

1 0 1 0

1 0 0

y3

1 1 0 0

0 1 0

1 1 1 0

0 0 1

y0
y1
y2

A
B

A Y0 Y1 Y2 Y3

y3

E B

A Y0 Y1 Y2 Y3

x 0

0 0 0

0 0 0 1

0 0 0

0 0 1 0

1 0 0

0 1 0 0

0 1 0

0 1 1 0

0 0 1

Decoder: gate Implementation

E

2/4

y0
y1
y2

A
B

y3

E B

A Y0 Y1 Y2 Y3

x 0

0 0 0

1 0 0 1

0 0 0

1 0 1 0

1 0 0

1 1 0 0

0 1 0

1 1 1 0

0 0 1

Y0 =E.B.A ; Y1 =E.B.A ; Y2 =E.B.A ; Y3 =E.B.A

E

E.B.A
Y0

E.B.A
Y1

E.B.A
Y2
B

E.B.A
Y3

A n to 2n decoder is a minterm generator

E .B.A

Y0

y min term

0
0
1
1

0
1
0
1

x.y
x.y
x.y
x.y

E .B.A

m0
m1
1
m2
m3

Y1

E .B.A
Y2
B

E .B.A
Y3

It can be used to implement any combinational circuit

B A f1
0
0
1
1

0
1
0
1

0
1
1
0

2/4
1

y0
y1
y2

1
0

A
B

y3

0
1
0
0

Implementation of a 3-variable function with a 3-to-8 decoder

1

C B A
0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

f
1
0
1
0
1
0
0
0

0
0
0

1
0
0
0
0
0
0
0

Although it is easy to implement any combinational circuit with this method , it

is often very inefficient in terms of gate utilization. Note that this method does
not require any minimization.
9

3/8 decoder using 2/4 decoders

E C B A y0

y1 y2 y3 y4 y5 y6 y7

0 x x x

0 0 0 0

0 0 0

1 0 0 0

1 0 0 0

0 0 0

1 0 0 1

0 1 0 0

0 0 0

1 0 1 0

0 0 1 0

0 0 0

1 0 1 1

0 0 0 1

0 0 0

1 1 0 0

0 0 0 0

0 0 0

1 1 0 1

0 0 0 0

1 0 0

1 1 1 0

0 0 0 0

0 1 0

1 1 1 1

0 0 0 0

0 0 1

E
E

2/4

1
0

C
0

2/4

y1 1
y2 0

1
A
0 B
E

y0 0

y3 0
2/4

y4 0
y5 0
y6 0

A
B

E B

A Y0 Y1 Y2 Y3

x 0

0 0 0

1 0 0 1

0 0 0

1 0 1 0

1 0 0

1 1 0 0

0 1 0

1 1 1 0

0 0 1

y7 0

10

How many 2/4 decoders are required to implement a 4/16 decoder ?

Seven segment decoder

a
f

c
d

c
d

b
g

5
5
5
5
5

D
C
B

7-segment
decoder

(abcdefg)

5
f

0
g
11

Seven segment decoder

a
f

D
C

7-segment
g
decoder

(abcdefg)

A
e

c
d

output: a

BA
DC 00
00 1

01

11

10

01

11

10

12

Please determine the simplified POS

D
C
B

7-segment
decoder

(abcdefg)

A
BL

a = (D + B ) (C + A) (D + C + B + A )

( )( )(

a = DB CA D C B A

7449 BCD to seven segment decoder

13

Encoders
An encoder performs the inverse operation of a decoder.
d3

4/2
0

1
2
3

d1 d0
d3d2 00

00
01

11
10

01

11

10
1

d2 d1 d0 B A

0 0

1 0 0

0 1

0 0 1

1 0

0 1 0

0 0

0 1 1

d1 d 0
d3d2 00

11

00
01

01

10
0

B = d1 d 0

11
1

10

A = d 2 d 0 Vacants are dont care

14

Multiplexers
I0
I1

2:1
mux

I0

I1

S
I0

I0
1

I0

I1

Y0

0
S

0
15

I0

00

I1
I2

01 4:1
10 mux

I3

11

y
S0

S1

S1 S0

S1 S 0

0 0

I0

0 1

I1

1 0

I2

1 1

I3

I0

I1

I2

I3

16

Implementing Boolean expressions using Multiplexers

y = x1 x2 + x1 x2

x2

x2

0
y
1

x1

x1 x2

y = x2 when x1 = 0

y = x2 when x1 = 1

17

F ( x, y, z ) = (1, 2, 6, 7)
A 3 variable function can be implemented with a 4:1 mux with 2 select lines

x
0
x

00

01
10

11
y

z F

0 0

0
F = 0 when yz = 00

1
0

0 0
0 1

0
1
F = x when yz =01

1
0

0 1
1 0

0
1
F = 1 when yz = 10

z
1
0

1 0
1 1

1
0
F = x when yz = 11

1 1

Mux is more efficient way of implementing combinational circuits as compared to

decoders.
18

Mux. expansion
E
I0

E S

I1

1
S

I1

0 0

I0

0 1

I1

I0

1 0

I2

1 1

I1

1 1

I3

0
I1

S0 1

1 0

I0

S1 S0

I2

I3

I1
0

S0

S1
19

Mux. expansion
E
I0

E S

I1

1
S

I0

I1

0 0

I0

0 1

I1

1 0

I0

1 0

I2

1 1

I1

1 1

I3

E
0

S1 S0

I2

I3

I3
I3

S0

S0

S1
20

DeMultiplexer
u-1

u-11

u-1

u-2

u-22

u-2

u-11

u-22

Demux

Mux
u-3

u-33

u-3

u-4

u-44

u-4

Data
S1
S0

0
1
2
3

u-33

u-44

S1

S0

y0

y1

y2

y3

D
21

Demultiplexer is very much like a decoder

E

Data
S1
S0

0 1
1 0
1 1

y0
y1
y2

0
1
2
3

y3

A
B

Dmux

S1 S0 y0 y1 y2 y3
0 0

2/4

I0 0 0 0
0 I1 0 0
0 0 I2 0
0 0 0 I3

E B

A Y0 Y1 Y2 Y3

x 0

0 0 0

1 0 0 1

0 0 0

1 0 1 0

1 0 0

1 1 0 0

0 1 0

1 1 1 0

0 0 1

Data

S0

Data
Y0

Y0
A

Y1

Y1

0
S1

Y2

Y2
B

0
Y3

Y3

22

Comparator

A = A3 A2 A1 A0 xi = Ai .Bi + Ai .Bi

B = B3 B2 B1 B0

for i = 0,1,2,3
0123

where xi = 1 only if the pair of bits in position i are

equal (i.e.,
(i e if both are 1 or both are: 0)
0).

( A = B ) = x3 x2 x1 x0

all xi variable must be equal to 1

takes feedbck frm
prev and check
next digit

( A > B ) = A3 B3 + x3 A2 B2 + x3 x2 A1 B1 + x3 x2 x1 A0 B0
( A < B ) = A3 B3 + x3 A2 B2 + x3 x2 A1 B1 + x3 x2 x1 A0 B0
23

( A < B ) = A3 B3 + x3 A2 B2
+ x3 x2 A1 B1 + x3 x2 x1 A0 B0

( A > B ) = A3 B3 + x3 A2 B2
+ x3 x2 A1 B1 + x3 x2 x1 A0 B0

( A = B ) = x3 x2 x1 x0

24

Adder
S

Half Adder

a b

0 0

0 0

0 1

1 0

1 0

1 0

1 1

0 1

S = a.b + a.b ; C = a.b

a b Cin S Cout

1
111
110
--------1101

0 0 0 0 0
0 0 1 1 0
0 1 0 1 0

Cout

F ll Add
Full
Adder

Cin

0 1 1 0 1
1 0 0 1 0
1 0 1 0 1

1 1 0 0 1
1 1 1 1 1

S = a.b.cin + a.b.cin + a.b.cin + a.b.cin ;

Cout = a.b.cin + a.b.cin + a.b.cin + a.b.cin

25

S = a.b.cin + a.b.cin + a.b.cin + a.b.cin

S = Cin ( a b)

Cout = a.b.Cin + a.b.Cin + a.b.Cin + a.b.Cin

a b Cin S Cout

Cout = Cin (a.b + a.b) + a.b = Cin .(a b) + a.b

a

ab

0 0 0 0 0
0 0 1 1 0
0 1 0 1 0

Cin (a b)

0 1 1 0 1

1 0 0 1 0
1 0 1 0 1

Cin .(a b)

1 1 0 0 1
1 1 1 1 1

a.b
Cout
Cin

26

4-bit Adder
S(0:3)

Cout

A 3A 2A 1A 0 B 3B 2B 1B 0 S 3S 2S 1S 0

4-bit adder

C3 C2 C1

Cout

0000

0000

0000

0000

0001

0001

0001

0000

0001

A 3 A 2 A 1A 0
B 3 B 2 B 1B 0
C 4 S 3 S 2 S 1S 0

A(0:3)

B(0:3)

S3

C2

C3

C4

C1

FA

FA

A3

B3

S0

S1

S2

A2

FA

B2

A1

FA

B1

A0

B0

27

Subtraction

A B = A + B +1

A - B = A + 2s complement of B
A - B = A + 1s complement of B+1

FA

FA

FA

B3
A3

FA

B2
A2

B1
A1

B0
A0
1

B3

B2

B1

B0

B0 1 = B0 .1 + B0 .1 = B0
One needs add a circuit for predicting errors resulting from overflow
28

Adder/Subtractor
FA

FA

A3

FA

B3

A2

FA

B2

A1

01

FA

B1

A0

A3

FA

A2

A3

A1

A0
1

FA

B2

FA

A2

FA

B0
B3

FA

FA

B1

B0

FA

A1

A0
M=1

B3

B2

B1

B0

B0 0 = B0 .0
0 + B0 .0
0 = B0

M = 0 for
f Adder
dd

B0 1 = B0 .1 + B0 .1 = B0

M=1

29
for Subtractor