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Xilinx

google
SVN
2007 5 10
google SVN

3 7

6 8

35678

2007-12-2

10
8

Xilinx FPGA MicroBlaze


MicroBlaze ucLinux
Xilinx XUP VIIPRO
PowerPC Xilinx
Spartan3E Starter Kit Microblaze Mini VOS
Xilinx XUP VIIPRO Microblaze


2007-12-2

........................................................................................................................7
1.1 ................................................................................................................7
1.1.1 .................................................................................................7
1.1.2 .................................................................................................7
1.2 ............................................................................................................8
1.3 ............................................................................................................9
GNU .....................................................................................................................10
2.1 GNU ..........................................................................................................10
2.2 ..............................................................................................................................10
2.2.1 GCC ..............................................................................................................10
2.2.2 GCC ..............................................................................................................11
2.2.3 GCC ......................................................................................................12
2.2.4 GCC ...........................................................................................13
2.2.5 Gdb ............................................................................................................14
2.3 .........................................................................................................................19
2.3.1 Make ......................................................................................................19
2.3.2 Makefile ........................................................................................................20
2.3.3 makefile .........................................................................................................21
2.3.4 makefile .........................................................................................................25
2.3.5 autotools .......................................................................................................26
2.4 ..........................................................................................................................28
2.4.1 .......................................................................................................28
2.4.2 ........................................................................................................29
2.4.3 CVS ...........................................................................................................30
2.4.4 Subversion..............................................................................................................33
FPGA .....................................................................................38
3.1 FPGA ...........................................................................................................38
3.1.1 PLD ..............................................................................................................38
3.1.2 FPGA ............................................................................................................39
3.2 MicroBlaze ...........................................................................................................43
3.2.1 MicroBlaze ........................................................................................44
3.2.2 MicroBlaze ................................................................................................46
3.2.3 Micro Blaze ..............................................................................47
3.2.4 MicroBlaze ................................................................................50
3.2.5 MicroBlaze ....................................................................................51
3.2.6 MicroBlaze ....................................................................................52
3.2.7 MicroBlaze ....................................................................................53
3.2.8 MicroBlaze FPUFloating Point Unit ...............................................54
3.2.9 MicroBlaze Cache.........................................................................54
3.3 MicroBlaze ...................................................................................................56
3.3.1 OPB.......................................................................................................................56

3.3.2 LMB.......................................................................................................................56
3.3.3 XCL.......................................................................................................................58
3.3.4 FSL.......................................................................................................................58
3.3.5 .........................................................................................59
3.4 Xilinx ........................................................................................59
3.4.1 Xilinx ....................................................................59
3.4.2 EDK ..............................................................................................60
3.4.3 Xilinx ............................................................................62
Microbalze .........................................................................................66
4.1 ..............................................................................................................66
4.2 IP.....................................................................................................90
4.3 IP ....................................................................................110
4.4 ....................................................................................................135
4.5 ...................................................................................................................156
4.6 .....................................................................................................184
............................................................................................................202
5.1 ....................................................................................................202
5.1.1 ..........................................................................................202
5.1.2 ......................................................................................................205
5.2 ....................................................................................................206
5.2.1 BSP ......................................................................................................................206
5.2.2 .............................................................................................................208
5.2.3 POSIX ..................................................................................................................216
5.3 ....................................................................................................219
5.3.1 Microblaze ..............................................................219
5.3.2 uCLinux ...........................................................................228
5.3.3 EDK uClinux ..............................................................235
5.3.4 uClinux ................................................................................................251
5.3.5 uClinux .......................................................................................260
5.3.6 uClinux .......................................................................................268
5.4 ....................................................................................................274
........................................................................................................277
6.1 .........................................................................................................................277
6.2 PowerPC ...................................................................................278
6.3 ................................................................................................301
6.4 ................................................................................................................................315
Mini VOS .............................................................................................316
7.1 .........................................................................................................................316
7.2 MicroBlaze ...........................................................................................317
7.3 EDK ......................................................................................334
7.4 uClinux .......................................................................................339
7.4.1 .................................................................................................340
7.4.2 .............................................................................................342
7.5 EDK uClinux .............................................................344

7.6 LED VOS ................................................................................357


...............................................................................................................................363
................................................................................................................372
8.1 .........................................................................................................................372
8.2 MicroBlaze ...........................................................................................373
8.3 EDK ......................................................................................381
8.4 uClinux .......................................................................................388
8.4.1 .................................................................................................388
8.4.2 .............................................................................................390
8.5 uClinux ...........................................................................................................392
8.6 ................................................................................................................407
8.7 ................................................................................................................408


1.1
1.1.1

1
2
3

1.1.2
30 4

CPU
CPU


(API)

Internet
Internet Internet
Internet
Internet

1.2

4
mW W

1.3

1.

2.

3.

4.

GNU
2.1 GNU
GNU GNU's Not UnixGNU
Richard Stallman 1983 9 27
Richard Stallman net.unix-wizards
GNU
GNU
GNU Unix (free software system)
Richard Stallman GNU GNU

Unix
GNU Unix Unix
GNU
1991 Linux GNU
GNU BashGCC Linus GNU
GNU/Linux : Linux
GNU

2.2
2.2.1 GCC
Linux GCC GNU
GNU GCC

20%~30%
GCC C GNU C Compiler
GCC GCC
CC++AdaObject-C Java GCC
GNU C CompilerGNU Compiler Collection

GNU

2.2.2 GCC
GCC GNU/Linux
GCC FPGA
Microblaze PowerPC

PC
ARM GCC 40
X86RS6000ArmPowerPC

GCC CC++
GCC a.out
Linux
GCC
GCC
.c C
.a
.C.cc .cxx C++
.h
.i C
.ii C++
.m Objective-C
.o

.s
.S

2.2.3 GCC
GCC C GCC C

(Preprocessing)(Compilation)(Assembly)
(Linking) 2-1

GCC

cpp

cc1

as(assembler)

ld(linker)

g++
2-1 GCC

GCC cpp
(include)( define ) cc1
g++.o
as .s
.o
GCC ld
GCC

2.2.4 GCC
GCC
GCC 100

GCC gcc [options] [filenames] options


filenames 2-1

-ansi

ANSI C

-c

-DMACRO

1 MACRO

-DMACRO=DEFN

DEFN MACRO

-E

-g

-IDIRECTORY

DIRECTORY

-LDIRECTORY

DIRECTORY

-lLIBRARY

LIBRARY

-o FILE

-O0

-O -O1

-O2

-O3

-O2 inline

-static

-w

-Wall

2-1 GCC

GCC
http://gcc.gnu.org/ test.c C

gcc test.c
a.out

test1.c test2.c
test
gcc test1.c test2.c -lm -o test
-lm libm.a

2.2.5 Gdb

Windows VC
Linux
Gdb GNU UNIX/Linux
VC

Linux Vi Emacs
/*test.c*/
#include <stdio.h>
int sum(int m);
int main()
{
int i,n=0;

sum(50);
for(i=1; i<=50; i++)
{
n += i;
}
printf("The sum of 1-50 is %d \n", n );
}
int sum(int m)
{
int i,n=0;
for(i=1; i<=m;i++)
n += i;
printf("The sum of 1-m is %d\n", n);
}
Gcc test.c -g

Gdb

[root@localhost Gdb]# gcc -g test.c -o test


Gdb
Gdb Gdb
.c Gcc Gdb

[root@localhost Gdb]# gdb test


GNU Gdb Red Hat Linux (6.3.0.0-1.21rh)
Copyright 2004 Free Software Foundation, Inc.
GDB is free software, covered by the GNU General Public License, and you are
welcome to change it and/or distribute copies of it under certain conditions.
Type "show copying" to see the conditions.
There is absolutely no warranty for GDB. Type "show warranty" for details.
This GDB was configured as "i386-redhat-linux-gnu"...Using host libthread_db

library "/lib/libthread_db.so.1".
(gdb)
Gdb Gdb
gdb
1
Gdb llist
(Gdb) l
1

#include <stdio.h>

int sum(int m);

int main()

int i,n=0;

sum(50);

for(i=1; i<=50; i++)

n += i;

10

(Gdb) l
11

printf("The sum of 150 is %d \n", n );

12
13

14

int sum(int m)

15

16

int i,n=0;

17

for(i=1; i<=m;i++)

18

n += i;

19
20

printf("The sum of 1m is = %d\n", n);


}

Gdb

Gdb b

(Gdb) b 6
Breakpoint 1 at 0x804846d: file test.c, line 6.

Gdb

3
info b Gdb

(Gdb) info b
Num Type

Disp Enb Address

keep y

breakpoint

What

0x0804846d in main at test.c:6

4
Gdb r
run
r
(Gdb) r
Starting program: /root/workplace/Gdb/test
Reading symbols from shared object read from target memory...done.
Loaded system supplied DSO at 0x5fb000

Breakpoint 1, main () at test.c:6


6

sum(50);

Gdb p
(Gdb) p n
$1 = 0
(Gdb) p i
$2 = 134518440
i
i
n
6
nnextsstep
sns
VC step in
n VC step over

(Gdb) n
The sum of 1-m is 1275
7

for(i=1; i<=50; i++)

(Gdb) s
sum (m=50) at test.c:16
16

int i,n=0;

n sum
s sum
7
ccontinue

n
(Gdb) c
Continuing.
The sum of 1-50 is :1275
Program exited with code 031.

2.3
2.3.1 Make
Linux
Gcc Gdb
Make

Gcc

2.2.3

Make
Make

Makefile
Linux

2.3.2 Makefile
makefile , make
Make makefile
IDE

Delphi make
Visual C++ nmake
Linux GNU make

Makefile Make
Makefile Makefile
target Object File
Label

prerequisites target
Commandmake

Targetprerequisites
Command
hello.c hello.h hello.o
gcc gcc c hello.c Makefile
hello.o: hello.c hello.h
gcc c hello.c o hello.o
make make make target make
Makefile makefile target
command
[root@localhost makefile]# make hello.o
gcc c hello.c o hello.o
[root@localhost makefile]# ls

hello.c hello.h hello.o Makefile


Makefile hello.ohello.o

tab 8 space
make

2.3.3 makefile
Makefile
Makefile Shell
Makefile
Makefile Makefile2
5 C
edit : main.o kbd.o
cc -o edit main.o kbd.o
main.o : main.c defs.h
cc -c main.c
kbd.o : kbd.c defs.h command.h
cc -c kbd.c
clean :
rm edit main.o kbd.o
Makefile target editmain.o kbd.o
make
edit make edit
make main.o
kbd.o
editmain.okbd.o
main.omain.cdefs.h
main.ogcc Wall O -g c
main.c -o main.omain.omain.okbd.o
make main.o
kbd.oeditmain.o

kbd.oedit
make Make

Makefilemake Makefile
Makefile

makefile Makefile

CFLAGS = $(CFLAGS) -O

VAR=var
VAR=var
Make $(VAR)
:
#
=

fooFOOFoo

makefile

Makefile OBJS main.o


kbd.o CC Gcc CFLAGS -Wall -O g

Makefile

Makefile
OBJS = main.o kbd.o
CC = cc
edit : $(OBJS)
$(CC) $(OBJS) -o edit
main.o : main.c defs.h
$(CC) -c main.c
kbd.o : kbd.c defs.h command.h
$(CC) -c kbd.c

Makefile
OBJS
Makefile

2-2
Makefile

AR

ar

AS

as

CC

C cc

CPP

C $(CC) E

CXX

C++ g++

FC

FORTRAN f77

RM

rm f

ARFLAGS

ASFLAGS

CFLAGS

CPPFLAGS

CXXFLAGS

C++

FFLAGS

FORTRAN
2-2 Makefile

CC CFLAGS CC
CC=Gcc

Gcc
Makefile Makefile

2-3 Makefile

$*

$+
$<

$?

$@

$^

$%

2-3 Makefile

Makefile
OBJS = main.o kbd.o
CC = cc
edit : $(OBJS)
$(CC) $^ -o $@
main.o : main.c defs.h
$(CC) -c $< -o $@
kbd.o : kbd.c defs.h command.h
$(CC) -c $< -o $@
Makefile
make
Makefile

2.3.4 makefile
Makefile Make
Makefile
Makefile $(CC) $(CFLAGS) -c $< -o $@
Makefile make

1
make
Make

OBJS = main.o kbd.o


CC = cc
edit: $(OBJS)
$(CC) $^ -o $@
main.o : main.c defs.h
kbd.o : kbd.c defs.h command.h

Make
.o .c
make
2-4

C .c .o

$(CC) c $(CPPFLAGS) $(CFLAGS)

C++.cc .C .o

$(CXX) -c $(CPPFLAGS) $(CXXFLAGS)

Pascal .p .o

$(PC) -c $(PFLAGS)

Fortran .r -o

$(FC) -c $(FFLAGS)

2-4 Makefile

make

Makefile
%
Makefile
OBJS = main.o kbd.o
CC = cc
edit: $(OBJS)
$(CC) $^ -o $@
%.o : %.c
$(CC) -c $< -o $@
make make
make Makefile
make 2-5
make

-C dir

Makefile

-f file

file Makefile

-i

-I dir

Makefile

-n

-p

make

-s

-w

make
2-5 make

2.3.5 autotools
Makefile make Makefile

Makefile make
autotools
Makefile

Linux autotools
Makefile
autotools
which

aclocal
autoscan
autoconf
autoheader
automake
autotools Makefile

aclocal aclocal.m4
configure.scanconfigure.in autoconf
configure

2-1

2-2 autotools Makefile

2.4
Revision Control Version Control (System)(Source)
Code Management

(revision)1
2

2.4.1
1

-- VSS
--
z

2
CVSSubversion

2
-
CVSSubversion

CVS
SubversionP4

BazaarGit
Mercurial

2.4.2

(Branch):

(Check-out):

(Commit):

(Conflict):

(Export):

(Import):

(Merge):

(Repository):

Working copy

2.4.3 CVS
1 CVS
CVS linux windows windows CVS
cvsnt RH linux CVS

> rpm qa | grep cvs cvs


cvs
cvs cvs
>rpm ivh /mnt/cdrom/RedHat/RPMS/cvs-x.x.x-x.i386.rpm
cvsserver
>mkdir -p /home/cvs/cvsroot
2 cvs cvs
>groupadd pjt_faceit

>useradd zhaofeng
passwd
>passwd zhaofeng
cvs
>chown zhaofeng.pjt_faceit /home/cvs/cvsroot/ -R
>chown 775 /home/cvs/cvsroot/ -R
cvs
>cvs d /home/cvs/cvsroot/ init
/home/cvs/cvsroot CVSROOT cvs

cvs
/etc/services
cvspserver 2401/tcp
cvspserver 2401/udp
2401 cvs tcp udp cvs

3 xinetd cvs
cvs xinetd
/etc/xinetd.d cvs cvs cvspserver
RH-linux cvs

service cvspserver
{
flags
= REUSE
socket_type
= stream
wait
= no
user
= root
server
= /usr/bin/cvs
server_args
= -f --allow-root=/home/cvs/cvsroot pserver
log_on_failure += USERID
disable
= no
}
-allow-root cvsserver
login : no such repository cvs
flags setsockopt socket
REUSE socket
disable no
yesserver_args -f allow-root space login
xinetd
>/sbin/service xinetd restart
/etc/init.d/xinetd restart
xinetd xinetd not recognized service
yum install xinetd xinetd RH CD rpm ihv
XXXX
cvspserver

>netstat l | grep cvspserver


, cvs :
tcp 0 0 *:cvspserver *:* LISTEN
4 CVSROOT
>export
CVSROOT=:pserver:zhaofeng:123456@localhost:/home/cvs/cvsroot
>cvs login

5 CVS

z
cvs checkout project_name
project_name
z
cvs update
z CVS
cvs commit -m "write some comments here" file_name
-m
z
touch new_file
cvs add new_file
Word cvs add kb
2 (k b binary)

cvs add -kb new_file.gif


cvs add -kb readme.doc

cvs ci -m "write some comments here"


z
rm file_name
cvs rm file_name

cvs ci -m "write some comments here"


2
cvs rm -f file_name
cvs ci -m "why delete file"
cvs commit=>ci; update=>up;
checkout=>co/get; remove=>rm;
z
cvs add dir_name
z
cvs log file_name
cvs history file_name
z
cvs diff -r1.3 -r1.5 file_name

cvs diff file_name


z

cvs update -p -r1.2 file_name >file_name


1.2
z /
cvs cvs move cvs rename cvs
remove old_file_name cvs add new_file_name
z
cvs export
z tag
cvs tag prj_rc1

2.4.4 Subversion
1Subversion
Subversion /Subversion

Subversion

Subversion

Subversion Subversion
CVS
z

CVS Subversion
Subversion
z

CVS
-- CVS
Subversion

--
/
z

Subversion
Subversion Apache

Subversion
SSH
z

Subversion

Subversion Subversion

1(repository)
Subversion (repository)

2.3

2.3 /
2(revision)

Subversion

revision

0
0

2.4

2.4

2TortoiseSVN
TortoiseSVN Subversion Windows
Windows
TortoiseSVNl
2.5
http://tortoisesvn.tigris.org/

2.5 Subversion

TortoiseSVN TortoiseSVN
update
commit 2.6
2.7

2.6 TortoiseSVN

2.7

1 Tortoise
1

myrepo TortoiseSVNCreate repository here


Native filesystem(FSFS) OK
Windows

prj TortoiseSVNImport
Import message OK
TortoiseSVN

SVN Checkout
4

3Google
TortoiseSVN
Google

Google
http://code.google.com/hosting/
Google Google
http://code.google.com/hosting/ Create a new project

AdministerProject Members Google


SVN Source svn
checkout https http
Subversion Windows
Source svn checkout Windows
TortoiseSVN svn
Checkout https http https
Source googlecode.com password
Google
Google

FPGA
3.1 FPGA
3.1.1 PLD
FPGA Field Programmable Gate Array
CPLDComplex Programmable Logic Device PLDProgrammable Logic
Device
PROMEPROM EEPROM
PLD
/PLD
PLD
1PALProgrammable Array Logic
EPROM EEPROM
2PLAProgrammable Logic Array

PAL GALGeneric Array Logic


EEPROM PAL
(OLMC)
GAL PAL
GAL
20 GAL

(ASIC)
ASIC
ASIC
(FPLD)(CPLD)
(FPGA)

ASICPLD ASIC
PLD
DSP SRAM FPGA
FFTPLD
FPGA FPGA

PLD

3.1.2 FPGA
FPGA PALGALEPLD
ASIC

FPGA Look-Up-Table LUTLUT


RAM FPGA 4 LUT LUT
4 161 RAM HDL
FPGA Xilinx ISE EDK
Xilinx
RAM

3.1.1 4 LUT
LUT LUT
FPGA

abcd

RAM

0000

0001

1111

3.1.1 LUT

FPGA LCALogic Cell Array


CLBConfigurable Logic Block IOB
Input Output BlockInterconnect 3.1.2 FPGA

3.1.2 FPGA

CLB FPGA FPGA


CLB 4 Silce 3.1.3
Xilinx Virtex-II FPGA CLB Slice LUT

D 3.1.3 Slice
Slice 3.1.4

3.1.3 CLB

3.1.4 slice

LUT SRAM FPGA SRAM


SRAM
EPROM FPGA EPROM
RAM FPGA FPGA
FPGA FPGA
FPGA EPROMPROM
FPGA Flash
FPGA FPGA
FPGA
FPGA
FPGA

FPGA FPGA Xilinx Virtex


II Pro MicroBlaze PowerPC
Soc
Xilinx Virtex-II Pro

3.1.5 Virtex-II Pro

3.1.6 FPGA

3.2 MicroBlaze
MicroBlaze Xilinx 32 RISC
Reduced Instruction Set Computer Xilinx FPGA
IBM CoreConnect PPC405 FPGA
MicroBlaze FPGA
Spartan3(-E) FPGA
400 slice 10 FPGA
10 3.2.1
MicroBlaze FPGA

3.2.1 MicroBlaze FPGA

3.2.1 MicroBlaze
Micro Blaze

1 32 32
2 32 3
3 32
4

3.2.1 Micro Blaze

Micro Blaze

v2.10

v3.00

v4.00

v5.00

v6.00

3/5

OPBOn-chip

Peripheral Bus
OPBOn-chip

FSLFast Simplex

0-7

0-7

0-7

0-7

0-7

IOPB

FPUFloating

ESR

Peripheral Bus
LMBLocal Memory
Bus
LMBLocal Memory
Bus

Link

Cache
DOPB
Cache
IXCL
Cache
DXCL
Cache
XCL 4 8
Cache

Point Unit

EAR
-

64

LUT Cache

PVRProcessor Version
Register

3.2.2 MicroBlaze
Micro Blaze RISC 32
IBM OPB
IP 3.2.2 MicroBlaze
3.2.3 MicroBlaze

3.2.2 MicroBlaze

3.2.3 MicroBlaze

3.2.3 Micro Blaze


Micro Blaze 3.2.2

3.2.2 Micro Blaze


MSByte LSByte MSBit LSBit

n+1

n+2

n+3

n+1

MSByte

LSByte

31

MSBit

LSBit

MSByte

LSByte

0
MSBit

15
LSBit

0
MSBit

7
LSBit

Micro Blaze 32 A 2
1 B 1 1 16
1 IMM 32
MicroBlaze
3.2.3 3.2.4
Micro Blaze
3.2.3 Micro Blaze
Symbol
Ra

Description
R0- R31, General Purpose Register, source operand a

Rb

R0 - R31, General Purpose Register, source operand b

Rd

R0 - R31, General Purpose Register, destination operand

SPR[x]

Special Purpose Register number x

MSR

Machine Status Register = SPR[1]

ESR

Exception Status Register = SPR[5]

EAR

Exception Address Register = SPR[3]

FSR

Floating Point Unit Status Register = SPR[7]

PVRx

Processor Version Register, where x is the register number = SPR[8192 + x]

BTR

Branch Target Register = SPR[11]

PC

Execute stage Program Counter = SPR[0]

x[y]

Bit y of register x

x[y:z]
x

Bit range y to z of register x


Bit inverted value of register x

Imm

16 bit immediate value

Immx

x bit immediate value

FSLx

3 bit Fast Simplex Link (FSL) port designator where x is the port number

Carry flag, MSR[29]

Sa

Special Purpose Register, source operand

Sd

Special Purpose Register, destination operand

s(x)

Sign extend argument x to 32-bit value

*Addr

Memory contents at location Addr (data-size aligned)

:=

Assignment operator

Equality comparison

!=

Inequality comparison

>

Greater than comparison

>=

Greater than or equal comparison

<

Less than comparison

<=

Less than or equal comparison

Arithmetic add

Arithmetic multiply

Arithmetic divide

>>x

Bit shift right x bits

<<x

Bit shift left x bits

and

Logic AND

or

Logic OR

xor

Logic exclusive OR

op1 if

Perform op1 if condition cond is true, else perform op2

cond else
op2
&

Concatenate. E.g. 0000100 & Imm7 is the concatenation of the fixed field 0000100 and a
7 bit immediate value.

signed

Operation performed on signed integer data type. All arithmetic operations are performed
on signed word operands, unless otherwise specified ediate value.

Unsigne

Operation performed on unsigned integer data type

d
float

Operation performed on floating point data type

3.2.4 Micro Blaze

3.2.4 MicroBlaze
Micro Blaze 32 32 18 32

1
32 6
R0 0
R1-R13 R18-R31
R14
R15Xilinx

R16Break
R17
BTRBranch Target

Register

2
7 PCProgram Counter
MSRMachine Status Register EARException Address
Register ESRException Status Register
BTR
Branch Target Register FSR
Floating Point Status Register
PVRProcessor Version Register
PC MFS MTS

MSR PVR
Cache 0
MFS MTSMSRSET
MSRCLR
EAR

0 MFS
BTR
MFS
FSR 0
MFS MTS

PVR C_PVR
MFS

3.2.5 MicroBlaze
MicroBlaze 3 MicroBlaze
3 5

MicroBlaze

2 1
3
D BNE
BNED
3.2.4 3.2.5 3 5

3.2.4 Fetch
DecodeExecute

3.2.5
IFOFEXMEMWB

3.2.6 MicroBlaze
MicroBlaze
32 4GB

MicroBlaze I/O

OPBLMB XCL LMB OPB XCL

3.2.7 MicroBlaze
MicroBlaze

1
2
3
4
5
6
3.2.5 (
)
3.2.5 MicroBlaze

0x00000

000-0x00000

0x00000

MSR<C_RESET_MSR
EAR< 0
ESR< 0

004

PC<0x00000000

FSR<0

Rx

rx<PC

R14

r14<PC

008-0x00000

PC<0x00000008

00C

0x00000
010-0x00000

PC<0x00000010
MSR[IE]<0

014
r16<PC

0x00000

018-0x00000

R16

PC< 0x00000018
MSR[BIP] <1

01C

0x00000

ESR[DS] <exception in delay

R17 or BTR

slot

020-0x00000

if ESR[DS] then
BTR< branch target PC

024

r17<invalid value
else
r17<PC + 4
PC<0x00000020
MSR[EE]<0
MSR[EIP] <1
ESR[EC] <exception specific
value
ESR[ESS] <exception specific
value
EAR<exception specific value
FSR<exception specific value

Xilinx

0x00000028-

0x0000004F

3.2.8 MicroBlaze FPUFloating Point Unit


MicroBlaze IEEE 754 FPU

3.2.9 MicroBlaze Cache


MicroBlaze Cache LMB

11
2 Cache
3 Cache tag
4 XCL Cache

5 4 8 Cache-line
6 MSR Cache
7 WIC/WDC Cache-line
8 Cache
3.2.6 3.2.7 Cache Cache

3.2.6 Cache

3.2.7 Cache

C_ICACHE_BASEADDR=
0x00300000,
C_ICACHE_HIGHADDR=0x0030ffff,

C_CACHE_BYTE_SIZE=4096,

_ICACHE_LINELEN=8
Cache 64KB 16 4KB 12
tag 16-12=4 2
RAM16 1024 1 RAM16 128 4 tag8
1 Cache-line 3 RAM16

3.3 MicroBlaze
MicroBlaze

OPBOn-chip Peripheral Bus32 v2.0


LMBLocal Memory Bus BRAM
FSLFast Simplex Link
XCLXilinx Cache Link Cache

MDM

3.3.1 OPB
OPB DDataOPB IInstructionOPB
OPB
IBM 64 OPB v2.0

3.3.2 LMB
LMB BRAMBlock RAM
LMB D
DataLMB IInstructionLMB BRAM
LMB 3.3.1-
3.3.4

3.3.1 LMB

3.3.2 LMB

3.3.3 LMB

3.3.4 LMB
LMB

3.3.3 XCL
XCL
FSL DData
XCL IInstructionXCL Cache
Cache OPB LMB
Cache OPB 3.3.5

3.3.5 XCL FSL

3.3.4 FSL
FSL FIFO FIFO M
MasterFSL SSlaveFSL 8 3.3.6

3.3.6 FSL Fx
FSL put get
FIFO FIFO

FIFO FIFO
MSR

FIFO FIFO
FIFO FIFO
MSR

3.3.5
JTAG XMD FPGA
MDM
Cache
Xilinx
IP

3.4 Xilinx
3.4.1 Xilinx
Xilinx Embedded Development Kit (EDK)
Xilinx
Xilinx Platform Studio(XPS) IBM
PowerPC Xilinx MicroBlaze Xilinx
FPGA IP
Xilinx FPGA , Virtex-4Virtex-II Pro
Spartan-3 ,EDK
/

. EDK

Xilinx
Virtex Spartan FPGA, Xilinx

EDK Xilinx ISE

3.4.2 EDK
1 Embedded Development Kit (EDK)

Xilinx Platform Studio (XPS)


Software Development Kit (SDK)
Xilinx Microprocessor Debug (XMD)
Interface to industry standard simulation tools
ChipScope Pro
Bus Functional Model (BFM) simulation
support
GNU ()
MicroBlazePowerPCInstruction Set Simulator (ISS)
for MicroBlaze and PowerPC
FlashFlash programmer
MicroBlaze
IP

2 XPS
XPS


Base System Builder (BSB)
IP
ChipScope Pro

Xilinx MicroKernelWind River VxWorks MontaVista


Linux Board Support Package (BSP)

3.4.1

Xilinx Platform Studio (XPS)

3SDK

SDK XPS IDE

Eclipse

C/C++
Makefile

CVS

3.4.2 Software Development Kit (SDK) IDE


4 ChipScope Pro Support

ChipScope Pro analyzer


GNU
ChipScope ProEDK
OPB and PLB IBA (Integrated Bus Analyzer)
VIO (Virtual I/O)
ICON (Integrated Controller)
ILA (Integrated Logic Analyzer)

3.4.3 Xilinx
1 BSB

BSB

3.4.3 BSB

Base System Builder (BSB):


-(MicroBlaze PowerPC);
-;
-
-
- GPIOUART
-
Xilinx Xilinx Board Description (XBD) file
FPGA
BSB Xilinx Xilinx Board
Description File.xbd
FPGA

2
XPS [ProjectPreoject Option...] Device and
Repository BSB Hierarchy
and Flow XPS
sub-module design ISE Project Navigator

3
XPS [Hardware|Generate Bitstream]


Generae Bitstream XPS $EDK/data/xflow
bitgen.ut etc etc fast_runtime.opt
BSB XPS

/implementation system.par

4
XPS [Software|Software Platform Settings] OS
& Library Settings XPS Standalone
, Xilinx MicroKernel, Monta Vista Linux vxWorks
Microprocessor Library Definition(MLD)
lwip

5
XPS [Software|Add Software Appliction Project]

$EDK/SDK_Projects EDK
EDK PowerPC/MicroBlaze GNU
Applications Project
Set Compiler Options
EDK Eclipse SDK
VC debug

6 FPGA,
XPS [Device Configuration|Downloads Bitstream]

7 IP ()
XPS [Project Information Area|IP Catalog] IP
XPS IP

Microbalze
xilinx Spartan-3E Starter Kit

4.1

Xilinx Platform Studio (XPS)


Spartan-3E Starter Kit

Base System Builder (BSB) XPS


Embedded Development Kit Xilinx IPs

4.1.1

OPB
Bus

MDM

UART

INTC
MicroBlaze
LMB
BRAM
Cntlr

Timer

LMB
BRAM
Cntlr

GPIO

PSB

GPIO

LEDs

MY IP

LCD

BRAM

ICON

IBA

4.1.1.

XPS BSB
IP 4.1.2

microblaze

opb_mdm

OPB

BRAM LMB BRAM

BRAM

UART

LEDs GPIO

OPB
Bus

MDM

UART
INTC

MicroBlaze
LMB
BRAM
Cntlr

Timer

LMB
BRAM
Cntlr

GPIO

PSB

GPIO

LEDs

MY IP

LCD

BRAM

ICON

IBA

4.1.2. IP

3 Base System Builder


IP

Base System Builder

1
BSB

IP

Xilinx Platform Studio (XPS) Base System Builder


Spartan-3E starter kit MicroBlaze
50 MHz H/W
n Xilinx Platform Studio 8.2i Xilinx Platform Studio
4.1.3 XPS

4.1.3. Xilinx Platform Studio

Xilinx Platform Studio SDK Software Development Kit


IDE.
o OK cancel File New
Project Base System Builder OK
4.1.4

4.1.4. New Base System Builder-Based Project Creation

BSB XPS 4.1.5

4.1.5. BSB XPS

c:\xup\embedded\labs
lab1
Open Save 4.1.6

4.1.6.
q

OK Welcome to Base System Builder I would like to create

a new design
v

Next Select Board 4.1.7


{

Board Vendor: Xilinx

Board Name: Spartan-3E Starter Board

Board Revision (Verify on board): C

4.1.7. Select Board


s

Next Select Processor 4.1.8

4.1.8. Select Processor


t Next Configure Processor 4.1.9
{

Reference Clock Frequency: 50 MHz

FPGA DCMs

Processor bus Clock Frequency: 50 MHz

Debug Interface: On-Chip H/W debug module

Local Data and Instruction Memory 8 KB

Cache Setup: No Cache - checked

4.1.9. Configure Processor

LEDs_8Bit OPB_GPIORS232_DCE 115200



n

Next Configure IO Interfaces 4.1.10


RS232_DCE LEDs_8Bit

RS232_DCE115200

LEDs4_BitOPB GPIO

4.1.10. Configure IO Interfaces


o Next Configure Additional IO Interfaces 4.1.11

4.1.11. Configure Additional IO Interfaces

Next Add Internal Peripherals


4.1.12 Add Peripheral

4.1.12. Add Internal Peripherals

Next Software Setup Memory Test

Peripheral SelfTest 4.1.13

4.1.13. Software Setup


s Next Configure Memory Test Application 4.1.14

4.1.14. Configure Memory Test Application


s

Next System Created 4.1.15

4.1.15. System Created


t

Generate
BSB

u Finish Start Using Platform


Studio OK
v 4.1.16

4.1.16. System Created

1
BSB

IP

Project Generate and View Block Diagram


System

n Project Generate and View Block Diagram 4.1.17

4.1.17.
MicroBlaze
lmb MicroBlaze opb
o I/O
p

4.1.18

4.1.18.

1.
debug_module:
dlmb_cntlr:
RS232_DCE:

Ports filter 4.1.19

4.1.19. Ports Filter

2.
RS232_DCE OPB_CLK:
RS232_DCE RX:
RS232_DCE TX:
LEDs_8Bit - GPIO:

3. Addresses filter
RS232_Uart Base address:
RS232_Uart High address:
LEDs_4Bit Base address:
LEDs_4Bit High address:
dlmb_cntlr Base address:
dlmb_cntlr High address:
ilmb_cntlr Base address:
ilmb_cntlr High address:

1
BSB

IP

PlatGen
n XPS Hardware Generate Netlist

o
p

Windows Explorer Windows Explorer

Lab1
VHDL

4.

Bitstream

1
BSB

IP

bitstream

n Spartan-3E starter kit


o

4.1.20.

p XPS Device Configuration J Download Bitstream

4.1.21.


XPS Base System Builder MHS


1.

debug_module:

2.

3.

4.

mb_opb

dlmb_cntrl:

dlmb

RS232_Uart:

mb_opb

RS232_Uart OPB_CLK:

sys_clk_s

RS232_Uart RX:

fpga_0_RS232_DCE_RX

RS232_Uart TX:

fpga_0_RS232_DCE_TX

LEDs_4Bit - GPIO:

fpga_0_LEDs_8Bit_GPIO_d_out

Addresses filter
RS232_DCE Base address:

0x40600000

RS232_DCE High address:

0x4060ffff

LEDs_8Bit Base address:

0x40000000

LEDs_8Bit High address:

0x4000ffff

dlmb_cntlr Base address:

0x00000000

dlmb_cntlr High address:

0x00001fff

ilmb_cntlr Base address:

0x00000000

ilmb_cntlr High address:

0x00001fff

__xps

blkdiagram

data

etc

hdl

implementation

pcores

microblaze_0

synthesis

TestApp_Memory

MHS
#
#
##############################################################################
#
# Created by Base System Builder Wizard for Xilinx EDK 8.2 Build EDK_Im.14
#
# Fri Sep 01 11:41:45 2006
#
# Target Board: Xilinx Spartan-3E Starter Board Rev C
# Family: spartan3e
# Device: XC3S500e
# Package:
FG320
# Speed Grade:
-4
#
# Processor: Microblaze
# System clock frequency: 50.000000 MHz
# Debug interface: On-Chip HW Debug Module
# On Chip Memory :
8 KB
#
#
##############################################################################

PARAMETER VERSION = 2.1.0

PORT fpga_0_RS232_DCE_RX_pin = fpga_0_RS232_DCE_RX, DIR = I


PORT fpga_0_RS232_DCE_TX_pin = fpga_0_RS232_DCE_TX, DIR = O
PORT fpga_0_LEDs_8Bit_GPIO_d_out_pin = fpga_0_LEDs_8Bit_GPIO_d_out, DIR = O, VEC
= [0:7]
PORT sys_clk_pin = dcm_clk_s, DIR = I, SIGIS = CLK, CLK_FREQ = 50000000
PORT sys_rst_pin = sys_rst_s, DIR = I, RST_POLARITY = 1, SIGIS = RST

BEGIN microblaze
PARAMETER INSTANCE = microblaze_0
PARAMETER HW_VER = 5.00.a
PARAMETER C_USE_FPU = 0
PARAMETER C_DEBUG_ENABLED = 1
PARAMETER C_NUMBER_OF_PC_BRK = 2
BUS_INTERFACE DLMB = dlmb

BUS_INTERFACE ILMB = ilmb


BUS_INTERFACE DOPB = mb_opb
BUS_INTERFACE IOPB = mb_opb
PORT DBG_CAPTURE = DBG_CAPTURE_s
PORT DBG_CLK = DBG_CLK_s
PORT DBG_REG_EN = DBG_REG_EN_s
PORT DBG_TDI = DBG_TDI_s
PORT DBG_TDO = DBG_TDO_s
PORT DBG_UPDATE = DBG_UPDATE_s
END
BEGIN opb_v20
PARAMETER INSTANCE = mb_opb
PARAMETER HW_VER = 1.10.c
PARAMETER C_EXT_RESET_HIGH = 1
PORT SYS_Rst = sys_rst_s
PORT OPB_Clk = sys_clk_s
END
BEGIN opb_mdm
PARAMETER INSTANCE = debug_module
PARAMETER HW_VER = 2.00.a
PARAMETER C_MB_DBG_PORTS = 1
PARAMETER C_USE_UART = 1
PARAMETER C_UART_WIDTH = 8
PARAMETER C_BASEADDR = 0x41400000
PARAMETER C_HIGHADDR = 0x4140ffff
BUS_INTERFACE SOPB = mb_opb
PORT DBG_CAPTURE_0 = DBG_CAPTURE_s
PORT DBG_CLK_0 = DBG_CLK_s
PORT DBG_REG_EN_0 = DBG_REG_EN_s
PORT DBG_TDI_0 = DBG_TDI_s
PORT DBG_TDO_0 = DBG_TDO_s
PORT DBG_UPDATE_0 = DBG_UPDATE_s
END
BEGIN lmb_v10
PARAMETER INSTANCE = ilmb
PARAMETER HW_VER = 1.00.a
PARAMETER C_EXT_RESET_HIGH = 1
PORT SYS_Rst = sys_rst_s
PORT LMB_Clk = sys_clk_s
END

BEGIN lmb_v10
PARAMETER INSTANCE = dlmb
PARAMETER HW_VER = 1.00.a
PARAMETER C_EXT_RESET_HIGH = 1
PORT SYS_Rst = sys_rst_s
PORT LMB_Clk = sys_clk_s
END
BEGIN lmb_bram_if_cntlr
PARAMETER INSTANCE = dlmb_cntlr
PARAMETER HW_VER = 2.00.a
PARAMETER C_BASEADDR = 0x00000000
PARAMETER C_HIGHADDR = 0x00001fff
BUS_INTERFACE SLMB = dlmb
BUS_INTERFACE BRAM_PORT = dlmb_port
END
BEGIN lmb_bram_if_cntlr
PARAMETER INSTANCE = ilmb_cntlr
PARAMETER HW_VER = 2.00.a
PARAMETER C_BASEADDR = 0x00000000
PARAMETER C_HIGHADDR = 0x00001fff
BUS_INTERFACE SLMB = ilmb
BUS_INTERFACE BRAM_PORT = ilmb_port
END
BEGIN bram_block
PARAMETER INSTANCE = lmb_bram
PARAMETER HW_VER = 1.00.a
BUS_INTERFACE PORTA = ilmb_port
BUS_INTERFACE PORTB = dlmb_port
END
BEGIN opb_uartlite
PARAMETER INSTANCE = RS232_DCE
PARAMETER HW_VER = 1.00.b
PARAMETER C_BAUDRATE = 115200
PARAMETER C_DATA_BITS = 8
PARAMETER C_ODD_PARITY = 0
PARAMETER C_USE_PARITY = 0
PARAMETER C_CLK_FREQ = 50000000
PARAMETER C_BASEADDR = 0x40600000
PARAMETER C_HIGHADDR = 0x4060ffff
BUS_INTERFACE SOPB = mb_opb

PORT RX = fpga_0_RS232_DCE_RX
PORT TX = fpga_0_RS232_DCE_TX
END
BEGIN opb_gpio
PARAMETER INSTANCE = LEDs_8Bit
PARAMETER HW_VER = 3.01.b
PARAMETER C_GPIO_WIDTH = 8
PARAMETER C_IS_DUAL = 0
PARAMETER C_IS_BIDIR = 0
PARAMETER C_ALL_INPUTS = 0
PARAMETER C_BASEADDR = 0x40000000
PARAMETER C_HIGHADDR = 0x4000ffff
BUS_INTERFACE SOPB = mb_opb
PORT GPIO_d_out = fpga_0_LEDs_8Bit_GPIO_d_out
END
BEGIN dcm_module
PARAMETER INSTANCE = dcm_0
PARAMETER HW_VER = 1.00.a
PARAMETER C_CLK0_BUF = TRUE
PARAMETER C_CLKIN_PERIOD = 20.000000
PARAMETER C_CLK_FEEDBACK = 1X
PARAMETER C_EXT_RESET_HIGH = 1
PORT CLKIN = dcm_clk_s
PORT CLK0 = sys_clk_s
PORT CLKFB = sys_clk_s
PORT RST = net_gnd
PORT LOCKED = dcm_0_lock
END

4.2 IP

Xilinx Platform Studio (XPS)


IP IP IP ISE

IP
ISE

1 1 MicroBlaze LMB
LMB GPIO MDM 2 GPIO
XPS IP
4.2.1
Spartan-3E DIP OPB GPIP
system.mhs

OPB
Bus

MDM

UART
INTC

MicroBlaze
LMB
BRAM
Cntlr

Timer

LMB
BRAM
Cntlr
BRAM

ICON

GPIO

PSB

GPIO

DIP

GPIO

LEDs

MY IP

LCD

IBA

4.2.1.

5 IP 1
MHS

IP

Step 1:

IP

Step 2:

Step 3:

Step 4:

MHS

Step 5:

2
1 Xilinx Platform Studio (XPS)
c:\xup\embedded\labs\lab2(
) c:\xup\embedded\completed\lab1.
n 2
1
o Xilinx Platform Studio 8.2i Xilinx Platform Studio
XPS

c:xupembeddedlabslab2
c:xupembeddedcompletedlab1

system.xmp

:
Step 1:

IP

Step 2:

Step 3:

Step 4:

MHS

Step 5:

System Assembly View IP


o OPB GPIO
XPS
System Assembly View IP
MHS
n

IP Catalog General Purpose IO

IP 4.2.2

4.2.2. System Assembly View


o

opb_gpio (version 3.01.b)2 2 System Assembly View

dip push
4.2.3

4.2.3.

Bus Interface push dip Bus Connection

mb_opb SOPB
Bus Connections 4.2.4

4.2.4.
v

Addresses XPS

Generate Addresses

push dip size 512

4.2.5

4.2.5.

Ports Push_Buttons_4Bit
Push_Buttons_4Bit
n System Assembly View Ports Push_Buttons_4Bit
4.2.6
o push GPIO_in Net push_GPIO_in
4.2.6

4.2.6. push GPIO_in

dip GPIO_in Net


dip_GPIO_in 4.2.7).

4.2.7. dip GPIO_in


q push
Enable
Channel 2
v

GPIO Data Bus Width 4 OK


8

4.2.8. GPIO
s

Channel 1 1 ( 4.2.9)

t Channel 1 is Bi-directional FALSE, Channel 1 is input Only TRUE


4.2.9, OK

4.2.9.
u dip
v System Assembly view External Ports

4.2.10.
w Net push dip GPIO_in
Make External 4.2.11

4.2.11.
FPGA [0:3]

4.2.12.

c
ISE
n

Software Generate Libraries and BSPs Applications

xparameters.h
o Applications Sources TestApp_Memory.c Remove
p

Sources c:xupembeddedsource lab.c

4.2.13.
q

Project system.ucf

(c:xupembeddedconstraints directory lab2.ucf


)

4.2.14. UCF ().


v

Application No Optimization

for loop ().

4.2.15.

.ucf ,

MHS

:
Step 1:

IP

Step 2:

Step 3:

Step 4:

MHS

Step 5:

system.mhs
n system.mhs

5. :
:
:
:
:

MHS
?

6. sys_clk_s :
_____________________________________________________________
___
_____________________________________________________________
___
mb_opb :
_____________________________________________________________
___
_____________________________________________________________
___

7.

$0000 0000

$FFFF FFFF

:
Step 1:

IP

Step 2:

Step 3:

Step 4:

MHS

Step 5:

Spartan-3E xc3s500e
n c:xup embeddedhyperterm ht115200.ht
o Spartan-3E .
p Device Configuration J Update Bitstream

q
DONE LED ON
4.2.16

4.2.16.
r 4.2.17)

4.2.17.

Xilinx Platform Studio (XPS) MHS

XUP Spartan-3E

A
1.

:
:

7
2

:
:
2.

sys_clk_s :
microblaze_0, mb_opb, debug_module, ilmb, dlmb, dcm_0, LEDs_8Bit, push, dip and
RS232_DCE
mb_opb :
microblaze_0, debug_module, LEDs_8Bit, push, dip and RS232_DCE

3.

. Addresses

0x000000000x00001fff

dlmb, llmb

unused

0x40000000
0x400001ff

push

0x40020000
0x400201ff

dip

0x40040000 0x4004ffff

LEDs_8Bit

0x40600000 0x4060ffff

RS232_DCE

0x41400000 0x4140ffff

debug-module

MHS
#
###########################################################################
###
# Created by Base System Builder Wizard for Xilinx EDK 8.2 Build EDK_Im.14
# Fri Sep 01 11:41:45 2006
# Target Board: Xilinx Spartan-3E Starter Board Rev C
# Family: spartan3e
# Device: XC3S500e
# Package:
FG320
# Speed Grade: -4
# Processor: Microblaze
# System clock frequency: 50.000000 MHz
# Debug interface: On-Chip HW Debug Module
# On Chip Memory :
8 KB
#
###########################################################################
###

PARAMETER VERSION = 2.1.0

PORT fpga_0_RS232_DCE_RX_pin = fpga_0_RS232_DCE_RX, DIR = I


PORT fpga_0_RS232_DCE_TX_pin = fpga_0_RS232_DCE_TX, DIR = O
PORT fpga_0_LEDs_8Bit_GPIO_d_out_pin = fpga_0_LEDs_8Bit_GPIO_d_out, DIR = O,
VEC = [0:7]
PORT sys_clk_pin = dcm_clk_s, DIR = I, SIGIS = CLK, CLK_FREQ = 50000000
PORT sys_rst_pin = sys_rst_s, DIR = I, RST_POLARITY = 1, SIGIS = RST
PORT push_GPIO_in_pin = push_GPIO_in, DIR = I, VEC = [0:3]
PORT dip_GPIO_in_pin = dip_GPIO_in, DIR = I, VEC = [0:3]

BEGIN microblaze
PARAMETER INSTANCE = microblaze_0
PARAMETER HW_VER = 5.00.a
PARAMETER C_USE_FPU = 0
PARAMETER C_DEBUG_ENABLED = 1
PARAMETER C_NUMBER_OF_PC_BRK = 2
BUS_INTERFACE DLMB = dlmb
BUS_INTERFACE ILMB = ilmb
BUS_INTERFACE DOPB = mb_opb

BUS_INTERFACE IOPB = mb_opb


PORT DBG_CAPTURE = DBG_CAPTURE_s
PORT DBG_CLK = DBG_CLK_s
PORT DBG_REG_EN = DBG_REG_EN_s
PORT DBG_TDI = DBG_TDI_s
PORT DBG_TDO = DBG_TDO_s
PORT DBG_UPDATE = DBG_UPDATE_s
END
BEGIN opb_v20
PARAMETER INSTANCE = mb_opb
PARAMETER HW_VER = 1.10.c
PARAMETER C_EXT_RESET_HIGH = 1
PORT SYS_Rst = sys_rst_s
PORT OPB_Clk = sys_clk_s
END
BEGIN opb_mdm
PARAMETER INSTANCE = debug_module
PARAMETER HW_VER = 2.00.a
PARAMETER C_MB_DBG_PORTS = 1
PARAMETER C_USE_UART = 1
PARAMETER C_UART_WIDTH = 8
PARAMETER C_BASEADDR = 0x41400000
PARAMETER C_HIGHADDR = 0x4140ffff
BUS_INTERFACE SOPB = mb_opb
PORT DBG_CAPTURE_0 = DBG_CAPTURE_s
PORT DBG_CLK_0 = DBG_CLK_s
PORT DBG_REG_EN_0 = DBG_REG_EN_s
PORT DBG_TDI_0 = DBG_TDI_s
PORT DBG_TDO_0 = DBG_TDO_s
PORT DBG_UPDATE_0 = DBG_UPDATE_s
END
BEGIN lmb_v10
PARAMETER INSTANCE = ilmb
PARAMETER HW_VER = 1.00.a
PARAMETER C_EXT_RESET_HIGH = 1
PORT SYS_Rst = sys_rst_s
PORT LMB_Clk = sys_clk_s
END
BEGIN lmb_v10
PARAMETER INSTANCE = dlmb

PARAMETER HW_VER = 1.00.a


PARAMETER C_EXT_RESET_HIGH = 1
PORT SYS_Rst = sys_rst_s
PORT LMB_Clk = sys_clk_s
END
BEGIN lmb_bram_if_cntlr
PARAMETER INSTANCE = dlmb_cntlr
PARAMETER HW_VER = 2.00.a
PARAMETER C_BASEADDR = 0x00000000
PARAMETER C_HIGHADDR = 0x00001fff
BUS_INTERFACE SLMB = dlmb
BUS_INTERFACE BRAM_PORT = dlmb_port
END
BEGIN lmb_bram_if_cntlr
PARAMETER INSTANCE = ilmb_cntlr
PARAMETER HW_VER = 2.00.a
PARAMETER C_BASEADDR = 0x00000000
PARAMETER C_HIGHADDR = 0x00001fff
BUS_INTERFACE SLMB = ilmb
BUS_INTERFACE BRAM_PORT = ilmb_port
END
BEGIN bram_block
PARAMETER INSTANCE = lmb_bram
PARAMETER HW_VER = 1.00.a
BUS_INTERFACE PORTA = ilmb_port
BUS_INTERFACE PORTB = dlmb_port
END
BEGIN opb_uartlite
PARAMETER INSTANCE = RS232_DCE
PARAMETER HW_VER = 1.00.b
PARAMETER C_BAUDRATE = 115200
PARAMETER C_DATA_BITS = 8
PARAMETER C_ODD_PARITY = 0
PARAMETER C_USE_PARITY = 0
PARAMETER C_CLK_FREQ = 50000000
PARAMETER C_BASEADDR = 0x40600000
PARAMETER C_HIGHADDR = 0x4060ffff
BUS_INTERFACE SOPB = mb_opb
PORT RX = fpga_0_RS232_DCE_RX
PORT TX = fpga_0_RS232_DCE_TX

END
BEGIN opb_gpio
PARAMETER INSTANCE = LEDs_8Bit
PARAMETER HW_VER = 3.01.b
PARAMETER C_GPIO_WIDTH = 8
PARAMETER C_IS_DUAL = 0
PARAMETER C_IS_BIDIR = 0
PARAMETER C_ALL_INPUTS = 0
PARAMETER C_BASEADDR = 0x40040000
PARAMETER C_HIGHADDR = 0x4004ffff
BUS_INTERFACE SOPB = mb_opb
PORT GPIO_d_out = fpga_0_LEDs_8Bit_GPIO_d_out
END
BEGIN dcm_module
PARAMETER INSTANCE = dcm_0
PARAMETER HW_VER = 1.00.a
PARAMETER C_CLK0_BUF = TRUE
PARAMETER C_CLKIN_PERIOD = 20.000000
PARAMETER C_CLK_FEEDBACK = 1X
PARAMETER C_EXT_RESET_HIGH = 1
PORT CLKIN = dcm_clk_s
PORT CLK0 = sys_clk_s
PORT CLKFB = sys_clk_s
PORT RST = net_gnd
PORT LOCKED = dcm_0_lock
END
BEGIN opb_gpio
PARAMETER INSTANCE = push
PARAMETER HW_VER = 3.01.b
PARAMETER C_IS_BIDIR = 0
PARAMETER C_ALL_INPUTS = 1
PARAMETER C_GPIO_WIDTH = 4
PARAMETER C_BASEADDR = 0x40000000
PARAMETER C_HIGHADDR = 0x400001FF
BUS_INTERFACE SOPB = mb_opb
PORT GPIO_in = push_GPIO_in
END
BEGIN opb_gpio
PARAMETER INSTANCE = dip
PARAMETER HW_VER = 3.01.b

PARAMETER C_GPIO_WIDTH = 4
PARAMETER C_IS_BIDIR = 0
PARAMETER C_ALL_INPUTS = 1
PARAMETER C_BASEADDR = 0x40020000
PARAMETER C_HIGHADDR = 0x400201FF
BUS_INTERFACE SOPB = mb_opb
PORT GPIO_in = dip_GPIO_in
END

4.3 IP

Create and Import Peripheral Wizard


OPB

IP IP catalog

UCF

bitstream

Lab 1 Lab 2 Lab 1 MicroBlaze UART


, LED OPB GPIO ,LMB BRAM BRAM Lab 2
GPIO instance
instance

Xilinx Platform Studio (XPS) Create and Import Peripheral


Wizard
instance system.ucf LCD 4.3.1

OPB
Bus

MDM

UART
INTC

MicroBlaze

Timer
LMB
BRAM
Cntl

LMB
BRAM
Cntl
BRAM

ICON

IBA

GPIO

PSB

GPIO

DIP

GPIO

LEDs

MY IP

LCD

4.3.1

OPB
Create and Import Peripheral Wizard
OPB

:
Step 1:

Step 2:

OPB

Step 3:

Step 4:

lab3 lab2 lab3


XPS
n

2 c:\xup\embedded\labs lab3 ,

lab2 lab3
o XPS

OPB

:
Step 1:

Step 2:

OPB

Step 3:

Step 4:

XPS Create/Import Peripheral Wizard create HDL


OPB LCD
XPS Hardware Create or Import Peripheral wizard

o Next Create and Import Peripheral Wizard


-2

4.3.2

Select Flow Create templates for a new peripheral

Next
To an XPS project

4.3.3. Repository or Project


q Next lcd_ip 1.00.a Next 4.3.4

4.3.4.
t

On-chip Peripheral Bus (OPB) Next

4.3.5. OPB

User Logic S/W Register support 32

C:\up\embedded\labs\lab3
n

IPIF Services User Logic S/W Register Support Next

4.3.6. IPIF Services

o User S/W Register Disable posted write Next

4.3.7. User SW Registers

p IP Interconnect (IPIC) IPIC

4.3.8. IP Interconnect (IPIC)

q (OPTIONAL) Peripheral Simulation Support Generate BFM


simulation platform Next

4.3.9. Peripheral Simulation Support


r (OPTIONAL) Peripheral Implementation Options Generate
template driver files to help you to implement software interface

4.3.10. Peripheral Implementation Options

s Next

4.3.11. Congratulations Dialog Box


t Finish
u XPS IP Catalog
lcd_ip IP Project
Repository

4.3.12. IP Catalog

Windows
Create and Import Peripheral Wizard 4.3.13

lab3

pcores
lcd v1 00 a

data old

data
MPD

hdl
PAO

devl

vhdl
ipwiz.log
ipwiz.opt
R d t t

4.3.13. Create and Import Peripheral Wizard

MPD lcd LCD


n \pcores\ lcd_ip_v1_00_a\data
o lcd_ip_v2_1_0.mpd
p

Ports OPB_Clk
PORT lcd = , DIR = O, VEC = [0:6]

4.3.14. LCD MPD file

C:\xup\embedded\labs\lab3\pcores\lcd_ip_v1_00_a\hdl\vhdl
lcd_ip.vhd user_logic.vhd
n \pcores\lcd_ip_v1_00_a\hdl\vhdl
o lcd_ip.vhd
p

USER ports added here 7 lcd 4.3.15

4.3.15. LED
q

USER 4.3.16

4.3.16.
v

vhdl user_logic.vhd USER Ports lcd

4.3.17. lcd Port


s

USER

4.3.18. User Logic


t

USER logic implementation

4.3.19.
u user_logic.vhd

:
Step 1:

Step 2:

OPB

Step 3:

Step 4:

System Assembly View lcd_ip instance


opb lcd

IP Catalog lcd_ip System Assembly View

o System Assembly View filters Bus Interface


4.3.20
,

4.3.20.

filters Ports lcd_ip_0 lcd


lcd_ip_0_lcd 4.3.21

4.3.21. lcd_0
q

Make External

filters Addresses

Lock lcd_ip_0s Generate Addresses

lcd size 32K


4.3.22

4.3.22.

system.ucf lcd lab2.c


C:\xup\embedded \labsolutions lab3.c file
bitstream XPS

system.ucf UCF data\system.ucf

o C:\xup\embedded\labsolutions\lab3.ucf ucf

4.3.23. UCF
p

XPS Project Information Area Applications sources

lab2.c
r sources C:\xup\embedded\sources lab3.c
s lab3.c
t Hardware Generate Bitstream
u Software Build All User Applications
v Device Configuration Update Bitstream bistream

:
Step 1:

Step 2:

OPB

Step 3:

Step 4:

EDK Spartan-3E xc3s500e-4fg320


n

USB RS-232 XUP Spartan-3E

o C:\xup\ embedded\labsolutions ht115200.ht


p EDK Device Configuration Download Bitstream
FPGA
bitstream LED
4.3.24

4.3.24. BitStream
LCD Test Over XUP Spartan-3E board LCD
Welcome to the #1 Prof Workshop
q Disconnect
r

Create and Import Peripheral Wizard


(MPD,
PAO)
bitstream

MHS
#
##############################################################################
# Created by Base System Builder Wizard for Xilinx EDK 8.2 Build EDK_Im.14
# Fri Sep 01 11:41:45 2006
# Target Board: Xilinx Spartan-3E Starter Board Rev C
# Family: spartan3e
# Device: XC3S500e
# Package:
FG320
# Speed Grade:
-4
# Processor: Microblaze
# System clock frequency: 50.000000 MHz
# Debug interface: On-Chip HW Debug Module
# On Chip Memory :
8 KB
#
##############################################################################

PARAMETER VERSION = 2.1.0

PORT fpga_0_RS232_DCE_RX_pin = fpga_0_RS232_DCE_RX, DIR = I


PORT fpga_0_RS232_DCE_TX_pin = fpga_0_RS232_DCE_TX, DIR = O
PORT fpga_0_LEDs_8Bit_GPIO_d_out_pin = fpga_0_LEDs_8Bit_GPIO_d_out, DIR = O, VEC
= [0:7]
PORT sys_clk_pin = dcm_clk_s, DIR = I, SIGIS = CLK, CLK_FREQ = 50000000
PORT sys_rst_pin = sys_rst_s, DIR = I, RST_POLARITY = 1, SIGIS = RST
PORT push_GPIO_in_pin = push_GPIO_in, DIR = I, VEC = [0:3]
PORT dip_GPIO_in_pin = dip_GPIO_in, DIR = I, VEC = [0:3]
PORT lcd_ip_0_lcd_pin = lcd_ip_0_lcd, DIR = O, VEC = [0:6]

BEGIN microblaze
PARAMETER INSTANCE = microblaze_0
PARAMETER HW_VER = 5.00.a
PARAMETER C_USE_FPU = 0
PARAMETER C_DEBUG_ENABLED = 1
PARAMETER C_NUMBER_OF_PC_BRK = 2
BUS_INTERFACE DLMB = dlmb
BUS_INTERFACE ILMB = ilmb
BUS_INTERFACE DOPB = mb_opb
BUS_INTERFACE IOPB = mb_opb

PORT DBG_CAPTURE = DBG_CAPTURE_s


PORT DBG_CLK = DBG_CLK_s
PORT DBG_REG_EN = DBG_REG_EN_s
PORT DBG_TDI = DBG_TDI_s
PORT DBG_TDO = DBG_TDO_s
PORT DBG_UPDATE = DBG_UPDATE_s
END
BEGIN opb_v20
PARAMETER INSTANCE = mb_opb
PARAMETER HW_VER = 1.10.c
PARAMETER C_EXT_RESET_HIGH = 1
PORT SYS_Rst = sys_rst_s
PORT OPB_Clk = sys_clk_s
END
BEGIN opb_mdm
PARAMETER INSTANCE = debug_module
PARAMETER HW_VER = 2.00.a
PARAMETER C_MB_DBG_PORTS = 1
PARAMETER C_USE_UART = 1
PARAMETER C_UART_WIDTH = 8
PARAMETER C_BASEADDR = 0x41400000
PARAMETER C_HIGHADDR = 0x4140ffff
BUS_INTERFACE SOPB = mb_opb
PORT DBG_CAPTURE_0 = DBG_CAPTURE_s
PORT DBG_CLK_0 = DBG_CLK_s
PORT DBG_REG_EN_0 = DBG_REG_EN_s
PORT DBG_TDI_0 = DBG_TDI_s
PORT DBG_TDO_0 = DBG_TDO_s
PORT DBG_UPDATE_0 = DBG_UPDATE_s
END
BEGIN lmb_v10
PARAMETER INSTANCE = ilmb
PARAMETER HW_VER = 1.00.a
PARAMETER C_EXT_RESET_HIGH = 1
PORT SYS_Rst = sys_rst_s
PORT LMB_Clk = sys_clk_s
END
BEGIN lmb_v10
PARAMETER INSTANCE = dlmb
PARAMETER HW_VER = 1.00.a

PARAMETER C_EXT_RESET_HIGH = 1
PORT SYS_Rst = sys_rst_s
PORT LMB_Clk = sys_clk_s
END
BEGIN lmb_bram_if_cntlr
PARAMETER INSTANCE = dlmb_cntlr
PARAMETER HW_VER = 2.00.a
PARAMETER C_BASEADDR = 0x00000000
PARAMETER C_HIGHADDR = 0x00001fff
BUS_INTERFACE SLMB = dlmb
BUS_INTERFACE BRAM_PORT = dlmb_port
END
BEGIN lmb_bram_if_cntlr
PARAMETER INSTANCE = ilmb_cntlr
PARAMETER HW_VER = 2.00.a
PARAMETER C_BASEADDR = 0x00000000
PARAMETER C_HIGHADDR = 0x00001fff
BUS_INTERFACE SLMB = ilmb
BUS_INTERFACE BRAM_PORT = ilmb_port
END
BEGIN bram_block
PARAMETER INSTANCE = lmb_bram
PARAMETER HW_VER = 1.00.a
BUS_INTERFACE PORTA = ilmb_port
BUS_INTERFACE PORTB = dlmb_port
END
BEGIN opb_uartlite
PARAMETER INSTANCE = RS232_DCE
PARAMETER HW_VER = 1.00.b
PARAMETER C_BAUDRATE = 115200
PARAMETER C_DATA_BITS = 8
PARAMETER C_ODD_PARITY = 0
PARAMETER C_USE_PARITY = 0
PARAMETER C_CLK_FREQ = 50000000
PARAMETER C_BASEADDR = 0x40600000
PARAMETER C_HIGHADDR = 0x4060ffff
BUS_INTERFACE SOPB = mb_opb
PORT RX = fpga_0_RS232_DCE_RX
PORT TX = fpga_0_RS232_DCE_TX
END

BEGIN opb_gpio
PARAMETER INSTANCE = LEDs_8Bit
PARAMETER HW_VER = 3.01.b
PARAMETER C_GPIO_WIDTH = 8
PARAMETER C_IS_DUAL = 0
PARAMETER C_IS_BIDIR = 0
PARAMETER C_ALL_INPUTS = 0
PARAMETER C_BASEADDR = 0x40040000
PARAMETER C_HIGHADDR = 0x4004ffff
BUS_INTERFACE SOPB = mb_opb
PORT GPIO_d_out = fpga_0_LEDs_8Bit_GPIO_d_out
END
BEGIN dcm_module
PARAMETER INSTANCE = dcm_0
PARAMETER HW_VER = 1.00.a
PARAMETER C_CLK0_BUF = TRUE
PARAMETER C_CLKIN_PERIOD = 20.000000
PARAMETER C_CLK_FEEDBACK = 1X
PARAMETER C_EXT_RESET_HIGH = 1
PORT CLKIN = dcm_clk_s
PORT CLK0 = sys_clk_s
PORT CLKFB = sys_clk_s
PORT RST = net_gnd
PORT LOCKED = dcm_0_lock
END
BEGIN opb_gpio
PARAMETER INSTANCE = push
PARAMETER HW_VER = 3.01.b
PARAMETER C_IS_BIDIR = 0
PARAMETER C_ALL_INPUTS = 1
PARAMETER C_GPIO_WIDTH = 4
PARAMETER C_BASEADDR = 0x40000000
PARAMETER C_HIGHADDR = 0x400001ff
BUS_INTERFACE SOPB = mb_opb
PORT GPIO_in = push_GPIO_in
END
BEGIN opb_gpio
PARAMETER INSTANCE = dip
PARAMETER HW_VER = 3.01.b
PARAMETER C_GPIO_WIDTH = 4

PARAMETER C_IS_BIDIR = 0
PARAMETER C_ALL_INPUTS = 1
PARAMETER C_BASEADDR = 0x40020000
PARAMETER C_HIGHADDR = 0x400201ff
BUS_INTERFACE SOPB = mb_opb
PORT GPIO_in = dip_GPIO_in
END
BEGIN lcd_ip
PARAMETER INSTANCE = lcd_ip_0
PARAMETER HW_VER = 1.00.a
PARAMETER C_BASEADDR = 0x7F600000
PARAMETER C_HIGHADDR = 0x7F607FFF
BUS_INTERFACE SOPB = mb_opb
PORT lcd = lcd_ip_0_lcd
END

4.4

Spantan-3E LED OPB BRAM OPB BRAM

Block RAM

IP

LMB and OPB

Spartan-3E

Spantan-3E LED

BSP

lab4 lab3
Xilinx Platform Studio (XPS) C:\xup\embedded\labs\lab4

n Lab 3 C:xupembeddedppclabs lab4


lab3 lab4
o Xilinx Platform Studio 8.2i Xilinx Platform Studio
XPS

Open Recent Project, OK


C:xupembeddedppclabslab4
p

system.xmp

IP IP

opb_bram_if_cntlr 1.00.a

bram_block 1.00.a

4.4.1. OPB memory

t addresses opb_bram 8K Generate Addresses

4.4.2. BRAM memory

BSP

Software Platform Settings


BSP
n Software Software Platform Settings

4.4.3. microblaze_0 Software Platform Settings

o Software Platform

Spartan-3E

50MHz

OS

D
Xilinx

4.4.4. PPC405 Software Platform Parameters

p OS and Libraries RS232_DCE stdin and stdout


microblaze_exceptions enable_sw_intrusive_profiling Current Value false

4.4.5. OS
q

4.4.6.

r Interrupt Handlers
s

OK

BSP.
n XPS System system.mss MSS

4.4.7. System
XPS Software Platform Settings system.mss
o MSS Software Platform Settings
system.mss

Software Generate Libraries and BSPs

BSP

system.mss LibGen BSP

lab4 microblaze_0

_____________________________________________________________
___
_____________________________________________________________
___
_____________________________________________________________
___

Step 3

BSP

3 C LED DIP
n Applications TestApp_Memory lab3.c add lab4.c
lab4.c lab3.c lab4.c LED

o System Assembly View LEDs_8Bit Driver:


gpio_v2_01_a J View API Documentation

4.4.8. API

p File List GPIO C


q xgpio.h GPIO

GPIO 1 GPIO, 2
, 3
r
XGpio_Initialize (XGpio *InstancePtr, Xuint16 DeviceId)

InstancePtr Xgpio The memory the pointer references must


be pre-allocated by the caller. Further calls to manipulate the component through
the XGpio API must be made with this pointer.

DeviceId XGpio IDPassing in a device ID associates the


generic XGpio instance to a specific device, as chosen by the caller or application
developer.

XGpio_SetDataDirection (XGpio * InstancePtr, unsigned Channel,


Xuint32 DirectionMask)

InstancePt XGpio

Channel GPIO (1 or 2)

DirectionMask bit Bits 0


1

XGpio_DiscreteWrite (XGpio *InstancePtr, unsigned channel,


Xuint32 data)
{

InstancePtr XGpio

Channel GPIO (1 or 2)

Data

s Applications TestApp_Memory microblaze_0 Generated


Header: microblaze_0/include/xparameters.h

4.4.9.
{

LibGen xparameters.h

xparameters.h #define used to identify the LEDs_8Bit


peripheral:
#define XPAR_LEDS_8BIT_DEVICE_ID

Note: LEDS_8BIT MHS


This #define can be used as the XGpio_Intialize function call.
t C

4.4.10. C

u
v

Linker Script

Step 4

objdump Cygwin shell


object dump
n Project Launch EDK shell Cygwin shell
o cd C:/xup/embedded/ppc/labs/lab4/TestApp_Memory
pwd

Xygwin shell mb-objdump h executable.elf

()

text
opb_bram

4.4.11. Object Dump - . OPB BRAM

Text LMB
objdump
n Applications TestApp_Memory Generate Linker
Script

4.4.12.

o ilmb_cntlr_dlmb_cntlr (.text )

4.4.13. LMB BRAM space .text


p TestApp_Memory/src
q Xygwin shell mb-objdump

LMB BRAM

4.4.14. Object dump - . LMB BRAM

s bitstream DIP LED


t

Xilinx Platform Studio


XPS MSS

lab4 microblaze_0

code

include

lib lbc, libm, libxil

libsrc

MHS
#
##############################################################################
# Created by Base System Builder Wizard for Xilinx EDK 8.2 Build EDK_Im.14
# Fri Sep 01 11:41:45 2006
# Target Board: Xilinx Spartan-3E Starter Board Rev C
# Family: spartan3e
# Device: XC3S500e
# Package:
FG320
# Speed Grade:
-4
# Processor: Microblaze
# System clock frequency: 50.000000 MHz
# Debug interface: On-Chip HW Debug Module
# On Chip Memory :
8 KB
#
##############################################################################

PARAMETER VERSION = 2.1.0

PORT fpga_0_RS232_DCE_RX_pin = fpga_0_RS232_DCE_RX, DIR = I


PORT fpga_0_RS232_DCE_TX_pin = fpga_0_RS232_DCE_TX, DIR = O
PORT fpga_0_LEDs_8Bit_GPIO_d_out_pin = fpga_0_LEDs_8Bit_GPIO_d_out, DIR = O, VEC
= [0:7]
PORT sys_clk_pin = dcm_clk_s, DIR = I, SIGIS = CLK, CLK_FREQ = 50000000
PORT sys_rst_pin = sys_rst_s, DIR = I, RST_POLARITY = 1, SIGIS = RST
PORT push_GPIO_in_pin = push_GPIO_in, DIR = I, VEC = [0:3]
PORT dip_GPIO_in_pin = dip_GPIO_in, DIR = I, VEC = [0:3]
PORT lcd_ip_0_lcd_pin = lcd_ip_0_lcd, DIR = O, VEC = [0:6]

BEGIN microblaze
PARAMETER INSTANCE = microblaze_0
PARAMETER HW_VER = 5.00.a
PARAMETER C_USE_FPU = 0
PARAMETER C_DEBUG_ENABLED = 1
PARAMETER C_NUMBER_OF_PC_BRK = 2
BUS_INTERFACE DLMB = dlmb
BUS_INTERFACE ILMB = ilmb
BUS_INTERFACE DOPB = mb_opb
BUS_INTERFACE IOPB = mb_opb

PORT DBG_CAPTURE = DBG_CAPTURE_s


PORT DBG_CLK = DBG_CLK_s
PORT DBG_REG_EN = DBG_REG_EN_s
PORT DBG_TDI = DBG_TDI_s
PORT DBG_TDO = DBG_TDO_s
PORT DBG_UPDATE = DBG_UPDATE_s
END
BEGIN opb_v20
PARAMETER INSTANCE = mb_opb
PARAMETER HW_VER = 1.10.c
PARAMETER C_EXT_RESET_HIGH = 1
PORT SYS_Rst = sys_rst_s
PORT OPB_Clk = sys_clk_s
END
BEGIN opb_mdm
PARAMETER INSTANCE = debug_module
PARAMETER HW_VER = 2.00.a
PARAMETER C_MB_DBG_PORTS = 1
PARAMETER C_USE_UART = 1
PARAMETER C_UART_WIDTH = 8
PARAMETER C_BASEADDR = 0x41400000
PARAMETER C_HIGHADDR = 0x4140ffff
BUS_INTERFACE SOPB = mb_opb
PORT DBG_CAPTURE_0 = DBG_CAPTURE_s
PORT DBG_CLK_0 = DBG_CLK_s
PORT DBG_REG_EN_0 = DBG_REG_EN_s
PORT DBG_TDI_0 = DBG_TDI_s
PORT DBG_TDO_0 = DBG_TDO_s
PORT DBG_UPDATE_0 = DBG_UPDATE_s
END
BEGIN lmb_v10
PARAMETER INSTANCE = ilmb
PARAMETER HW_VER = 1.00.a
PARAMETER C_EXT_RESET_HIGH = 1
PORT SYS_Rst = sys_rst_s
PORT LMB_Clk = sys_clk_s
END
BEGIN lmb_v10
PARAMETER INSTANCE = dlmb
PARAMETER HW_VER = 1.00.a

PARAMETER C_EXT_RESET_HIGH = 1
PORT SYS_Rst = sys_rst_s
PORT LMB_Clk = sys_clk_s
END
BEGIN lmb_bram_if_cntlr
PARAMETER INSTANCE = dlmb_cntlr
PARAMETER HW_VER = 2.00.a
PARAMETER C_BASEADDR = 0x20002000
PARAMETER C_HIGHADDR = 0x20003fff
BUS_INTERFACE SLMB = dlmb
BUS_INTERFACE BRAM_PORT = dlmb_port
END
BEGIN lmb_bram_if_cntlr
PARAMETER INSTANCE = ilmb_cntlr
PARAMETER HW_VER = 2.00.a
PARAMETER C_BASEADDR = 0x20002000
PARAMETER C_HIGHADDR = 0x20003fff
BUS_INTERFACE SLMB = ilmb
BUS_INTERFACE BRAM_PORT = ilmb_port
END
BEGIN bram_block
PARAMETER INSTANCE = lmb_bram
PARAMETER HW_VER = 1.00.a
BUS_INTERFACE PORTA = ilmb_port
BUS_INTERFACE PORTB = dlmb_port
END
BEGIN opb_uartlite
PARAMETER INSTANCE = RS232_DCE
PARAMETER HW_VER = 1.00.b
PARAMETER C_BAUDRATE = 115200
PARAMETER C_DATA_BITS = 8
PARAMETER C_ODD_PARITY = 0
PARAMETER C_USE_PARITY = 0
PARAMETER C_CLK_FREQ = 50000000
PARAMETER C_BASEADDR = 0x40600000
PARAMETER C_HIGHADDR = 0x4060ffff
BUS_INTERFACE SOPB = mb_opb
PORT RX = fpga_0_RS232_DCE_RX
PORT TX = fpga_0_RS232_DCE_TX
END

BEGIN opb_gpio
PARAMETER INSTANCE = LEDs_8Bit
PARAMETER HW_VER = 3.01.b
PARAMETER C_GPIO_WIDTH = 8
PARAMETER C_IS_DUAL = 0
PARAMETER C_IS_BIDIR = 0
PARAMETER C_ALL_INPUTS = 0
PARAMETER C_BASEADDR = 0x40040000
PARAMETER C_HIGHADDR = 0x4004ffff
BUS_INTERFACE SOPB = mb_opb
PORT GPIO_d_out = fpga_0_LEDs_8Bit_GPIO_d_out
END
BEGIN dcm_module
PARAMETER INSTANCE = dcm_0
PARAMETER HW_VER = 1.00.a
PARAMETER C_CLK0_BUF = TRUE
PARAMETER C_CLKIN_PERIOD = 20.000000
PARAMETER C_CLK_FEEDBACK = 1X
PARAMETER C_EXT_RESET_HIGH = 1
PORT CLKIN = dcm_clk_s
PORT CLK0 = sys_clk_s
PORT CLKFB = sys_clk_s
PORT RST = net_gnd
PORT LOCKED = dcm_0_lock
END
BEGIN opb_gpio
PARAMETER INSTANCE = push
PARAMETER HW_VER = 3.01.b
PARAMETER C_IS_BIDIR = 0
PARAMETER C_ALL_INPUTS = 1
PARAMETER C_GPIO_WIDTH = 4
PARAMETER C_BASEADDR = 0x40000000
PARAMETER C_HIGHADDR = 0x4000ffff
BUS_INTERFACE SOPB = mb_opb
PORT GPIO_in = push_GPIO_in
END
BEGIN opb_gpio
PARAMETER INSTANCE = dip
PARAMETER HW_VER = 3.01.b
PARAMETER C_GPIO_WIDTH = 4

PARAMETER C_IS_BIDIR = 0
PARAMETER C_ALL_INPUTS = 1
PARAMETER C_BASEADDR = 0x40020000
PARAMETER C_HIGHADDR = 0x4002ffff
BUS_INTERFACE SOPB = mb_opb
PORT GPIO_in = dip_GPIO_in
END
BEGIN lcd_ip
PARAMETER INSTANCE = lcd_ip_0
PARAMETER HW_VER = 1.00.a
PARAMETER C_BASEADDR = 0x7f600000
PARAMETER C_HIGHADDR = 0x7f60ffff
BUS_INTERFACE SOPB = mb_opb
PORT lcd = lcd_ip_0_lcd
END
BEGIN opb_bram_if_cntlr
PARAMETER INSTANCE = opb_bram_if_cntlr_0
PARAMETER HW_VER = 1.00.a
PARAMETER c_baseaddr = 0x00000000
PARAMETER c_highaddr = 0x00001fff
BUS_INTERFACE SOPB = mb_opb
BUS_INTERFACE PORTA = opb_bram_if_cntlr_0_PORTA
END
BEGIN bram_block
PARAMETER INSTANCE = opb_bram
PARAMETER HW_VER = 1.00.a
BUS_INTERFACE PORTA = opb_bram_if_cntlr_0_PORTA
END

4.5

Software Developers Kit (SDK)

OPB timer

OBP timer

SDK Debugger

OPB OPB
2

OPB
Bus

MD

UART
INTC

MicroBlaze
Timer
LMB
BRAM
Cntl

LMB
BRAM
Cntl
BRAM

ICON

IBA

GPIO

PSB

GPIO

DIP

GPIO

LEDs

MY IP

LCD

4.5.1.

OPB

:
Step 1:

Step 2:

Step 3:

BSP

OPB

Step 4:

SDK

Step 5:

Step 9:

Step 10:

Step 6:

Step 7:

Step 8:

SDK

5
4 Xilinx Platform Studio (XPS)
c:\xup\embedded\labs\lab5(
)
n 5
4
o Xilinx Platform Studio 8.2i Xilinx Platform Studio
XPS
p

Open Recent Project, OK

system.xmp

OPB

:
Step 1:

Step 2:

Step 3:

BSP

OPB

Step 4:

SDK

Step 5:

Step 9:

Step 10:

Step 7:

Step 6:

Step 8:

SDK

IP Catalog OPB OPB_INTC

opb_clk
Intr
Irq

opb_intc instance
sys_clk_s
timer1
Interrupt
delay instance

CaptureTrig0
net_gnd
Interrupt
timer1
microblaze_0 instance
INTERRUPT
Interrupt
n IP Catalog Timers opb_timer delay
o

IP Catalog Interrupt opb_intc

timer interrupt s (slave) OPB

4.5.2.

Addresses opb_intc delay

r size 512 bytes Generate Addresses

4.5.3.

s Ports timer1 delay Interrupt


t

microblaze_0 net INTERRUPT ()

interrupt
u opb_intc_0 Intr Irq net timer1 and interrupt
delay CaptureTrig0 net net_gnd.

4.5.4.

v delay Only One Timer is Present


w OK

BSP

:
Step 1:

Step 2:

Step 3:

BSP

OPB

Step 4:

SDK

Step 5:

Step 9:

Step 10:

Step 6:

Step 7:

Step 8:

SDK

Software Platform Settings delay


xparameters.h
n

Software Software Platform Settings timer_int_handler

delay .

4.5.5.
o OK
p Software Generate Libraries and BSPs xparameters.h

Platform Studio Software Development Kit (SDK)

:
Step 1:

Step 2:

Step 3:

BSP

OPB

Step 4:

SDK

Step 5:

Step 9:

Step 10:

Step 6:

Step 7:

Step 8:

SDK
n Software Launch Platform Studio SDK SDK
SDK 5 Welcome
{

Import XPS Design XPS

Overview Eclipse

Tutorials Eclipse

Samples Eclipse

Whats New

Welcome .

SDK

:
Step 1:

Step 2:

Step 3:

BSP

Step 4:

SDK

Step 5:

Step 9:

Step 10:

OPB

Step 6:

Step 7:

Step 8:

Platform Studio C
n Create a new SDK Application Project Next.

4.5.6. Managed Make C Project


q

sdk_lab

Create sample file in project Finish

SDK lab5SDK_projectssdk_lab.

SDK

4.5.7.

:
Step 1:

Step 2:

Step 3:

BSP

OPB

Step 4:

SDK

Step 5:

Step 9:

Step 10:

Step 6:

Step 7:

Step 8:

SDK

n C/C++ Projects

XPS LibGen

4.5.8. Software Project


o sdk_lab Properties ( Project
Properties )
p sdk_lab Properties C/C++ Build

makefile

Cancel
linker script

sdk_lab

:
Step 1:

Step 2:

Step 3:

BSP

OPB

Step 4:

SDK

Step 5:

Step 9:

SDK

Step 6:

Step 7:

Step 8:

Step 10:

SDK lab.c
n File Import File System
c:xupembeddedsp3ekitsources lab5.c Finish

Navigator , lab5.c

Problems Console

p Problems , x . 80

4.5.9. 1
q unsigned 1 1

4.5.10. 2
s int 0
Outline , timer_int_handler
;


Step 8
:
Step 1:

Step 2:

Step 3:

BSP

OPB

Step 4:

SDK

Step 5:

Step 9:

SDK

Step 6:

Step 7:

Step 8:

Step 10:

Window ->
Preference Preferences Workbench Build automatically
Project -> Build All
Console

OPB
n outline
timer_int_handler. Software Platform
Settings

timer_int_handler:
unsigned int csr;

OPB OPB
OPB Timer Control Status Register API
Control Status Register
n XPS System Assembly View , opb_timer delay and
View PDF Datasheet data sheet
o

data sheet Register Description TCSR0 Register. btt 23

Timer0 Interrupt
Indicates that the condition for an interrupt on this timer has occurred. If the timer mode
is capture and the timer is enabled, this bit indicates a capture has occurred.

If the mode

is generate, this bit indicates the counter has rolled over. Must be cleared by writing a 1

Read:
0 - No interrupt has occurred
1 - Interrupt has occurred
Write:
0 No change in state of T0INT
1 Clear T0INT (clear to 0)

OPB 0 2 Control Status Register


System Assembly View delay, Driver:tmrctr_v1_00_b J View API
Documentation API API File List
, xtmrctr_l.h

XTmrCtr_mGetControlStatusReg( )
OPB :
p

XTmrCtr_mGetControlStatusReg ( BaseAddress, TmrCtrNumber )


Get the Control Status Register of a timer counter
{

Parameters:
o BaseAddress is the base address of the device.
o TmrCtrNumber is the specific timer counter within the device, a zero-based
number, 0 -> (XTC_DEVICE_TIMER_COUNT - 1)

Returns:
o The value read from the register, a 32-bit value

XTmrCtr_mGetControlStatusReg 32

csr. XTmrCtr CNTL-SPACE


- XTmrCtr

csr = XTmrCtr_mGetControlStatusReg(baseaddr, 0);


: xparameters.h baseaddr delay .

csr bit23

XTC_CSR_INT_OCCURED_MASK ANDing csr


LEDs_8Bit XGpio_mSetDataReg()
printf
s

:
XTmrCtr_mSetControlStatusReg(baseaddr, 0, csr);

4.5.11
t

Console
?
.text segment:
.data segment:
.bss segment:
Total in decimal:
Total in hexadecimal:

xupv2pro_LinkScr.ld linker
script
n C/C++ Projects , sdk_lab Properties
Properties ( Project Properties )

C/C++ Build. Configuration Settings Tool Settings

PowerPC C Linker Linker Script

4.5.8),

4.5.12. Linker Script


p

c:xup embeddedsources lab5_LinkScr.ld

OK

linker script ,
linker script linker script

?
_____________________________________________________________
___
_____________________________________________________________
___

r printf xil_printf
xil_printf printf
s /

?
.text segment:
.data segment:
.bss segment:
Total in decimal:
Total in hexadecimal:

:
Step 1:

Step 2:

Step 3:

BSP

OPB

Step 4:

SDK

Step 5:

Step 9:

Step 10:

Step 6:

Step 7:

Step 8:

SDK

Spartan-3E starter kit.


n
o Device Configuration J Program Hardware
FPGA

4.5.13.

SDK

Step 1:

Step 2:

Step 3:

BSP

OPB

Step 4:

SDK

Step 5:

Step 9:

SDK

Step 6:

Step 7:

Step 8:

Step 10:

n SDK , Run Run


This will present a screen summarizing the existing Launch Configurations
o Configurations , Xilinx C/C++ ELF
p New Launch configuration sdk_debug

4.5.14.

Apply Run

r Console Terminate button ()

4.5.15. XMD

s OK

.
n SDK Run Debug
Launch Configurations
o Debug. Debug Perspective
Yes
Debug perspective. XMD
main
p Resume .

4.5.16.

q Debug Thread[0] (Running)

4.5.17.
r

Suspend Terminate

Suspend

Variables Add Global Variables

count OK
u count Enable

4.5.18 Enable

.
n lab5.c 65 ,

4.5.19.

o Resume
count

Memory , LEDs_8Bit , evaluate my_led

xparameters.h XPS
q

Resume
LEDs_8Bit

4.5.20. my_led (0x7d800000)

r sdk_lab Terminate

4.5.21.

s SDK

OPB software platform


settings
SDK

4.

.text segment:

57188

.data segment:

1928

.bss segment:

1120

Total in decimal:

60236

Total in hexadecimal:
5.

eb4c

printf

6.

.text segment:

4224

.data segment:

825

.bss segment:

683

Total in decimal:

5732

Total in hexadecimal:

1664

MHS
#
###########################################################################
###
# Created by Base System Builder Wizard for Xilinx EDK 8.2 Build EDK_Im.14
# Tue Aug 29 14:15:28 2006
# Target Board: Xilinx XUP Virtex-II Pro Development System Rev C
# Family: virtex2p
# Device: xc2vp30
# Package:
ff896
# Speed Grade: -7
# Processor: PPC 405
# Processor clock frequency: 300.000000 MHz
# Bus clock frequency: 100.000000 MHz
# Debug interface: FPGA JTAG
# On Chip Memory : 64 KB
#
###########################################################################
###

PARAMETER VERSION = 2.1.0

PORT fpga_0_RS232_Uart_1_RX_pin = fpga_0_RS232_Uart_1_RX, DIR = I


PORT fpga_0_RS232_Uart_1_TX_pin = fpga_0_RS232_Uart_1_TX, DIR = O
PORT sys_clk_pin = dcm_clk_s, DIR = I, SIGIS = CLK, CLK_FREQ = 100000000
PORT sys_rst_pin = sys_rst_s, DIR = I, RST_POLARITY = 0, SIGIS = RST
PORT dip = DIP, DIR = I, VEC = [0:3]
PORT push = PUSH, DIR = I, VEC = [0:4]
PORT led = fpga_0_LEDs_4Bit_GPIO_d_out, DIR = O, VEC = [0:3]

BEGIN ppc405
PARAMETER INSTANCE = ppc405_0
PARAMETER HW_VER = 2.00.c
BUS_INTERFACE JTAGPPC = jtagppc_0_0
BUS_INTERFACE IPLB = plb
BUS_INTERFACE DPLB = plb
PORT PLBCLK = sys_clk_s
PORT C405RSTCHIPRESETREQ = C405RSTCHIPRESETREQ
PORT C405RSTCORERESETREQ = C405RSTCORERESETREQ

PORT C405RSTSYSRESETREQ = C405RSTSYSRESETREQ


PORT RSTC405RESETCHIP = RSTC405RESETCHIP
PORT RSTC405RESETCORE = RSTC405RESETCORE
PORT RSTC405RESETSYS = RSTC405RESETSYS
PORT CPMC405CLOCK = proc_clk_s
PORT EICC405EXTINPUTIRQ = interrupt
END
BEGIN ppc405
PARAMETER INSTANCE = ppc405_1
PARAMETER HW_VER = 2.00.c
BUS_INTERFACE JTAGPPC = jtagppc_0_1
END
BEGIN jtagppc_cntlr
PARAMETER INSTANCE = jtagppc_0
PARAMETER HW_VER = 2.00.a
BUS_INTERFACE JTAGPPC0 = jtagppc_0_0
BUS_INTERFACE JTAGPPC1 = jtagppc_0_1
END
BEGIN proc_sys_reset
PARAMETER INSTANCE = reset_block
PARAMETER HW_VER = 1.00.a
PARAMETER C_EXT_RESET_HIGH = 0
PORT Ext_Reset_In = sys_rst_s
PORT Slowest_sync_clk = sys_clk_s
PORT Chip_Reset_Req = C405RSTCHIPRESETREQ
PORT Core_Reset_Req = C405RSTCORERESETREQ
PORT System_Reset_Req = C405RSTSYSRESETREQ
PORT Rstc405resetchip = RSTC405RESETCHIP
PORT Rstc405resetcore = RSTC405RESETCORE
PORT Rstc405resetsys = RSTC405RESETSYS
PORT Bus_Struct_Reset = sys_bus_reset
PORT Dcm_locked = dcm_0_lock
END
BEGIN plb_v34
PARAMETER INSTANCE = plb
PARAMETER HW_VER = 1.02.a
PARAMETER C_DCR_INTFCE = 0
PARAMETER C_EXT_RESET_HIGH = 1
PORT SYS_Rst = sys_bus_reset
PORT PLB_Clk = sys_clk_s

END
BEGIN opb_v20
PARAMETER INSTANCE = opb
PARAMETER HW_VER = 1.10.c
PARAMETER C_EXT_RESET_HIGH = 1
PORT SYS_Rst = sys_bus_reset
PORT OPB_Clk = sys_clk_s
END
BEGIN plb2opb_bridge
PARAMETER INSTANCE = plb2opb
PARAMETER HW_VER = 1.01.a
PARAMETER C_DCR_INTFCE = 0
PARAMETER C_RNG0_BASEADDR = 0x40000000
PARAMETER C_RNG0_HIGHADDR = 0x7fffffff
PARAMETER C_NUM_ADDR_RNG = 1
BUS_INTERFACE SPLB = plb
BUS_INTERFACE MOPB = opb
END
BEGIN opb_uartlite
PARAMETER INSTANCE = RS232_Uart_1
PARAMETER HW_VER = 1.00.b
PARAMETER C_BAUDRATE = 115200
PARAMETER C_DATA_BITS = 8
PARAMETER C_ODD_PARITY = 0
PARAMETER C_USE_PARITY = 0
PARAMETER C_CLK_FREQ = 100000000
PARAMETER C_BASEADDR = 0x40600000
PARAMETER C_HIGHADDR = 0x4060ffff
BUS_INTERFACE SOPB = opb
PORT RX = fpga_0_RS232_Uart_1_RX
PORT TX = fpga_0_RS232_Uart_1_TX
END
BEGIN plb_bram_if_cntlr
PARAMETER INSTANCE = plb_bram_if_cntlr_1
PARAMETER HW_VER = 1.00.b
PARAMETER c_plb_clk_period_ps = 10000
PARAMETER c_baseaddr = 0xffff0000
PARAMETER c_highaddr = 0xffffffff
BUS_INTERFACE SPLB = plb
BUS_INTERFACE PORTA = plb_bram_if_cntlr_1_PORTA

END
BEGIN bram_block
PARAMETER INSTANCE = plb_bram_if_cntlr_1_bram
PARAMETER HW_VER = 1.00.a
BUS_INTERFACE PORTA = plb_bram_if_cntlr_1_PORTA
END
BEGIN dcm_module
PARAMETER INSTANCE = dcm_0
PARAMETER HW_VER = 1.00.a
PARAMETER C_CLK0_BUF = TRUE
PARAMETER C_CLKFX_BUF = TRUE
PARAMETER C_CLKFX_DIVIDE = 1
PARAMETER C_CLKFX_MULTIPLY = 3
PARAMETER C_CLKIN_PERIOD = 10.000000
PARAMETER C_CLK_FEEDBACK = 1X
PARAMETER C_DFS_FREQUENCY_MODE = HIGH
PARAMETER C_DLL_FREQUENCY_MODE = LOW
PARAMETER C_EXT_RESET_HIGH = 1
PORT CLKIN = dcm_clk_s
PORT CLK0 = sys_clk_s
PORT CLKFX = proc_clk_s
PORT CLKFB = sys_clk_s
PORT RST = net_gnd
PORT LOCKED = dcm_0_lock
END
BEGIN plb_bram_if_cntlr
PARAMETER INSTANCE = plb_bram_if_cntlr_2
PARAMETER HW_VER = 1.00.b
PARAMETER c_baseaddr = 0x00000000
PARAMETER c_highaddr = 0x00003fff
BUS_INTERFACE SPLB = plb
BUS_INTERFACE PORTA = plb_bram_if_cntlr_2_PORTA
END
BEGIN bram_block
PARAMETER INSTANCE = plb_bram_if_cntlr_2_bram
PARAMETER HW_VER = 1.00.a
BUS_INTERFACE PORTA = plb_bram_if_cntlr_2_PORTA
END
BEGIN opb_gpio

PARAMETER INSTANCE = dip1


PARAMETER HW_VER = 3.01.b
PARAMETER C_GPIO_WIDTH = 4
PARAMETER C_IS_BIDIR = 0
PARAMETER C_ALL_INPUTS = 1
PARAMETER C_BASEADDR = 0x40020000
PARAMETER C_HIGHADDR = 0x400201FF
BUS_INTERFACE SOPB = opb
PORT GPIO_in = DIP
END
BEGIN opb_gpio
PARAMETER INSTANCE = push1
PARAMETER HW_VER = 3.01.b
PARAMETER C_GPIO_WIDTH = 5
PARAMETER C_IS_BIDIR = 0
PARAMETER C_ALL_INPUTS = 1
PARAMETER C_BASEADDR = 0x40000000
PARAMETER C_HIGHADDR = 0x400001FF
BUS_INTERFACE SOPB = opb
PORT GPIO_in = PUSH
END
BEGIN my_led
PARAMETER INSTANCE = my_led_0
PARAMETER HW_VER = 1.00.a
PARAMETER C_BASEADDR = 0x7d800000
PARAMETER C_HIGHADDR = 0x7d8001ff
BUS_INTERFACE SOPB = opb
PORT LED = fpga_0_LEDs_4Bit_GPIO_d_out
END
BEGIN opb_timer
PARAMETER INSTANCE = delay
PARAMETER HW_VER = 1.00.b
PARAMETER C_BASEADDR = 0x41C00000
PARAMETER C_HIGHADDR = 0x41C001FF
PARAMETER C_ONE_TIMER_ONLY = 1
BUS_INTERFACE SOPB = opb
PORT Interrupt = timer1
PORT CaptureTrig0 = net_gnd
END
BEGIN opb_intc

PARAMETER INSTANCE = opb_intc_0


PARAMETER HW_VER = 1.00.c
PARAMETER C_BASEADDR = 0x41200000
PARAMETER C_HIGHADDR = 0x412001FF
BUS_INTERFACE SOPB = opb
PORT Intr = timer1
PORT Irq = interrupt
END

4.6

XPS ChipScope

ChipScope Analyzers
Chipscope SDK debugger

OPB
Bus

MD

UART
INTC

MicroBlaze
Timer
LMB
BRAM
Cntl

LMB
BRAM
Cntl
BRAM

ICON

IBA

GPIO

PSB

GPIO

DIP

GPIO

LEDs

MY IP

LCD

4.6.1. MicroBlaze

:
Step 1:

Step 2:

Step 3:

Step 4:

SDK

Chipscope

Chipscope

c:\xup\embedded\microblaze\labs\ lab6
lab5 lab5
lab6 Xilinx Platform Studio (XPS)
c:\xup\embedded\microblaze\labs\lab6
n c:xupembeddedmicroblazelabs lab6
lab5 lab5 lab6
o Start Programs Xilinx Platform Studio 8.2i Xilinx Platform
Studio XPS

Open Recent Project OK


C:xupembeddedmicroblazelabslab6
Select Open Recent Project, Click OK and browse to
C:xupembeddedmicroblazelabslab6

q system.xmp
r

Click system.xmp to open the project

ChipScope

Step 1:

Step 2:

Step 3:

Step 4:

SDK

Chipscope

Chipscope

IP Catalog ChipScope 4.6.2


OPB OPB OPB
trigger to trigger

4.6.2. ChipScope

n IP Catalog Debug section chipscope_icon chipscope_opb_iba


chipscope_opb_iba OPB

4.6.3. Chipscope OPB


o Ports chipscope_cores microblaze_0

Instance

Port Name

Net Name

chipscope_icon_0

control0

chipscope_icon_0_control0

chipscope_opb_iba_0

chipscope_icon_control

chipscope_icon_0_control0

chipscope_opb_iba_0

iba_trig_out

dbg_stop

microBlaze_0

DBG_STOP

dbg_stop

p chipscope_icon_0 IP (instance) Number of Control Ports 1

q chipscope_opb_iba_0 IP

4.6.4

r Download

SDK ChipScope

Step 1:

Step 2:

Step 3:

Step 4:

SDK

Chipscope

Chipscope

SDK XMD

SDK
n SDK Software Launch Platform Studio SDK
o wizard cance
p

lab5 sdk_lab sdk_lab delete do not

delete contents
q

lab6 SDK File Import Existing Project Into Workspace

<Next>lab6SDK_projectssdk_lab<Finish>

4.6.5. SDK

s Run Run

4.6.6. .elf

s Run

debug sdk_lab

4.6.7 debug

SDK Debugger

4.6.8. XMD SDK Debugger


main( )

u Thread [0] Resume LED

ChipScope Pro

n ChipScope Pro Analyzer


o Open Cable/Search JTAG chain

JTAG

OK ChipScope Pro Analyzer Trigger Setup Waveform signal

4.6.9. ChipScope JTAG

File Import Signal Import Select New File

XPS
c:xupembeddedlabslab6implementationchipscope_opb_iba_0_wrapper cs_c
oregen_chipscope_opb_iba_0.cdc OK 4.6.8

OPB Trigger Setup Waveform signal

Step 1:

Step 2:

Step 3:

Step 4:

SDK

Chipscope

Chipscope

Trigger/Waveform

4.6.10. ChipScope
n

M0:TRG0:OPB_CTRL OPB_RNW bit == 0 M0 +


OPB_RNW 0

o M1 M2 (Bin)(Hex)
Bin Hex
p M1:TRIG1:OPB_ABUS == 7D80_0000 LED 8
M2:TRIG2:OPB_DBUS == 0000_0005 value

TriggerCondition0 Trigger Condition Equation

M0

M1 M2

r M0 && M1 && M2 OK
s trigger depth 512position 0

t [Shift Select] Waveform Signals


OPB_Dbus Add To View Waveform
Waveform OPB_ABUS OPB_RNW
u Trigger Output Enable Pulse (High)
Trigger Setup -> Run

4.6.11 Trigger Setup -> Run

n Resume

GDB
ChipScope Pro Trigger Chipscope-Pro
4.6.12

Expected

4.6.12. Chipscope-Pro

X/O v8.2 Chipscope

/docs

Chipscope IP EDK ChipScope


SDK JTAG

MHS
#
##############################################################################
# Created by Base System Builder Wizard for Xilinx EDK 8.2 Build EDK_Im.14
# Fri Sep 01 11:41:45 2006
# Target Board: Xilinx Spartan-3E Starter Board Rev C
# Family: spartan3e
# Device: XC3S500e
# Package:
FG320
# Speed Grade:
-4
# Processor: Microblaze
# System clock frequency: 50.000000 MHz
# Debug interface: On-Chip HW Debug Module
# On Chip Memory :
8 KB
#
##############################################################################

PARAMETER VERSION = 2.1.0

PORT fpga_0_RS232_DCE_RX_pin = fpga_0_RS232_DCE_RX, DIR = I


PORT fpga_0_RS232_DCE_TX_pin = fpga_0_RS232_DCE_TX, DIR = O
PORT fpga_0_LEDs_8Bit_GPIO_d_out_pin = fpga_0_LEDs_8Bit_GPIO_d_out, DIR = O, VEC
= [0:7]
PORT sys_clk_pin = dcm_clk_s, DIR = I, SIGIS = CLK, CLK_FREQ = 50000000
PORT sys_rst_pin = sys_rst_s, DIR = I, RST_POLARITY = 1, SIGIS = RST
PORT push_GPIO_in_pin = push_GPIO_in, DIR = I, VEC = [0:3]
PORT dip_GPIO_in_pin = dip_GPIO_in, DIR = I, VEC = [0:3]
PORT lcd_ip_0_lcd_pin = lcd_ip_0_lcd, DIR = O, VEC = [0:6]

BEGIN microblaze
PARAMETER INSTANCE = microblaze_0
PARAMETER HW_VER = 5.00.a
PARAMETER C_USE_FPU = 0
PARAMETER C_DEBUG_ENABLED = 1
PARAMETER C_NUMBER_OF_PC_BRK = 2
BUS_INTERFACE DLMB = dlmb
BUS_INTERFACE ILMB = ilmb
BUS_INTERFACE DOPB = mb_opb
BUS_INTERFACE IOPB = mb_opb

PORT DBG_CAPTURE = DBG_CAPTURE_s


PORT DBG_CLK = DBG_CLK_s
PORT DBG_REG_EN = DBG_REG_EN_s
PORT DBG_TDI = DBG_TDI_s
PORT DBG_TDO = DBG_TDO_s
PORT DBG_UPDATE = DBG_UPDATE_s
PORT INTERRUPT = interrupt
PORT DBG_STOP = dbg_stop
END
BEGIN opb_v20
PARAMETER INSTANCE = mb_opb
PARAMETER HW_VER = 1.10.c
PARAMETER C_EXT_RESET_HIGH = 1
PORT SYS_Rst = sys_rst_s
PORT OPB_Clk = sys_clk_s
END
BEGIN opb_mdm
PARAMETER INSTANCE = debug_module
PARAMETER HW_VER = 2.00.a
PARAMETER C_MB_DBG_PORTS = 1
PARAMETER C_USE_UART = 1
PARAMETER C_UART_WIDTH = 8
PARAMETER C_BASEADDR = 0x41400000
PARAMETER C_HIGHADDR = 0x4140ffff
BUS_INTERFACE SOPB = mb_opb
PORT DBG_CAPTURE_0 = DBG_CAPTURE_s
PORT DBG_CLK_0 = DBG_CLK_s
PORT DBG_REG_EN_0 = DBG_REG_EN_s
PORT DBG_TDI_0 = DBG_TDI_s
PORT DBG_TDO_0 = DBG_TDO_s
PORT DBG_UPDATE_0 = DBG_UPDATE_s
END
BEGIN lmb_v10
PARAMETER INSTANCE = ilmb
PARAMETER HW_VER = 1.00.a
PARAMETER C_EXT_RESET_HIGH = 1
PORT SYS_Rst = sys_rst_s
PORT LMB_Clk = sys_clk_s
END
BEGIN lmb_v10

PARAMETER INSTANCE = dlmb


PARAMETER HW_VER = 1.00.a
PARAMETER C_EXT_RESET_HIGH = 1
PORT SYS_Rst = sys_rst_s
PORT LMB_Clk = sys_clk_s
END
BEGIN lmb_bram_if_cntlr
PARAMETER INSTANCE = dlmb_cntlr
PARAMETER HW_VER = 2.00.a
PARAMETER C_BASEADDR = 0x20002000
PARAMETER C_HIGHADDR = 0x20003fff
BUS_INTERFACE SLMB = dlmb
BUS_INTERFACE BRAM_PORT = dlmb_port
END
BEGIN lmb_bram_if_cntlr
PARAMETER INSTANCE = ilmb_cntlr
PARAMETER HW_VER = 2.00.a
PARAMETER C_BASEADDR = 0x20002000
PARAMETER C_HIGHADDR = 0x20003fff
BUS_INTERFACE SLMB = ilmb
BUS_INTERFACE BRAM_PORT = ilmb_port
END
BEGIN bram_block
PARAMETER INSTANCE = lmb_bram
PARAMETER HW_VER = 1.00.a
BUS_INTERFACE PORTA = ilmb_port
BUS_INTERFACE PORTB = dlmb_port
END
BEGIN opb_uartlite
PARAMETER INSTANCE = RS232_DCE
PARAMETER HW_VER = 1.00.b
PARAMETER C_BAUDRATE = 115200
PARAMETER C_DATA_BITS = 8
PARAMETER C_ODD_PARITY = 0
PARAMETER C_USE_PARITY = 0
PARAMETER C_CLK_FREQ = 50000000
PARAMETER C_BASEADDR = 0x40600000
PARAMETER C_HIGHADDR = 0x4060ffff
BUS_INTERFACE SOPB = mb_opb
PORT RX = fpga_0_RS232_DCE_RX

PORT TX = fpga_0_RS232_DCE_TX
END
BEGIN opb_gpio
PARAMETER INSTANCE = LEDs_8Bit
PARAMETER HW_VER = 3.01.b
PARAMETER C_GPIO_WIDTH = 8
PARAMETER C_IS_DUAL = 0
PARAMETER C_IS_BIDIR = 0
PARAMETER C_ALL_INPUTS = 0
PARAMETER C_BASEADDR = 0x40040000
PARAMETER C_HIGHADDR = 0x4004ffff
BUS_INTERFACE SOPB = mb_opb
PORT GPIO_d_out = fpga_0_LEDs_8Bit_GPIO_d_out
END
BEGIN dcm_module
PARAMETER INSTANCE = dcm_0
PARAMETER HW_VER = 1.00.a
PARAMETER C_CLK0_BUF = TRUE
PARAMETER C_CLKIN_PERIOD = 20.000000
PARAMETER C_CLK_FEEDBACK = 1X
PARAMETER C_EXT_RESET_HIGH = 1
PORT CLKIN = dcm_clk_s
PORT CLK0 = sys_clk_s
PORT CLKFB = sys_clk_s
PORT RST = net_gnd
PORT LOCKED = dcm_0_lock
END
BEGIN opb_gpio
PARAMETER INSTANCE = push
PARAMETER HW_VER = 3.01.b
PARAMETER C_IS_BIDIR = 0
PARAMETER C_ALL_INPUTS = 1
PARAMETER C_GPIO_WIDTH = 4
PARAMETER C_BASEADDR = 0x40000000
PARAMETER C_HIGHADDR = 0x4000ffff
BUS_INTERFACE SOPB = mb_opb
PORT GPIO_in = push_GPIO_in
END
BEGIN opb_gpio
PARAMETER INSTANCE = dip

PARAMETER HW_VER = 3.01.b


PARAMETER C_GPIO_WIDTH = 4
PARAMETER C_IS_BIDIR = 0
PARAMETER C_ALL_INPUTS = 1
PARAMETER C_BASEADDR = 0x40020000
PARAMETER C_HIGHADDR = 0x4002ffff
BUS_INTERFACE SOPB = mb_opb
PORT GPIO_in = dip_GPIO_in
END
BEGIN lcd_ip
PARAMETER INSTANCE = lcd_ip_0
PARAMETER HW_VER = 1.00.a
PARAMETER C_BASEADDR = 0x7f600000
PARAMETER C_HIGHADDR = 0x7f60ffff
BUS_INTERFACE SOPB = mb_opb
PORT lcd = lcd_ip_0_lcd
END
BEGIN opb_bram_if_cntlr
PARAMETER INSTANCE = opb_bram_if_cntlr_0
PARAMETER HW_VER = 1.00.a
PARAMETER c_baseaddr = 0x00000000
PARAMETER c_highaddr = 0x00001fff
BUS_INTERFACE SOPB = mb_opb
BUS_INTERFACE PORTA = opb_bram_if_cntlr_0_PORTA
END
BEGIN bram_block
PARAMETER INSTANCE = opb_bram
PARAMETER HW_VER = 1.00.a
BUS_INTERFACE PORTA = opb_bram_if_cntlr_0_PORTA
END
BEGIN opb_timer
PARAMETER INSTANCE = delay
PARAMETER HW_VER = 1.00.b
PARAMETER C_BASEADDR = 0x41C00000
PARAMETER C_HIGHADDR = 0x41C001FF
PARAMETER C_ONE_TIMER_ONLY = 1
BUS_INTERFACE SOPB = mb_opb
PORT Interrupt = timer1
PORT CaptureTrig0 = net_gnd
END

BEGIN opb_intc
PARAMETER INSTANCE = opb_intc_0
PARAMETER HW_VER = 1.00.c
PARAMETER C_BASEADDR = 0x41200000
PARAMETER C_HIGHADDR = 0x412001FF
BUS_INTERFACE SOPB = mb_opb
PORT Intr = timer1
PORT Irq = interrupt
END
BEGIN chipscope_icon
PARAMETER INSTANCE = chipscope_icon_0
PARAMETER HW_VER = 1.01.a
PORT control0 = chipscope_icon_0_control0
END
BEGIN chipscope_opb_iba
PARAMETER INSTANCE = chipscope_opb_iba_0
PARAMETER HW_VER = 1.01.a
PARAMETER C_CONTROL_UNIT_MATCH_TYPE = extended with edges
PARAMETER C_DATA_UNIT_MATCH_TYPE = extended with edges
PARAMETER C_ENABLE_TRIGGER_SEQUENCER = 0
PARAMETER C_ENABLE_STORAGE_QUALIFICATION = 0
BUS_INTERFACE MON_OPB = mb_opb
PORT chipscope_icon_control = chipscope_icon_0_control0
PORT iba_trig_out = dbg_stop
END


5.1

Embedded Operating SystemEOS

5.1.1

VxWorkseCosPalm OS uC/OS II

WinCE Linux
1VxWorks
VxWorks WindRiver 1983
RTOS Tornado

VxWorks
POSIX1003.1b
TCP/IP

10

2WinCE
Windows CE Windows Windows CE
WinCE3.0 32

200 K B ROM Windows CE

Windows

3uC/OS II
uC/OS II
8 16 ,32

64

4 Linux
Linux Linux
Linux
Linux Linux
Linux
Linux
RTLinuxRTAIEL Linux-SRT
RTLinux Linux APIRTAI
DIAPM Polytechnic Politecnico di MilanoDIAPM
RTLinux API EL/IX POSIX
Linux API Red Hat Linux-SRT API
Linux

5.1.1

5.1.2

Linux WinCE
VxWorks WinCE
ARMPPC68000
2

WinCE
Windows
3

VxWorks

Linux VxWorks 256

VxWorks

5.2
5.2.1 BSP
1.
BSP(Board Support Package)

,
BSPbootloader
BSP

BSP

BSP
BSP
BSP BSP
BSP
BSP

I/O System

OS Libraries
OS Kernel
BSP

TCP/IP

SCSI Controller

Serial Controller

Clock Timer

Ethernet Controller

5.1.2 BSP

PC windows linux BSP PC


X86 Windows,linux..) BSP x86
OS x86
PC BSP
CPURISC)(PPC,ARM,MIPS....),

CPU, BSP CPU,


DRAM BSP
BSP

2. BSP BIOS
BSP PC BIOS BIOS

Firmware

OS BIOS
BIOS PC BIOS
Bootloader,
BSP
BSP BIOS BIOS
BSP ...),
BSP BSP
BSP BIOS
I/O

3. BSP
BSP

1
2BSP
3
BSP BSP
BSP

5.2.2
1.

LDD
PDD

LCDVGA

FlashSD

USBI2CSPI

WIFI

2.

x86IN OUT

ARM
LDDPDD
LDD
PDD
XON XOFF
LDD
NS-16550 UART
PL-011 PDD
LDDLDD PDD

PDDPDD LDD
LDD

bug

3.
1)

Cache MMU
Cache
Cache
Cache

IO
volatile

2)

mutexcriticalsectionspinlocksemaphore

3) FIFO DMA
FIFO
FIFO FIFO
FIFO

DMA DMA
DMA DMA FIFO
DMA Cacheable DMA

4. Linux
Linux API

Linux /dev
/dev/lp0

Linux
z

/dev/console/dev/ttyS0
tty1lp0

1K
1K 1K Linux

eth0eth1

USB 1394SCSI

1
Linux 3
1

2 I/O

sleep()
3 Linux
Linux

I/O /
Linux
file_operation
linux/fs.h file_operaiton

file_operation
fsynfasynlock
file_operation NULLfile_operaiton
file_operation

2Linux
linux

request_irq free_irq
Linux
3
Linux
file_operation Linux
register_chrdev register_chrdev
#include<linux/fs.h>
#include<linux/error.h>
int register_chrdev(unsigned int major, const char * name, struct file_operation * fops);

major Name fops


register_chrdev
/proc/device
int unregister_chrdev(unsigned int major, const char * name);

Major name


(1)

(2)

(3)
Linux

/proc/device
(4)
IRQ
int request_irq(unsigned int irq,
void (*handler)(int, void *, struct pt_regs *),
unsigned long flags,
const char * device,
void * dev_id);

(5)
IRQ DMA

int __init chr_driver_init(void); __init

int init_module(void)

1
/

Linux
1
2
3 file_operation
4 read write
5 request_irq
6 ismod
7

5. Windows CE
Windows CE
device.exe
Windows CE
XXX_OpenXXX_CloseXXX_ReadXXX_Write

5.2.3 POSIX
1.
POSIX Portable Operating System Interface
IEEE
API UNIX
UNIX POSIX
GNU Richard Stallman POSIX
UNIXPOSIX IEEE IEEE Std 1003.1-1988
POSIX IEEE Std 1003.nn
POSIX.1 IEEE Std 1003.1 POSIX
POSIX ISO ISO/IEC
9945IEEE Std 1003.1POSIX.1 Open Group
Base Specifications IEEE Std 1003.1

2.
POSIX 1980 UNIX (usr/group)
UNIX AT&T V Berkeley CSRG BSD
1984 /usr/group
1985 IEEE TCOS-SS
ANSI IEEE
1986 4 IEEE
1988 9 IEEE 1003.1-1988
POSIX.1 1989 POSIX ISO/IEC 15
ISO 1990 POSIX.1 C
IEEE 1003.1-1990 ANSI ISO/IEC 9945-1:1990

POSIX.1 API

IEEE POSIX
1990 300
(POSIX.2)
POSIX.3 APIPOSIX.4 1990 25
16
X/OpenAT&TOSF

50
(Open Group)

3.
POSIX IEEE Std 1003

1003.1

Library procedures (mostly system calls)

1003.2

Shell and utilities

1003.3

Test methods and conformance

1003.4

Real-time binary semaphores, process memory locking, memory-mapped files,


shared memory, priority scheduling, real-time signals, clocks and timers, IPC
message passing, synchronized I/O, asynchronous I/O, real-time files

1003.5

Ada language bindings

1003.6

Security

1003.7

System admin (incl. printing)

1003.8

Transparent file access

1003.9

FORTRAN language bindings

1003.10

Super computing

1003.12

Protocol-independent I/Fs

1003.13

Real-time profiles

1003.15

Supercomputing batch I/Fs

1003.16

C-language bindings (?)

1003.17

Directory services

1003.18

POSIX standardized profile

1003.19

FORTRAN 90 language bindings

POSIX.1 IEEE Std 1003.1, 2004 Edition


http://www.opengroup.org/onlinepubs/009695399/toc.htm

4. POSIX Linux
90 POSIX
1991-1993 Linux UNIX Linux
Linux UNIX
Linux (0.01 0.11 ) Linux POSIX
0.01 /include/unistd.h
POSXI ok

1991 7 3 comp.os.minix post


POSIX ( Linux Linus
FREAXFREAX )
Linux Linux
POSIX
Alan Cox 1992 9 23 comp.os.linux 386BSD
Linux Linux
386BSD Linux POSIX (Linux is more
POSIX-like.)
Linux POSIX POSIX

Linux

5.3
5.3.1 Microblaze
1
Microbaze
BSP
Microblaze
Microblaze

2
1 Microblaze uclinux
uclinux_v1_00_d EDK \sw\lib\bsp
2 Microblaze test
Spartan_uclinux EDK

3 Spartan_uclinux system.xmp

4 Microblaze
EDK System assembly
View Bus interface
Microblaze

5 port Microblaze

6 Addresses Microblaze

7
port debug module interupt net debug module
interupt

8 port opb_inct_0, L to H

10

debug module interupt connected interupt

debug module interuptdebug module interup


connected interupt

11

Software Software Platform

Setting

12

Software PlatformOS and LibrariesDriversInterupt Handle

13

Software Platform Software Platform

processor parameters

extra compiler flag


BSP archiver compiler
BSP
50MHz
CORE_CLOCK_FREQ_Hz Current Value 50MHz
OS&Library settings OS
uclinux uclinux
OS uclinux

14

OS and Library

uclinux BSP FLASH MEMORY

Lmb memorydlmb_crtlr
Main memory bank0
Main memoryDDR_SDRAM_16M*16
Flash memory bank0
Flash memory16M*8

StdinRS232_DCE
StdoutRS232_DCE

15 DriversDrivers

16 OK
17 uclinux Microblaze
Microblaze BSP uclinux
EDK Software Generate BSP and Libraries
spartan_uclinux/
microblaze_0/ libsrc/ uclinux_v1_00_d auto-config.in

5.3.2 uCLinux
1
uClinux
bin

Linux embed Windows C


training package
uClinux

2
1.

VMWare VM Settings

Shared Folders
Windows training uClinux
C:\training\
/mnt/hgfs Linux /mnt/hgfs/training/
Windows

2.

Linux /home/embed microblaze-elf-tool

cd /home/embed
mkdir microblaze-elf-tools

cd /home/embed mkdir
microblaze-elf-tools

3.

Windows microblaze-elf-tools.tar.gz
/home/embed/microblaze-elf-tool)

Cp /mnt/hgfs/training/package/microblaze-elf-tools.tar.gz /home/embed/microblaze-elf-tool

cp /mnt/hgfs/training/package
microblaze-elf-tools.tar.gz /home/embed/microblaze-elf-tool.
4.

cd microblaze-elf-tool/
tar -zxf microblaze-elf-tools.tar.gz

tar -z gzip -x
-f
5.

.bash_profile
vi ../.bash_profile

vim

microblaze PATH
PATH=/home/embed/microblaze-elf-tools/bin:$PATH

6.

source ../.bash_profile

7.

exit

embed

8.

microblaze
mb-gcc v

microblaze
9.

uClinux uClinux
uClinux-dist-20060803.tar.bz2/home/embed
cp /mnt/hgfs/training/package/uClinux-dist-20060803.tar.bz2 /home/embed

uClinux
uClinux uClinux
www.uclinux.org/pub/uClinux/dist/
10. uClinux
cd /home/embed
tar jxf uClinux-dist-20060803.tar.bz2

-j bzip2
11. uClinux

cd uClinux-dist

12. uClinux
ls l

uClinux

5.3.3 EDK uClinux


1
uClinux xilinx
xmd Linux
Linux

2
1.

FPGA EDK
labs C\training\task4\labs\
EDK autoconfig.in

2.

autoconfig.in Linux
linux-2.4.x/arch/microblaze/platform/uclinux-auto
cd uClinux-dist
cp

/mnt/hgfs/training/task4/autoconfig.in

linux-2.4.x/arch/microblaze/platform/uclinux-auto

3.

autoconfig.in
vi linux-2.4.x/arch/microblaze/platform/uclinux-auto/autoconfig.in

vi vi
:set ff=unix


:wq

autoconfig.in
4.

make clean

5.

uClinux
make menuconfig

6.

Vendor/Product Selection
Vendor Xilinx Xilinx Product uclinux-auto

Exit Main Menu


7.

MainMenu Kernel/Library/Defaults Selection Kernel Version


linux-2.4.x Libc Version uClibc Customize
Kernel Settings Customize Vendor/User Settings

Exit Main Menu Main Menu

yes kernel
8.

kernel

9.

Main Menu Processor type and features


Processor type and features Console on
UARTLITE Ethernet driver Main Menu

10. Memory Technology DevicesMTD RAM/ROM/Flash


chip drivers

Support for Intel/Sharp flash chips Support for AMD/Fujitsu


flash chips

Memory Technology DevicesMTD Mapping drivers for


chip access

Mapping drivers for chip access Generic uClinux RAM/ROM


filesystem support uClinux RAM/ROM

Exit Main Menu


11. Main Menu Block devices Initial RAM disk(initrd)
support

Exit Main Menu


12. File Systems

/dev file system support EXPERIMENTAL


Automatically mount at boot Debug devfs

13.

yes
14. Vendor/user

15. core applications enable console shell


agetty

Exit Main Menu


16. Filesystem Applications flatfsd

Exit Main Menu


17. Network Applications dhcpcd-new

Exit Main Menu


18. BusyBox ping

Exit Main Menu


19. Main Menu

yes vendor/user
20. uClinux
make dep

make

21.
make


images image.bin image.bin
tftpboot uClinux

22. image.bin Windows EDK


C:\training\task4\labs\
23. EDK Download bitstream bitstream
FPGA

24. EDK debug xmd XMD dow data image.bin


0x22000000 0x22000000 DDR

25. con 0x22000000cpu uClinux

26. FPGA ip 192.168.0.75


ifconfig eth0 192.168.0.75

27. ip 192.168.0.72

ping

10

192.168.0.72

5.3.4 uClinux
1
uClinux

Linux .config

2
1.

make clean

2.

uClinux
make menuconfig

3.

Vendor/Product Selection
Vendor Xilinx Xilinx Product
uclinux-auto

Exit Main Menu


4.

MainMenu Kernel/Library/Defaults Selection


Kernel Version linux-2.4.x Libc Version uClibc
Customize Kernel Settings Customize Vendor/User Settings

Exit Main Menu Main Menu

yes kernel
5.

kernel Exit
yes

6.

vendor/user Miscellaneous Applications


mknod

zmodem utils lrzNEWlszNEW

Exit Main Menu


7.

Main Menu Exit

yes vendor/user
8.

uClinux
make dep

9.

make

images image.bin image.bin


tftpboot

10. images image.bin Windows EDK


C:\training\task4\labs\
11. EDK Device Configuration->Download Bitstream
bitstream FPGA

12. bitstream EDK debug xmd XMD


dow data image.bin 0x22000000 0x22000000 DDR

13. con 0x22000000cpu uClinux

14. uClinux /tmp zmodem

cd

/tmp

lrz

15. ->

readme.txt zmodem
16.

17.
cat readme.txt

readme.txt zmodem

5.3.5 uClinux
1
uClinux

2
1.

hellodrv.c linux-2.4.x/drivers/char
/home/embed/uClinux-dist
cp
cd

2.

/mnt/hgfs/training/task4/src/hellodrv.c

linux-2.4.x/drivers/char

linux-2.4.x/drivers/char

linux-2.4.x/drivers/char Config.in
tristate hello world driver CONFIG_DRIVER_HELLO


3.

Makefile
obj-$(CONFIG_DRIVER_HELLO) += hellodrv.o

hellodrv.o hellodrv.c hellodrv


4.

uClinux-dist
cd ../../../
make clean

5.

uClinux
make menuconfig

6.

Main Menu Kernel/Library/Defaults Selection


Kernel Version linux-2.4.x Libc Version uClibc
Customize Kernel Settings Customize Vendor/User Settings

Exit Main Menu Main Menu

yes kernel
7.

kernel

8.

Main Menu Character Devices Character Devices


Hello world driver M
module insmod
/rmmod

Exit Main Menu Main Menu


9.

vendor/user Main Menu Exit


vendor/user

10. uClinux
make dep

11.
make

12. images image.bin


Windows EDK linux-2.4.x/drivers/char
hellworld.o Windows EDK
13. EDK bistreamdebug xmd
XMD
dow data image.bin 0x22000000

0x22000000 DDR

14. con 0x22000000cpu uClinux

15. uClinux /tmp zmodem

cd
lrz

/tmp

16. ->

EDK hellodrv.o zmodem


17.

ls

zmodem
18. hellodrv
insmod ./hellodrv.o

19.
lsmod

5.3.6 uClinux
1
uClinux

2
1.

uClinux-dist user helloapp


cd /home/embed/uClinux-dist/user
mkdir helloapp

2.

helloapp.c Makefile helloapp


cp /mnt/hgfs/training/task4/src/helloapp.c
cp /mnt/hgfs//training/task4/src/Makefile

3.

helloapp/
helloapp/

/home/embed/uClinux-dist/user Makefile

dir-$(CONFIG_USER_HELLOAPP) += helloapp

4.

uClinux-dist/config config.in
cd

../config

vi

config.in

comment Miscellaneous Applications


bool hello application CONFIG_USER_HELLOAPP

5.

uClinux-dist
cd

../

make clean

6.

uClinux
make menuconfig

7.

Main Menu Kernel/Library/Defaults Selection


Kernel Version linux-2.4.x Libc Version uClibc
Customize Kernel Settings Customize Vendor/User Settings

Exit Main Menu Main Menu


8.

kernel Exit Main Menu


Main Menu

9.

vendor/user Miscellaneous Applications


hello applicationNEW

vendor/user
10. uClinux
make dep

11.
make

12. images image.bin


Windows EDK C:\training\task4\labs\
13. EDK bistreamdebug xmd
XMD dow data image.bin 0x22000000 0x22000000
DDR

14. con 0x22000000cpu uClinux

15. uClinux /bin

cd

/bin

ls

16. helloapp
helloapp

5.4
1. mb-gcc
A microblaze
echo $PATH

.bash.profile export PATH= .


2 uClinux ln 3.4.1/c++ file exists.
A include/Makefile ln
3
A
make mrproper -i
image.bin
Make mrproper .o
.config
4 uClinux agetty

A vendor/user core applications agetty


5 dhcpcd[33]: timed out waiting for a valid DHCP server response

A vendor/user Network Applications dhcpcd-new


2.0/2.4
6. xmd
A
EDK debug_module Interrupt
debug_module_Interrupt

opt_intc_0 Intr debug_module_Interrrupt

7. busybox

A make make mrproper

8. shutils
Amake cleanmake menuconfig
vendor/user Miscellaneous Applications shutils
Busybox
make dep;make


6.1
1.

Face
Dtection
FPGA
2.
Xilinx XUP Virtex-II Pro Development Board PPC405

6.2 6.3

1Xilinx XUP Virtex-II Pro Development Board


2266MHz256M
3
4
55V

Xilinx Platform Studio8.2.01


3.
/Chapter6/
/Doc
/Src

6.2 PowerPC
Xilinx XUP Virtex-II Pro Development Board MicroBlaze
PowerPC MicroBlaze
PowerPC PowerPC
6.1 PowerPC PowerPC
PLBProcess Local BusPLB2OPB PLB
OPB OPBOn-Chip
Peripheral Bus
PowerPC
PLB OPB
PLB BRAMUART

OPB Bus
PLB Bus

UART
GPIO

Switches

GPIO

Push

PLB2OPB
PPC
PLB BRAM Cntlr

PLB BRAM
MY IP

PLB BRAM Cntlr

PLB BRAM

Timer

INTC

6.1 PowerPC

1.

Xilinx_XUP_V2P X:\EDK\board\Xilinx\boards
X:\EDK EDK

2.

XPS 8.2i

6.2

3.

PowerPC

PowerPC
Base System Builder Wizard Ok
open a recent project

6.3

4.

6.4

5.

browse
system
Face_Detect

6.5

6.

OK

7.

I would like to creat a new design next

6.6

8.

Board Name
XUP Virtex-II Pro Development System 1

Board Vendor: Xilinx


Board Name: XUP Virtex-II Pro Development System
Board Revision: C
next

6.7

9.

XUP Virtex-II Pro MicroBlazee


PowerPC
PowerPC PowerPC
PowerPC PowerPC
Xilinx

6.8

10. PowerPC 300MHz


PowerPC 100MHz

Debug I/F FPGA JTAGOn chip memory 16K


Cache setup Enable next

6.9

11. RS232-Uart-1 115200

Enthernet-MAC Data
sheet

6.10

12.

6.11

13. Xilinx XUP Virtex-II Pro

256M
256M Xilinx XUP Virtex-II Pro
www.xilinx.com

6.12

14. PLB BRAM 16K


Add Peripheral OPB BRAMTIMER

6.13

15. Cache Cache


PowerPC Cache Cache
PLB BRAM

6.14

Cache

16. EDK

6.15

17.

6.16

18.

6.17

19.
PLB OPB
Generate

6.18

20. finish

6.19

21. Start Using Platform Studio

6.20

Platform Studio

22. Xilinx Platform Studio


ApplicationProjectIP Catalog IP

6.21

Xilinx Platform Studio

23. Hardware Generate Netlist

PowerPC

6.22

Netlist

24. Application TestApp_Memory Mark to Initialize the


BRAMs Bitsream

6.23

25. Device Configuration J Update Bitstream

6.24

Bitstream

26.

6.25

27.

6.26

28.

6.27

29.

6.28

30.

6.29

31. EDK Device Configueration Download


Bitstream Netlist

6.30

Bitstream

32. Bitsream

6.31

6.3

Adaboost OPENCV
OpenCV(Intel Open Source Computer Vision Library) Intel

3D
http://www.sourceforge.net Opencv
http://www.yahoogroups.com/group/OpenCV OpenCV
OpenCV
OpenCV

OpenCV
Windows Linux
1) C

2)
3)
4)
OPENCV
OPENCV
OPENCV PUBLIC LICENSE
OPENCV PC

1.

EDK SDK Software


Lauch Platform Studio SDK

6.32

2.

SDK

SDK Creat a new SDK C


Application Project

6.33

3.

Face Detect

6.34

4.

6.35

5.

ppc405_0

6.36

6.

SDK
Face Detect ppc405_0
SDK PowerPC

6.37 SDK

7.

X:\Face_Detect\SDK_projects\Face Detect
X: SDK
Face Detect Refresh SDK
X:\Face_Detect\SDK_projects

6.38

8.

SDK

main main
main.c

6.39

9.

Face_Detect.c main
main

detect_and_draw_objects( image, cascade, 1 )image


cascade
Adaboost

10. detect_and_draw_objects
cvCreateImage
cvHaarDetectObjects
1.3 cvRectangle

OPENCV OPENCV
11.
Face_Detect Properties

6.40

12.

6.41

13. Include Paths

../cxcore/include

6.41

14. ../cv/include../highgui

6.42

15. Miscellaneous

V2P_BUILD

6.43

16. Generate Linker Script


0x250000

6.44

17.
SDK elf

6.45

18. X:\Face_Detect\SDK_projects\Face Detect\Release


FaceDetect.elf X:\Face_Detect\
dat
X:\Face_Detect\
19. EDK XMD

6.46 XMD

20. ppc405_0

6.47

21.
:
dow -data pic.jpg.raw.big 0x0fe00000
dow -data cascade.raw.big 0x0ff00000
dow FaceDetect.elf

6.48

22. 352*288
factor
6446 53 53

6.49

6.4
PowerPC XUP
Virtex-II Pro board XPS
PowerPC
SDK elf

XMD
PowerPC Xilinx
FPGA

Mini VOS
Spartan 3E-Starter Kit WEB
WEB SERVER

7.1
Web
MP3
1.
VOS MINI VOS

2.
1)
FPGA Xilinx Spartan 3E-Starter Kit
RS232 RJ45
HUB
2)
EDK 8.2i 8.2.03i
Fedora Core 4 RedHat9 Linux
VMware 5.0.0 build-13124
3.
/Chapter7/

/Doc
/Src web LED
/Tools uClinux uclinux_v1_00_d

microblaze-elf-tools-20060213.tar.gz uClinux

uClinux-dist-20060803.tar.bz2

7.2 MicroBlaze

1. XPS 8.2i

MicroBlaze Base
System Builder Wizard OK
2. browse

system OK BSB
3. I would like to create a new design next

4.
Board Vendor: Xilinx
Board Name: Spartan 3E starter board
Board Revision: C
next

5. Spartan 3E MicroBlaze
MicroBlaze
next

6. MicroBlaze
50MHz MicroBlaze
66.67MHz
Debug I/F on-chip
H/W debug moduleLocal memory 8K Cache setup Enable
Cache link next

7. I/O I/O RS232DCE RS232DTE


115200
Data sheet data sheet next

8. I/O LED
LED8bit FLASH
next

9. Spartan3E 32M
DDR_SDRAM_16M*16
Ethernet_MAC next

10. Add
Peripherals OPB_TIMER OK

11. Timer Timer


next

12. cache
cache Cache
Cache 8K 2K ICache DCache next

13. RS232_DCE
MicroBalze
next

14.
bitstream
next

15.
next

16. MicroBlaze Generate

17. finish Start Using Platform Studio

18. Xilinx Platform Studio

19. Hardware Generate Netlist MicroBlaze

20. Application TestApp_Memory Mark to Initialize the


BRAMs bitstream

21. Device Configuration J Update Bitstream bit


22.

223.

24.
25.

26. EDK Device ConfigurationDownload Bitstream


Bitstream executable

27. Bitstream

7.3 EDK
1. MicroBlaze uClinux
uClinux uclinux_v1_00_d /EDK/sw/lib/bsp/

2. EDK MicroBlaze
system.xmp
3. MicroBlaze EDK
Bus interface MicroBlaze

4. port debug
module interrupt net debug module interrupt

5. port opb_inct_0 L to H

6.

7. debug module interrupt connected interrupt


debug module interruptdebug module interrupt
connected interrupt

8. Software Software Platform Setting

9.
Software PlatformOS and LibrariesDriversInterrupt Handle

10.
Software Platform Software Platform
processor parameters

extra compiler flag BSP


archiver compiler
BSP
50MHz CORE_CLOCK_FREQ_Hz
Current Value 50MHz OS&Library settings
OS uClinux
uClinux OS
uClinux

11. OS and Library


ucClinux BSP FLASH MEMORY

Lmb memorydlmb_crtlr
Main memory bank0
Main memoryDDR_SDRAM_16M*16
Flash memory bank0
Flash memory16M*8
StdinRS232_DCE

StdoutRS232_DCE

12. Drivers Interrupt Handle OK


uClinux MicroBlaze
MicroBlaze BSP uClinux
13. EDK Software Generate BSP and Libraries
MicroBlaze
/microblaze_0/ libsrc/ uclinux_v1_00_d auto-config.in

7.4 uClinux
linux uClinux
microblaze-elf-tools uClinux-dist
Windows D share
uClinux

7.4.1
windows linux
VMware VMware5 VMware
windows mount linux /mnt/hgfs/ windows
linux
1 VMWare VM Settings

2 Shared Folders
Windows share uClinux
D:\share/mnt/hgfs
Linux /mnt/hgfs/share/ Windows

hgfs share

7.4.2
1. root /home embed embed
microblaze-elf-tools
>cd

/home

>mkdir embed
>cd

embed

>mkdir microblaze-elf-tools
2 Windows microblaze-elf-tools-20060213.tar.gz
D:\share)

>cp

/mnt/hgfs/share/microblaze-elf-tools-20060213.tar.gz

/home/embed/microblaze-elf-tools
3
>tar -zxvf microblaze-elf-tools-20060213.tar.gz
4.bash_profile /root
>vi

~/.bash_profile

microblaze PATH
PATH=/home/embed/microblaze-elf-tools/bin:$PATH

5
>source ~/.bash_profile

>echo $PATH
6 MicroBlaze
>mb-gcc v

MicroBlaze
7 uClinux uClinux
uClinux-dist-20060803.tar.bz2/home/embed
>cp

/mnt/hgfs/share/uClinux-dist-20060803.tar.bz2

/home/embed

/home/embed uClinux
>cd

/home/embed

>tar jxvf uClinux-dist-20060803.tar.bz2

uClinux
>cd

uClinux-dist

uClinux
>ls l

uClinux

7.5 EDK uClinux


28. EDK autoconfig.in 7.3 Linux
linux-2.4.x/arch/microblaze/platform/uclinux-auto
>cd

uClinux-dist

>cp

/mnt/hgfs/share/autoconfig.in

linux-2.4.x/arch/microblaze/platform/uclinux-auto
29. autoconfig.in
>vi

linux-2.4.x/arch/microblaze/platform/uclinux-auto/autoconfig.in

vi vi
:set ff=unix

ESCwq
autoconfig.in
30.
>make clean
31. uClinux
>make menuconfig

32. Vendor/Product Selection Vendor Xilinx Xilinx Product


uclinux-auto

Exit Main Menu


33. MainMenu Kernel/Library/Defaults Selection
Kernel Version linux-2.4.x Libc Version uClibc
Customize Kernel Settings Customize Vendor/User Settings

Exit Main Menu Main Menu

yes kernel
34. kernel

35. Main Menu Processor type and features Processor type and
features Console on UARTLITE Ethernet driver Main
Menu

36. Memory Technology DevicesMTD RAM/ROM/Flash


chip drivers

Support for Intel/Sharp flash chips Support for AMD/Fujitsu


flash chips

Memory Technology DevicesMTD Mapping drivers for


chip access

Mapping drivers for chip access Generic uClinux RAM/ROM


filesystem support

Exit Main Menu


37. Main Menu Block devices Initial RAM disk(initrd)
support

Exit Main Menu


38. File Systems

/dev file system supportEXPERIMENTALAutomatically


mount at boot Debug devfs
39.

yes
40. Vendor/user

41. core applications enable console shell


agetty

Exit Main Menu


42. Filesystem Applications flatfsd

Exit Main Menu


43. Network Applications dhcpcd-new

Exit Main Menu


44. BusyBox ping

Exit Main Menu


45. Main Menu

yes vendor/user
46. uClinux
>make dep
47.
>make
images image.bin
48. image.bin Windows EDK
22. EDK Download bitstream bitstream
FPGA
23. EDK debug xmd XMD
>dow data image.bin 0x22000000
0x22000000 DDR

24.
>con 0x22000000
cpu uClinux

7.6 LED VOS


1/home/embed/uClinux-dist/linux-2.4.x /drivers
LED drivers char

>cd

/home/embed/uClinux-dist/linux-2.4.x/ddrivers/char

2 vim ,
/chapter7/Src/ xup_spartan3e_led.c xup_spartan3e_led.c

>vim xup_spartan3e_led.c

#include <linux/module.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/fs.h>
static int led_major;
static struct file_operations fop_devicename =
{
// fops
};

static int __init led_init(void)


{
led_major=register_chrdev//);
if (led_major<0)
{
printk(KERN_ALERT "LED initial failed!/n");
return -1;
}
printk(KERN_ALERT "The LED major number is %d\n",//);
return 0;
}
static void __exit led_exit(void)
{
int led_unreg = unregister_chrdev(led_major,"LED_TEST_1");
if (led_unreg<0)
printk(KERN_ALERT "Error in unregister device:%d\n",//);
}

//
//

3.
4. ESC insert wq
5. xup_spartan3e_led.c
>ls xup_spartan3e_led.*
6. web server
/chapter7/Src/src D:\share\ VMware
/chapter7/Src/src /home/embed/uClinux-dist/user/ping

>cp -r /mnt/hgfs/share/src

/home/embed/uClinux-dist/user/ping

7. /home/embed/uClinux-dist/linux-2.4.x/driver/char Config.in

tristate LED CONFIG_DRIVER_LED


8. /home/embed/uClinux-dist/linux-2.4.x/driver/char Makefile

obj -$(CONFIG_DRIVER_LED) +=xup_spartan3e_led.o

9. uClinux-dist
10.
>make clean

11.
>make menuconfig
12 7.5 uClinux
7.5 891011 Kernel Setting

Character devices

13 M

14 vendor/user 7.5 14151617


Miscellaneous Applications mknod

zmodem utils lrzNEWlszNEW

Exit Main Menu


15
>make dep
16
>make

18 Linux
image.bin xup_spartan3e_led.o EDK
7.5 image.bin

19

20. EDK Bitstream


XMD dow data image.bin 0x22000000 image.bin
XMD con 0x22000000
21. uClinux /tmp zmodem

>cd

/tmp

>lrz
22. ->
xup_spartan3e_led.o zmodem


>ls
23. xup_spartan3e_led
>insmod ./ xup_spartan3e_led.o

>ls
xup_spartan3e_led.o Spartan 3E
LED LED
24. FPGA IP IP FPGA IP
IP 192.168.238.4 FPGA
192.168.238.8

>ifconfig eth0 192.168.238.8


25. pc web
http://192.168.238.8/home/index.htm

xup_spartan3e_led.c
#include <linux/module.h>
#include <asm/io.h>
#include <linux/poll.h>

#include <linux/init.h>
#include <linux/ioctl.h>
#include <asm/semaphore.h>//struct semaphore
#include <linux/timer.h>//timer_list
//#include <linux/wait.h>//wait_event_interruptible_timeout
//#include <linux/sched.h>//schedule_timeout
#define XUP_SPARTAN3E_LED_MAJOR

222

#define XUP_SPARTAN3E_PLAY_MAJOR

223

#define DATA_REG_ADDR

0x40000000

#define DIRC_REG_ADDR

0x40000004

#define OutMem(OutAddr, Value)

(*(volatile u32 *)((OutAddr)) = (Value))

#define InMem(InputAddr)

(*(volatile u32 *)(InputAddr))

#define DELAY

(HZ>>3)

#define INITIAL_COUNT

40

#define XUP_SPARTAN3E_LED_IOC_MAGIC

'x'

#define XUP_SPARTAN3E_LED_MAX_NUM

#define XUP_SPARTAN3E_LED_SET_DIR
_IOWR(XUP_SPARTAN3E_LED_IOC_MAGIC, 0, u32) //ioctl
#define XUP_SPARTAN3E_LED_SET_REV
_IOWR(XUP_SPARTAN3E_LED_IOC_MAGIC, 1, u32) //ioctl
static int initial_count;
static unsigned char led_state;
static struct semaphore sem;

/* mutual exclusion semaphore

static struct timer_list refresh_timer;


static void refresh(unsigned long ptr)
{
if (refresh_timer.data == 1)
{
if (initial_count < INITIAL_COUNT)
{
if (led_state|0x0)

*/

led_state <<= 1;
else
led_state = 1;
initial_count = initial_count + 1;
}
else if (initial_count < INITIAL_COUNT*2 && initial_count >= INITIAL_COUNT)
{
if (led_state != 0x01)
led_state >>= 1;
else
led_state = 0x80;
initial_count = initial_count + 1;
}
else
{
if (led_state == 0x0)
led_state = 0xff;
else if (led_state == 0xff)
led_state = 0x0;
else
led_state=0x0;
}
OutMem(DATA_REG_ADDR, led_state);
refresh_timer.expires = jiffies + DELAY;
add_timer(&refresh_timer);
}
else if (refresh_timer.data == 2)
{
OutMem(DATA_REG_ADDR, led_state);
refresh_timer.expires = jiffies + DELAY>>2;
add_timer(&refresh_timer);

}
else {}
}
static int xled_open(struct inode * inode, struct file * file)
{
MOD_INC_USE_COUNT;
//printk("XUP_SPARTAN3E_LED open: Usage = %d\n", MOD_IN_USE);
return 0;
}
static int xled_release(struct inode * inode, struct file * file)
{
MOD_DEC_USE_COUNT;
//printk("XUP_SPARTAN3E_LED release: Usage = %d\n", MOD_IN_USE);
return 0;
}
static ssize_t xled_read(struct file *file, char *buffer, size_t count, loff_t *ppos)
{
down(&sem);
//led_state = inb(INPORT);
//OutMem(DIRC_REG_ADDR, 0xFFFFFFFF);//set direction
//barrier();
//led_state = InMem(DATA_REG_ADDR);
//printk("data = %x hex\n", led_state);
if(copy_to_user( buffer, &led_state, 1))
{
printk("Read Data to user error\n");
up(&sem);
return -EFAULT;
}
up(&sem);
return 1;

// for debugging only

}
static ssize_t xled_write(struct file *file, const char *buf, size_t count, loff_t *ppos)
{
down(&sem);
refresh_timer.data = 0;
if (copy_from_user(&led_state, __user (u8 *)buf, 1))
//int ret = get_user(led_state,buf);
//if (ret != 0)
{
printk("Write Data from user error\n");
up(&sem);
return -EFAULT;
}
printk("Write Data from user %x\n", led_state);
up(&sem);
//outb(data, OUTPORT);
if (led_state == 0xAA)
{
refresh_timer.data = 1;
refresh(0);
}
else
{
refresh_timer.data = 2;
refresh(0);
}
return 1;
}
static int xled_ioctl(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg)
{
if (MINOR(inode->i_rdev) >= XUP_SPARTAN3E_LED_MAX_NUM)

return -ENODEV;
if (_IOC_TYPE(cmd) != XUP_SPARTAN3E_LED_IOC_MAGIC)
return -ENOTTY;
switch (cmd)
{
case XUP_SPARTAN3E_LED_SET_DIR:
OutMem(DIRC_REG_ADDR, arg);
printk("Set XUP_SPARTAN3E_LED direct %ld\n", arg);
break;
case XUP_SPARTAN3E_LED_SET_REV:
;
break;
default:
return -ENOTTY;
}
return 0;
}

static ssize_t play_read(struct file *file, char *buffer, size_t count, loff_t *ppos)
{
down(&sem);
//led_state = inb(INPORT);
//OutMem(DIRC_REG_ADDR, 0xFFFFFFFF);//set direction
//barrier();
//led_state = InMem(DATA_REG_ADDR);
//printk("data = %x hex\n", led_state);
if(copy_to_user( buffer, &led_state, 1))
{
printk("Read Data to user error\n");
up(&sem);
return -EFAULT;

// for debugging only

}
up(&sem);
return 1;
}
static ssize_t play_write(struct file *file, const char *buf, size_t count, loff_t *ppos)
{
down(&sem);
refresh_timer.data = 0;
if (copy_from_user(&led_state, __user (u8 *)buf, 1))
//int ret = get_user(led_state,buf);
//if (ret != 0)
//if (copy_from_user(&led_state, __user (u8 *)buf, count))
{
printk("Write Data from user error\n");
up(&sem);
return -EFAULT;
}
printk("Write Data from user %x\n", led_state);
//outb(data, OUTPORT);
OutMem(DATA_REG_ADDR, led_state);
up(&sem);
return 1;
}
struct file_operations play_fops = {
owner:

THIS_MODULE,

open:

xled_open,

release: xled_release,
read:

play_read,

write:

play_write,

ioctl:

xled_ioctl,

};

struct file_operations xled_fops = {


owner:

THIS_MODULE,

open:

xled_open,

release: xled_release,
read:

xled_read,

write:

xled_write,

ioctl:

xled_ioctl,

};
int __init xled_init (void)
{
if
(register_chrdev(XUP_SPARTAN3E_LED_MAJOR,"XUP_SPARTAN3E_LED",&xled_fops))
{
printk("XUP_SPARTAN3E_LED: Failed to get major %d\n",
XUP_SPARTAN3E_LED_MAJOR);
return -EIO;
}

if
(register_chrdev(XUP_SPARTAN3E_PLAY_MAJOR,"XUP_SPARTAN3E_PLAY",&play_fops
))
{
printk("XUP_SPARTAN3E_PLAY: Failed to get major %d\n",
XUP_SPARTAN3E_PLAY_MAJOR);
return -EIO;
}
initial_count = 0;
init_MUTEX(&sem);
init_timer(&refresh_timer);
refresh_timer.function = refresh;
refresh_timer.data = 1;
refresh_timer.expires = jiffies + DELAY;

add_timer(&refresh_timer);
printk("Registered device XUP_SPARTAN3E_LED: major
%d\n",XUP_SPARTAN3E_LED_MAJOR);
printk("Registered device XUP_SPARTAN3E_PLAY: major
%d\n",XUP_SPARTAN3E_PLAY_MAJOR);
return 0;
}
static void __exit xled_cleanup (void)
{
printk("Freed resources: MOD_IN_USE = %d\n", MOD_IN_USE);
unregister_chrdev(XUP_SPARTAN3E_LED_MAJOR,"XUP_SPARTAN3E_LED");
unregister_chrdev(XUP_SPARTAN3E_PLAY_MAJOR,"XUP_SPARTAN3E_PLAY");
del_timer(&refresh_timer);
printk("Unregistered device XUP_SPARTAN3E_LED: major
%d\n",XUP_SPARTAN3E_LED_MAJOR);
printk("Unregistered device XUP_SPARTAN3E_PLAY: major
%d\n",XUP_SPARTAN3E_PLAY_MAJOR);
}

module_init(xled_init);
module_exit(xled_cleanup);
MODULE_LICENSE("GPL");
EXPORT_NO_SYMBOLS;


8.1
Web
fast-order
solution & service

1.
V2PRO WEB WEB
SERVER

2.
1)
FPGA XUP V2PRO BOARD
RS232 RJ45
HUB
2)
EDK 8.2i 8.2.03i
Fedora Core 4 RedHat9 Linux
VMware 5.0.0 build-13124
3.
/Chapter8/
/Doc
/Src web LEDDIP
/Tools uClinux uclinux_v1_00_d

microblaze-elf-tools-20060213.tar.gz uClinux

uClinux-dist-20060803.tar.bz2

8.2 MicroBlaze
1. XPS 8.2i

Base System Builder Wizard MicroBlaze OK

2. browse

system OK BSB
3. I would like to creat a new design next
4.
Board Vendor: Xilinx
Board Name: XUP Virtex-II Pro Development System
Board Revision: C
next

Board Name XUP Virtex-II Pro


Xilinx_XUP_V2P EDK
board>Xilinx>boards
5. MicroBlaze next

6. MicroBlaze No Cache
DDR 512MB next

7. I/O RS232
115200 next

8. I/O next

9. Add Periperals
OPB_TIMER OK

10. Timer Timer


next

11. Software Setup Memory Test Peripheral


selftest

12. Generate

13. finish Start using Platform Studio

14. Xilinx Platform Studio

8.3 EDK
1. MicroBlaze uClinux
uClinux uclinux_v1_00_d EDK->sw->lib->bsp

2. EDK MicroBlaze
system.xmp
3. MicroBlaze EDK
Bus interface MicroBlaze

4. port debug
module interrupt net debug module interrupt

5. port opb_inct_0 L to H

6.

7. debug module interrupt connected interrupt


debug module interruptdebug module interrupt
connected interrupt

9. Software Software Platform Setting

10.
Software PlatformOS and LibrariesDriversInterrupt Handle

11. Software Platform Software Platform


OS&Library settings OS
uClinux uClinux
OS uClinux

12. OS and Library


uClinux
BSP FLASH MEMORY

Main memory bank0


Main memoryDDR_512M_64M*64
StdinRS232_Uart_1
StdoutRS232_Uart_1

13. Drivers Interrupt Handle OK


uClinux MicroBlaze
MicroBlaze BSP uClinux
14. EDK Device Configuration Update BitstreamXPS

MicroBlaze microblaze_0/ libsrc/ uclinux_v1_00_d


auto-config.in

8.4 uClinux
linux uClinux
microblaze-elf-tools uClinux-dist
Windows D share
uClinux

8.4.1
windows linux
VMware VMware5 VMware
windows mount linux /mnt/hgfs/ windows
linux
1 VMWare VM Settings

2 Shared Folders
Windows share uClinux
D:\share/mnt/hgfs

Linux /mnt/hgfs/share/ Windows

hgfs share

8.4.2
1. root /home embed embed
microblaze-elf-tools
>cd

/home

>mkdir embed
>cd

embed

>mkdir microblaze-elf-tools
2 Windows microblaze-elf-tools-20060213.tar.gz
D:\share)
>cp

/mnt/hgfs/share/microblaze-elf-tools-20060213.tar.gz

/home/embed/microblaze-elf-tools
3
>tar -zxvf microblaze-elf-tools-20060213.tar.gz
4.bash_profile /root
>vi

~/.bash_profile

microblaze PATH
PATH=/home/embed/microblaze-elf-tools/bin:$PATH

5
>source ~/.bash_profile

>echo $PATH
6 MicroBlaze
>mb-gcc v

MicroBlaze
7. uClinux uClinux
uClinux-dist-20060803.tar.bz2/home/embed
>cp

/mnt/hgfs/share/uClinux-dist-20060803.tar.bz2

/home/embed

/home/embed uClinux
>cd

/home/embed

>tar jxvf uClinux-dist-20060803.tar.bz2


uClinux
>cd

uClinux-dist

uClinux
>ls l

uClinux

8.5 uClinux
1 FPGA \microblaze_0\libsrc\uclinux_v1_00_d \autoconfig.in
uClinux-dist linux-2.4.x/arch/microblaze/platform/uclinux-auto

>cd

uClinux-dist

>cp

/mnt/hgfs/share/autoconfig.in

linux-2.4.x/arch/microblaze/platform/uclinux-auto
2 autoconfig.in
>vi linux-2.4.x/arch/microblaze/platform/uclinux-auto/autoconfig.in
vi vi
>:set ff=unix


>:wq
autoconfig.in
3
/Chapter8/Src/ xup_v2pro_led.c xup_v2pro_dip.c
linux-2.4.x/drivers/char
4linux-2.4.x/drivers/char Config.in

tristate LED CONFIG_DRIVER_LED


tristate DIP CONFIG_DRIVER_DIP

5.linux-2.4.x/drivers/char Makefile

obj-$(CONFIG_DRIVER_DIP) += xup_v2pro_dip.o
obj-$(CONFIG_DRIVER_LED) += xup_v2pro_led.o

6 uClinux-dist
>pwd
7
>make mrproper i

8 uClinux
>make menuconfig

9 Vendor/Product Selection Vendor Xilinx Xilinx Product

uclinux-auto

Exit Main Menu


10 MainMenu Kernel/Library/Defaults Selection
Kernel Version linux-2.4.x Libc Version uClibc
Customize Kernel Settings Customize Vendor/User Settings

Exit Main Menu Main Menu

yes kernel
11LED DIP m module
LED DIP

12 kernel

15 Main Menu Processor type and features Processor


type and features Console on UARTLITE Ethernet driver
Main Menu

16 Memory Technology DevicesMTD RAM/ROM/Flash


chip
drivers

Detect flash chips by Common Flash Interface(CFI) probe Detect


JEDEC JESD21c compatible flash chips

17 Memory Technology DevicesMTD Mapping drivers


for chip access
Mapping drivers for chip access Generic uClinux RAM/ROM
filesystem support

Exit Main Menu


18 Main Menu Block devices Initial RAM disk(initrd)
support

Exit Main Menu


19 File Systems

/dev file system supportEXPERIMENTALAutomatically


mount at boot Debug devfs
20 Main Menu Character Devices Character Devices
LED DIP M
module insmod /rmmod

21

yes

22

Vendor/user

23

core applications enable console shell

agetty


Exit Main Menu
24

Filesystem Applications flatfsd

Exit Main Menu

Network Applications dhcpcd-new

Exit Main Menu


25

BusyBox ping httpd

Exit Main Menu

26

Miscellaneous Applications mknod

zmodem utils lrz NEW lsz NEW

Exit Main Menu


27

Main Menu

yes vendor/user
28

uClinux

>make dep
29

>make
images image.bin

8.6
1 /Chapter8/Src/httpd uClinux
vendors/Xilinx/uclinux-auto/httpd
> cp fr /mnt/hgfs/Data/.httpd /home/uClinux-dist/ vendors/Xilinx/uclinux-auto/
HTML JAVA

2 uClinux Program cgi


/Chapter8/Src/source getInfo.c, ledctl.c, priority.c Program

3 Makefile
/Source
ifndef ROOTDIR
ROOTDIR = /home/uClinux-dist ucLinux
endif
UCLINUX_BUILD_USER = 1
include $(ROOTDIR)/.config
LINUXDIR = linux-2.4.x
LINUX_CONFIG = $(ROOTDIR)/$(LINUXDIR)/.config
include $(LINUX_CONFIG)
LIBCDIR = $(CONFIG_LIBCDIR)
include $(ROOTDIR)/config.arch
LDFLAGS = -Wl -elf2flt
PATH:=$(ROOTDIR)/tools:$(PATH)
EXEC = Priority.cgi
EXEC_OBJS = Priority.o
all: $(EXEC)
$(EXEC): $(EXEC_OBJS)
$(CC) $(LDFLAGS) -o $@ $(EXEC_OBJS) $(LDLIBS)
clean:
-rm -f $(EXEC) *.elf *.gdb *.o
%.o: %.c
$(CC) -c $(CFLAGS) -I $(LINUXDIR)/include -o $@ $<
4 Program make Priority.cgi
5 Makefile
EXEC = ledctl.cgi
EXEC_OBJS = ledctl.o
make ledctl.cgi
6 Makefile
EXEC = getInfo.cgi

EXEC_OBJS = getInfo.o
make getInfo.cgi
7 cgi vendors/Xilinx/uclinux-auto/httpd
8 8.5 linux-2.4.x/drivers/char xup_v2pro_led.o
xup_v2pro_dip.o vendors/Xilinx/uclinux-auto/httpd
9 8.5 6 , image.bin

8.7
1 image.bin xup_v2pro_led.o xup_v2pro_dip.o EDK

2 FPGA PC
( HUB )

3>>>>

4 EDK Download bitstream bitstream FPGA

5 EDK debug -> launch xmd XMD :


>dow data image.bin 0x30000000
0x30000000 DDR

6 con 0x30000000cpu uClinux


>con 0x30000000

7 uClinux /tmp zmodem

>cd

/tmp

>lrz(.o lrz )
8 ->
xup_v2pro_led.o xup_v2pro_dip.o zmodem


>ls
xup_v2pro_led.o xup_v2pro_dip.o
9
>cd /
>mkdir /tmp/httpd
>cp /home/httpd/*.*

/tmp/httpd/

>chmod 644 /tmp/httpd/*.*


>chmod 755 /tmp/httpd/*.cgi
>thttpd d /tmp/httpd c *.cgi &
>ps( thttpd )

>kill 80( thttpd )


10.
>cd /tmp/httpd

>insmod xup_v2pro_led.o
>insmod xup_v2pro_dip.o
LED LED
DIP DIP
11 FPGA IP IP FPGA IP
IP 192.168.238.4 FPGA
192.168.238.8

>ifconfig eth0 192.168.238.8


12 http://192.168.238.8/home.html
LED DIP
Java