ENGINEERING
7TH SEMESTER (2016-17)
EXPERMINET NO- 4
AIM:
To study the operational features of resistance and resistance capacitance gate triggering
circuits for Thyristor.
OBJECTIVE:
To study the operational features of resistance and resistance capacitance gate triggering
circuits for thyristor.
APPARATUS REQUIRED:
Serial no
1
2
3
4
CIRCUIT DIAGRAM:
R TRIGGERING:
Equipments used
Thyristor inbuilt kit
(PECI4M121)
DMM
CRO
Patch Cords
Specifications
R,RC triggering circuit
inbuilt
AC/DC voltage/current
measurements
Monitoring device
Connecting medium
Quanity
1
1
1
3
THEORY:
Resistance triggering circuits are most economical and simplest but the triggering angle in this circuit cant
be achieved beyond 90 and this is the main disadvantage of this circuit. Resistance triggering circuit is
shown in the fig: 1. In this circuit R2 is variable resistance and R is stabilizing resistance. In case R2 is zero,
gate current may flow from source, through load, R1, D and gate to cathode. This current should not turn
on the thyristor unnecessarily, so it should not exceed maximum permissible gate current Igm. So, R1
needs to obey the following relation,
(Vm/R1)Igm or
R1 (Vm/Igm)
Where,
Vm maximum value of source voltage.
Igm maximum permissible gate current.
Resistance R should have such a value that maximum voltage drop across it does not exceed maximum
possible gate voltage Vgm. Now, when R2=0, following relation should be maintained,
{Vm/ (R1+R)} .R} Vgm or
R ( Vgm.R1)/ (Vm-Vgm)
The value of the resistances R1 and R2 are large and so gate trigger circuit draws a small current. Diode D
allows the flow of current during positive half cycle so, gate voltage Vg is a half wave dc pulse. Magnitude of
this pulse can be controlled by varying the value of R2.
Mathematical relationship:
When the thyristor is triggered at , the following relation will exist,
-1
Vgp. Sin = Vgt or, =Sin (Vgt/Vgp)
-1
So, = Sin (Vgt.(R1+R2+R)/ Vs().R)
Now, we can say from the above equation that if we increase the value of variable resistance we will be able to
increase the value of .
When R2 is kept in its highest position current i is small and voltage across R, i.e. Vg=i.R is also small
as shown in the fig: 1(a), which is not sufficient to turn on the thyristor that means Vgp (peak of gate
voltage Vg) is less than Vgt(minimum gate trigger voltage), so thyristor will not turn on. Therefore load
voltage and current are zero and supply voltage Vs appears as VT across the thyristor. This is a purely
resistive circuit so Vg is always in phase with Vs.
2> When thyristor is triggered at triggering angle = 90: To trigger the thyristor at 90 angle, R2 is
adjusted such that Vgp=Vgt. This gives the firing angle 90 as shown in the fig: 1(b). The output current
and voltage waveforms will be in same phase due to the purely resistive circuit.
3> When thyristor is triggered at triggering angle < 90: To trigger the thyristor at < 90 angle Vgp should
be greater than Vgt. As soon as Vg becomes equal to Vgt for the first time thyristor is turned on and Vg
is reduced to almost zero (about 1v). The waveforms for this stage are shown in the following fig.
RC TRIGGERING:
THEORY:
In RC triggering circuit by varying the resistance R, firing angle can be controlled from 0 to 180. In the negative half
cycle, capacitor C charges through D2 with lower plate positive to the peak supply voltage Vm at wt=-90. After
wt=90, source voltage Vs decreases from - Vm at wt= - 90 to zero at wt=0. During this period, capacitor voltage Vc
may fall from Vm at wt=-90 to some lower value oa at wt=0 as shown in the fig:2. Now as SCR anode voltage
passes through zero and becomes positive, C begins to charge through variable resistance R from the initial voltage
oa. When capacitor charges to positive voltage equal to gate trigger voltage Vgt ,SCR is fired and after this, capacitor
holds to a small positive voltage, diode D1 is used to prevent the breakdown of cathode to gate junction through D2
during negative half cycle. From the fig we can examine that firing angle can never be zero and 180.
In the range of power frequencies, it may be empirically shown that RC for zero output voltage is given by,
RC (1.3T/2)=4/w (approx)
Where T=1/f= period of ac line frequency in seconds.
The SCR will trigger when Vc=Vgt+Vd, where Vd is the voltage drop across diode D1.At the instant of triggering, if Vc is
assumed constant, the current Igt must be supplied by voltage source through R, D1 and gate to cathode circuit. Hence
maximum value of R is given by,
Vs >= RIgt+Vc
Vs >= RIgt+Vgt+Vd
OBSERVATION TABLE:
R TRIGGERING:
Firing angle
a in degrees
Vdc measured
from the CRO in
volts
Variable resistance
( R2) R in ohms
Remarks
=0
R1
=1<90
R2>R1
Observed
(draw)
=2> 1
R3>R2
Observed
(draw)
=3> 2
R4>R3
Observed
(draw)
=90
R5>R4
Observed
(draw)
>90
R6>R5
No waveform observed.
RC TRIGGERING:
Firing angle
a in degrees
=0
Vdc measured
from the CRO in
volts
Variable
resistance R in
ohms
R1
Remarks
R2>R1
Observed
(draw)
2> 1
R3>R2
Observed
(draw)
3> 2
R4>R3
Observed
(draw)
4> 3
R5>R4
Observed
(draw)
increases.
R6>R5
No waveform observed.
CONCLUSION:
PRECAUTIONS:
Practical waveforms from CRO: