Schematic of n-Channel
Enhancement Mode MOSFET
Cut-off
Before electron
inversion layer is
formed
After electron
inversion layer is
formed
Voltage between
drain and source
Threshold voltage for
an n-ch MOSFET
Voltage between
gate and source
Conduction parameter for an n-ch MOSFET
p-Channel Enhancement-Mode
MOSFET
Symbols
OFF state
ON state
Symbols
Nonsaturation vDS<vDS(sat)
2
2
]
iD Kn[2(vGS VTN)vDS vDS
] iD Kp[2(vSG VTP)vSD vSD
Saturation
vDS>vDS(sat)
i D K n [vGS VTN ]2
vSD>vSD(sat)
iD K p [vSG VTP ]2
Transition Pt.
Enhancement
Mode
VTN > 0V
VTP < 0V
Depletion
Mode
VTN < 0V
VTP > 0V
Conduction Parameters
Mobility
N-MOSFET
P-MOSFET
MOSFET width
W nCox
' W
kn
Kn
L
L
Kp
W p Cox
L
Channel length
W
k
L
'
p
ox
DC equivalent circuit
DC Load Line
Q-point near the middle
of the saturation region
for maximum symmetrical
output voltage swing,.
Transfer Characteristics
VGS vs ID
gm
iD
vGS
id
v gs
g m 2 K n (VGSQ VTN ) 2 K n I DQ
ro ( viDSD ) 1
ro [K n (VGSQ VTN ) 2 ]1 [I DQ ]1
Phasor components
AC equivalent circuit
Av Vo Vi g m (ro RD )
Common-Source Configuration
DC analysis:
Coupling capacitor is assumed
to be open.
Output
Input
AC analysis:
Coupling capacitor is assumed
to be a short. DC voltage
supply is set to zero volts.
Ri
Av Vo Vi g m (ro RD )(
)
Ri RSi
W p Cox
L
W
k
L
'
p
Note: Vsg and p are considered for PMOS, and Vgs and n for NMOS
transistor based circuits.
Problem-Solving Technique:
NMOSFET DC Analysis
1. Assume the transistor is in saturation.
a. VGS > VTN, ID > 0, & VDS VDS(sat)
2. Analyze circuit using saturation I-V relations.
3. Evaluate resulting bias condition of transistor.
a. If VGS < VTN, transistor is likely in cutoff
b. If VDS < VDS(sat), transistor is likely in
nonsaturation region
4. If initial assumption is proven incorrect, make
new assumption and repeat Steps 2 and 3.
Problem-Solving Technique:
MOSFET AC Analysis
1. Analyze circuit with only the dc sources to
find quiescent solution. Transistor must be
biased in saturation region for linear
amplifier.
2. Replace elements with small-signal model.
3. Analyze small-signal equivalent circuit,
setting dc sources to zero, to produce the
circuit to the time-varying input signals only.
MOSFET Part 2
Common
Source
Common
drain/ Source
Follower
Common
Gate
Voltage
Gain
Av > 1
Av 1
Av > 1
Current
Gain
__
__
Ai 1
Input
Output
Resistance Resistance
RTH
RTH
Low
Moderate
to high
Low
Moderate
to high
NMOS Source-Follower
or Common Drain Amplifier
RS ro
Ri
Av
(
)
1
RS ro Ri RSi
gm
1
RO
RS ro
gm
Common-Gate Circuit
Av
g m ( RD RL )
1 g m RSi
IO
g m RSi
RD
)(
)
Ai
(
Ii
RD RL 1 g m RSi
Common-source
(provides voltage gain)
Source follower
(for increased output current drive ability)
Adequate negative
gate voltage
(pinch off)
JFET symbol
N-channel JFET
P-channel JFET
JFET characteristics
JFET characteristics
N-channel JFET
P-channel JFET
Pinch-off voltage
JFET characteristics
N-Channel MESFET
(Metal Semiconductor Field Effect
Transistor)
Kn = 1mA/V2
VTN = 1V
ML is always in
saturation.
MD can be biased
either in saturation or
nonsaturation region.
vI > VTN
CMOS Inverter
V1 (V)
V2 (V) VO (V)
High
Low
Low
Low
Current Mirrors