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# Lab 7: 4 bit ripple adder

## 13ECE039 AND 13ECE048

November 14, 2016

Objective

To design a circuit for 4 bit ripple adder circuit using cmos logic in cadence software. Design the schematic and layout for the same and verify the result.

Theory

To design a 4 bit adder circuit we start by designing the 1 bit full adder then connecting
the four 1 bit full adders to get the 4 bit adder.
For the 1 bit full adder, the design begins by drawing the Truth Table for the three input
and the corresponding output SUM and CARRY. In a 4 bit adder circuit, 3 bits are added
at a time sequentially.A full adder is a combinational circuit that performs the arithmetic
sum of three input bits: augends A, addend B and carry from the previous adder. Its
results contain the sum S and the carry out, to the next stage.
A= A3 A2 A1 A0
B= B3 B2 B1 B0
For example:
A= 1 0 1 1 +
B= 1 1 0 1

A+B= 1 1 0 0 0 = Cout S3 S2 S1 S0

## Figure-1: 1-BIT FULL ADDER :

Multiple full adder circuits can be cascaded in parallel to add an N-bit number. For an Nbit parallel adder, there must be N number of full adder circuits. A ripple carry adder is a
logic circuit in which the carry-out of each full adder is the carry in of the succeeding next
most significant full adder. It is called a ripple carry adder because each carry bit gets
rippled into the next stage. In a ripple carry adder the sum and carry out bits of any half
adder stage is not valid until the carry in of that stage occurs.Propagation delays inside
the logic circuitry is the reason behind this. Propagation delay is time elapsed between the
application of an input and occurrence of the corresponding output. Consider a NOT gate,
When the input is 0 the output will be 1 and vice versa. The time taken for the NOT
gates output to become 0 after the application of logic 1 to the NOT gates input
is the propagation delay here. Similarly the carry propagation delay is the time elapsed
between the application of the carry in signal and the occurrence of the carry out (Cout)
signal. Circuit diagram of a 4-bit ripple carry adder is shown below.In simple words, the
final result of the ripple carry adder is valid only after the joint propogation delays of all
2

RESULTS

NAND schematic

NAND symbol:

NAND layout:

SCHEMATIC

RISE TIME

FALL TIME

S1

62.2 *1012

62.2 *1012

S2

67.95 *1012

67.95 *1012

S3

62.4 *1012

62.4 *1012

S4

63.79 *1012

63.79 *1012

Cout

655.1 *1012

655.1 *1012

SCHEMATIC

RISE TIME

FALL TIME

S1

3.19 *1012

3.19 *1012

S2

3.14 *1012

3.14 *1012

S3

3.16 *1012

3.16 *1012

S4

3.19 *1012

3.19 *1012

Cout

131.12 *1012

131.12 *1012

10

## Delay between schematic and layout

S1

217.8 *1012

S2

246.1 *1012

S3

258.2 *1012

S4

276.3 *1012

Cout

298.3 *1012

Conclusion

In this experiment, 4 bit ripple adder circuit schematic and layout were designed in cadence
using cmos logic.The 4 bit ripple adder circuit cant compute the outputs instantaneously.
There is some delay between the time the inputs are sent to the circuit, and the time
the output is computed.Lets say the delay is T units of time.An n-bit ripple carry adder
consists of n adders, there will be a delay of nT. This is O(n) delay.Here n=4.While the
adders are working in parallel, the carrys must ripple their way from the least significant
bit and work their way to the most significant bit. It takes T units for the carry out of the
rightmost column to make it as input to the adder in the next to rightmost column.Thus,
the carries slow down the circuit, making the addition linear with the number of bits in