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Contents
ADS workspace table
ADS Certification Task 1 Checklist
1.- Max Flat LPF
2.- Equal Ripple LPF
3.- LPF from Template SW_LPF_LC
4.- How to Generate a Symbol
5.- Max Flat HPF
6.- Equal Ripple HPF
7.- BPF with Microstrip from Template
8.- BPF with Smart Filter Block
9.- Filter Transfer Function with AC Sweep
10.- In Out Z block Filtering with ADS Smith Chart Utility
11.- List of ADS examples for Single Freq Impedance Matching with L-shape Networks
12.- ADS Virtual Instrument to Test Filters Transfer Function
13.- Pending, Filters with DFILT
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INTRO
I started attempting to correct the previous 033 lab2 sent by email that was sent with some missing images.
However while fixing the problem, I decided to enhance a bit this Laboratory task in order to meet the requirements of ADS
certification checklist task 1.
from POZAR page 410 example 8.3, with fc=1GHz and 20dB stop band at f=2GHz one gets
| | 1 = 0.5 N=5,
yet since told to use ADS, when applying the ADS Filter Design Guide, in the Filter Assistant tab, when setting Ap=3dB at
1GHz and As=20dB at 2GHz, the design assistant sets N=4:
\02_max_flat_filter
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..\01_max_flat_filter.dds
..\02_max_flat_filter.dds
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..\01_max_flat_filter_DA_LCLowpassDT
When first I place the smart component, set the parameters and try directly to configure the filter block from the Filter Design window the following 'do
nothing' message may come up
I learnt that one has to first increase the filter order by for instance just 1 unit,
N=5, in what I think it's called the component instance window, and then go to
the Filter Design Menu and tell the assistant to design the filter.
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\03_equal_ripple_filter
Observation: I note that despite increasing by one the amount of elements in the filter circuit, perhaps it's a minor bug in the student version, the Filter
Assistant N remains on 4
Observation: furthermore, besides 5 generated elements in the filter but N remains 4 in the filter design window, the built-in filter analysis graph
generated from the filter design guide is only updated when switching circuit directly with
Or alternatively one can use the Filter Design from the beginning, switching the palette to the Smart Component Filters available:
\03_Cheby_2.dds
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Observation: I initially considered that in the previous filter realisation it would be convenient to place the highest notch right on 1GHz (marker
m4), that in turn may probably shift s21 furthest to the right peak slightly further to the right. Manual tuning has to be started from the top circuit, not
from the sub-circuit.
After a while attempting manual tuning I realised that to obtain at least -20dB |s11| and at the same time 0.5dB ripple flat band pass one may need
more components in the filter, and that manual tuning becomes if not impossible to achieve, it's time consuming as soon as the amount of tuneable
components increases..
The Filter Design assistant cannot be used because there are no smart components.
\cell_1.dds
Obviously this is not the LPF we are after. One way to modify this
filter down to the specs in point 1 is to use the optimizer, that it's a
bit ahead in the ADS certification check list, but why learning
tomorrow what one can learn today?
Single parameter
discrete with a DAC block that can also take input from
.mdf file
final
swept
programmable
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this LPF is too wide, the cut-off should be shorter, cutting at 1GHz. Then a first attempt with both dB(S(1,1)) and dB(S(2,1)) constraints does not manage
to optimise |s21|
Cockpit
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\generate_symbol
\04_max_flat_high_pass.dds
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\05_equal_ripple_high_pass.dds
OPTIONAL: WHY THE HIGH PASS FILTER SHOWS ATTENUATION HIGHER THAN -0.5dB?
Such may be the case when manually designing the filters. When using ADS Filter Guide, as one can in see in the zoomed s21, the 3 markers m5 m6 m7 show the lowest
attenuation in the HPF pass band to be within specs [0 0.5] dB
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\SW_BPF_MS
Now I manually tune this filter to shift centre of the filter pass band around 1GHz:
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may be I can manually improve the attenuation along the pass band:
learning how to play with different steps mins and maxs, may also need more frequency resolution than can only be changed with the tuner off
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the problem when attempting to trim with excessively small steps is that the impedances start to show 'noise' tat at this point one cannot tell if it's really
simulated noise because tracks too close each other or numerical errors that with too small step push impedance markers from one side to the other of
the Smith Chart.
Another probable explanation of such zig-zagged Smith Chart may be that a microstrip that is perfectly working well at for instance 2GHz, may need a
translation into UHF components like mechanical tuning structures or lumped components that precisely avoid the problems that arise when attempting to
use microstrip lines at too low frequency for its dimensions. Let's see if automating the search of optimal W S L can be solved with the Optimizer.
\cell_3_BPF_template_ustrip
Again I have put all W S L in the optimizer,
tried different algorithms, manual tuning,
expanded ranges for all W S L yet the
optimizer doesn't move a single millimetre
|s21| and |s11| curves.
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the filter has the ports stuck on short circuit and no matter what
algorithm, start values, or ranges, it remains shorted. Tuning directly on
microstrip parameters is not that easy.
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Microstgrip
components
Microstrip circuit
blocks
Stripline
Stripline circuit
blocks
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Input Port
SLC SE L=6.991415 nH C=1.811529 pF
PLC PG L=2.693403 nH C=4.702286 pF
SLC SE L=15.071753 nH C=840.32349 fF
PLC PG L=2.25022 nH C=5.628404 pF
SLC SE L=16.114517 nH C=785.946493 fF
PLC PG L=2.182683 nH C=5.802558 pF
SLC SE L=16.349403 nH C=774.655077 fF
PLC PG L=2.172628 nH C=5.829414 pF
SLC SE L=16.24939 nH C=779.422981 fF
PLC PG L=2.244598 nH C=5.642503 pF
SLC SE L=13.025929 nH C=972.302851 fF
Output Port
The Filter Design Window solves very quickly the problem of previously attempt manual tuning:
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Input Port
PLC PG L=1.283396 nH
C=19.786397 pF
SLC SE L=111.672606 nH
C=227.394895 fF
PLC PG L=526.644952 pH
C=48.218027 pF
SLC SE L=113.742245 nH
C=223.257246 fF
Output Port
And experience proves that it pays off as Winston Churchill once wrote
it to go for a conservative choice in matters of design.
Input Port
SLC SE L=58.952473 nH C=430.750047 fF
PLC PG L=576.237452 pH C=44.068257 pF
SLC SE L=136.766922 nH C=185.671945 fF
PLC PG L=485.11323 pH C=52.346089 pF
SLC SE L=117.46516 nH C=216.181381 fF
Output Port
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the Design assistant generates a filter design result presentation that for this filter it shows the following:
\DA_LCBandpassST3.dds
\SA_LCBandpassST1.dds
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\Zmatch_input.scu
In same way that the student version only allows 1 open Workspace at a time, there can only be one Smith Chart utility open at a time, and when in the
Smith Chart Utility one clicks on DESIGN button to translate into circuit components, the Smith Chart Utility updates whatever smart component available
in the circuit, and selected from the top right corner of the Smith Chart utility.
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\Zmatch_output.scu
\Zmatch_with_Smith_Chart_Utility.dds
wonder: the flat |s21| may be caused by the transformers, because as shown in this Smith Chart there is no short.
Observation: In the YouTube presentation the author mirrors one of the SCU generated blocks, to make the same port number of both SCU generated
blocks to be the one in contact with the Z block, and respectively face load and source respectively with same other pin number.
When I try this
\Zmatch_reversed_with_Smith_Chart_Utility |cell30
yet if one may accidentally reverse the matching ports, placing the input matching network DA_SmithChartMatch1 at the output and network
DA_SmithChartMatch2 at the input, then the gadget is at 1GHz quite an open circuit.
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\Zmatch_reversed_with_Smith_Chart_Utility.dds
\Zmatch2_input.scu
\Zmatch3_input.scu
\Zmatch4_input.scu
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A simple stretch of microstrip plus a couple series capacitors and a series inductor may suffice.
gremlin: getting this error message from time to time, fputs and NULLS and references to missing files are the last thing that customers expect to see
when shoving considerable amounts of money for s software tool and is one of the reasons why they start considering or make up their mind regarding
using alternative tools.
11 LIST OF ADS EXAMPLES FOR SINGLE FREQ IMPEDANCE MATCHING WITH L-SHAPE NETWORKS
The Design Guide Amplifier contains a group of L shape matching network test benches that automate the calculations of
capacitors and inductances when looking for a quick narrow 2 elements impedance match.
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Pending: It would be useful through equations and variables or AEL script to get these test benches calculating values
upon query from an arbitrary filter design and to get in return possible L matching networks.
\SS_P2P_TOP4
tip: there is no need to expand one by one cell folders, select a group or ctrl+a within the workspace to check right mouse
click and there are options to both 'expand all' or 'collapse all'.
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