Lecture 19

The WHY slide

Logistics

Lab 8 this week to be done in pairs

HW5 and HW6 solutions out today

HW7 out today due Wednesday March 4
Midterm 2 Wednesday

Find a partner before your lab period

Otherwise you will have to wait for a pairing which will slow you down

Moore/Mealy machines

Covers material up to simple FSM

Review session tomorrow, 4:30 here, EEB 037

There are two different ways to express the FSMs with

respect to the output. Both have different advantages so it is
good to know them.

Last lecture

Counter FSM design

General Finite State Machine Design
Vending machine example

Today

Moore/Mealy machines
Midterm 2 topics and logistics

CSE370, Lecture 19

Generalized FSM model: Moore and Mealy

CSE370, Lecture 19

Moore versus Mealy machines

Combinational logic computes next state and outputs

Next state is a function of current state and inputs

Outputs are functions of

inputs

combinational
logic for
next state

Current state (Moore machine)

Current state and inputs (Mealy machine)

Moore machine
Outputs are a function
of current state
reg

logic for
outputs

outputs

Outputs change
synchronously with
state changes

state feedback

Inputs

output
logic
Next-state
logic

logic for
outputs

inputs

Outputs

combinational
logic for
next state

Next State

Current State
CSE370, Lecture 19

CSE370, Lecture 19

State diagram
State-transition table
Next-state logic minimization
Implement the design

Each state is labeled by a pair:

state-name/output

State diagram
State-transition table
State minimization
State encoding
Next-state logic minimization
Implement the design

CSE370, Lecture 19

Moore machine

FSM-design procedure
1.
2.
3.
4.
5.
6.

Input changes can cause

immediate output changes
(asynchronous)

State Diagrams

Counter-design procedure
1.
2.
3.
4.

reg

state feedback
3

Impacts start of the FSM design procedure

Mealy machine
Outputs depend on state
and on inputs

outputs

or

state-name [output]

Mealy machine

Each transition arc is labeled by a pair:

input-condition/output

CSE370, Lecture 19

Example 10 01: Moore or Mealy?

Example 01 or 10 detector: a Moore machine

Circuits recognize AB=10 followed by AB=01

What kinds of machines are they?

Output is a function of state only

Specify output in the state bubble

current next
reset input state
state

out
A

DQ
Q

DQ
Q

DQ
Q

DQ
Q

out
A

D Q
Q

D Q
Q

clock

Mealy

0/1

1/1

1/0
C

A
B
C
B
D
E
C
E
C
B
D

0
0
0
0
0
0
0
1
1
1
1
8

Moore machines
+ Safer to use because outputs change at clock edge
May take additional logic to decode state into outputs

current next
reset input state
state
1
0
0
0
0
0
0

E/1

A
A
B
B
C
C
D
D
E
E

CSE370, Lecture 19

Specify outputs on transition arcs

0/0
reset/0

0
1
0
1
0
1
0
1
0
1

Comparing Moore and Mealy machines

Output is a function of state and inputs

1
1

1
7

0/0

0
A/0

C/0

Example 01 or 10 detector: a Mealy machine

reset

CSE370, Lecture 19

1
0
0
0
0
0
0
0
0
0
0

D/1

clock

Moore

B/0

current
output

0
1
0
1
0
1

A
A
B
B
C
C

A
B
C
B
C
B
C

0
0
0
0
1
1
0

Mealy machines
+ Typically have fewer states
+ React faster to inputs don't wait for clock
Asynchronous outputs can be dangerous

current
output

We often design synchronous Mealy machines

Design a Mealy machine

Then register the outputs

1/0
CSE370, Lecture 19

Synchronous (registered) Mealy machine

10

Example =01: Moore or Mealy?

Registered state and registered outputs

CSE370, Lecture 19

No glitches on outputs
No race conditions between communicating machines

Recognize AB = 01

Mealy or Moore?

A
D

inputs

logic for
outputs
combinational
logic for
next state

reg

outputs

Registered Mealy
(actually Moore)

reg

clock

out

out

Q
Q

state feedback

CSE370, Lecture 19

clock

11

CSE370, Lecture 19

Q
Q

Moore

12

Example: A parity checker

Example: A parity checker

1.

State diagram

Serial input string

Moore

OUT=1 if odd # of 1s in input

OUT=0 if even # of 1s in input

Mealy

Lets do this for Moore and Mealy

0/00
Even
[0]

Even
[0]

1 1/0

1/11

Odd
[1]

Odd
[1]

0/1

CSE370, Lecture 19

CSE370, Lecture 19

13

14

Example: A parity checker

Example: A parity checker

1. State-transition table

3. State minimization: Already minimized

Moore

Present
State

Input

Next
State

Even
Even
Odd
Odd

0
1
0
1

Even
Odd
Odd
Even

Present
Output
0
0
1
1 Present
State
Even
Even
Odd
Odd

Mealy
Input

Next
State

Present
Output

0
1
0
1

Even
Odd
Odd
Even

0
1
1
0

CSE370, Lecture 19

CSE370, Lecture 19

15

Example: A parity checker

Moore

5. Next-state logic minimization

Present
State

Input

Next
State

Present
Output

0
0
1
1

0
1
0
1

0
1
1
0

0
0
1
1

0
0
1
1

Assume D flip-flops
Next state = (present state) XOR (present input)

6. Implement the design

Input
0
1
0
1

Next
State
0
1
1
0

Mealy
Output

Moore

Mealy

Present
State

16

Example: A parity checker

Assignment
Even 0
Odd 1

4. State encoding

CSE370, Lecture 19

Need both states (even and odd)

Use one flip-flop

Present
Output

Input

Output

Input

0
1
1
0

CLK
17

CSE370, Lecture 19

Q
Q

Current
State

CLK
18

What was covered after midterm 1

What was covered after midterm 1

Combinational logic applications

PLAs/PALs
ROMs
Adders
Multi-level logic
Timing diagrams
Hazards

Sequential logic building blocks

1010
+ 0110
------------????

Latches (R-S and D)

Flip-flops (D and T)
Latch and flip-flop timing (setup/hold time, prop delay)
Timing diagrams
Asynchronous inputs and metastability
Registers
Remember that
the last number was 1

CSE370, Lecture 19

19

Counters

Timing diagrams
Shift registers
Ring counters
State diagrams and state-transition tables
Counter design procedure
1.
2.
3.
4.

Draw a state diagram

Draw a state-transition table
Encode the next-state functions
Implement the design

20

What was covered after midterm 1

What was covered after midterm 1

CSE370, Lecture 19

Finite state machines

1, 2, 3, 4,

FSM design procedure

1.
2.
3.
4.
5.
6.

State diagram
State-transition table
State minimization
State encoding
Next-state logic minimization
Implement the design

The last coin was 25cents and

already had 50cents deposited
so lets pop out a soda

No Mealy machines

Self-starting counters

Don t expect to know a ton of FSM.

Just understand what was presented in the lectures.

CSE370, Lecture 19

21

Midterm 2 logistics

45 minutes long (starts 10:35)

Materials covered from

Lectures 9 to 18 (but not Sequential Verilog or Moore/Mealy)

HW 4, 5, and 6

Closed book/notes, no calculator

Scratch papers provided

Just have your pencil/pen and eraser

Raise hand for questions (dont walk to get help)

CSE370, Lecture 19

23

CSE370, Lecture 19

22