H8S ...........................................................................................................................................
Warning ..............................................................................................................................
Reset Line
Troubleshooting ................................................................................................................
SYStem.Up Errors
FAQ
Configuration .....................................................................................................................
System Overview
10
10
11
11
11
12
SYStem.JtagClock
SYStem.Option Advanced
12
SYStem.Option BrkVector
13
SYStem.Option IMASKASM
13
SYStem.Option IMASKHLL
13
SYStem.Option KEYCODE
Keycode
13
14
14
15
SYStem.MemAccess
SYStem.Mode
SYStem.LOCK
JTAG lock
1989-2016 Lauterbach GmbH
H8S/23x9 Debugger
15
SYStem.CONFIG
16
Daisy-chain Example
18
TapStates
19
SYStem.CONFIG.CORE
20
Breakpoints ........................................................................................................................
21
Software Breakpoints
21
On-chip Breakpoints
21
Breakpoint in ROM
21
21
TrOnchip.CONVert
23
23
23
TrOnchip.DMA
23
TrOnchip.DTC
24
TrOnchip.SIZE
24
24
Sequential breakpoints
25
26
Trace ...................................................................................................................................
27
TrOnchip.RESet
TrOnchip.SEQ
FIFO Trace
27
28
29
Support ...............................................................................................................................
30
Available Tools
30
Compilers
30
31
31
Products .............................................................................................................................
33
Product Information
33
Order Information
33
H8S/23x9 Debugger
H8S/23x9 Debugger
Version 24-May-2016
General Note
This documentation describes the processor specific settings and features for
TRACE32-ICD for the following CPUs:
H8S/2329, H8S/2339
H8S/2367, H8S/2377
Debugger Basics - Training (training_debugger.pdf): Get familiar with the basic features of a
TRACE32 debugger.
Architecture-specific information:
Processor Architecture Manuals: These manuals describe commands that are specific for the
processor architecture supported by your debug cable. To access the manual for your processor
architecture, proceed as follows:
-
RTOS Debugger (rtos_<x>.pdf): TRACE32 PowerView can be extended for operating systemaware debugging. The appropriate RTOS manual informs you how to enable the OS-aware
debugging.
H8S/23x9 Debugger
General Note
Warning
Signal Level
The debugger drives the output pins of the JTAG connector with 3.3 V always.
ESD Protection
NOTE:
Disconnect the debug cable from the target while the target power is
off.
2.
Connect the host system, the TRACE32 hardware and the debug
cable.
3.
4.
5.
6.
7.
Power down:
1.
2.
3.
4.
H8S/23x9 Debugger
Warning
Application Note
Reset Line
Ensure that the debugger signal RESET is connected directly to the RESET of the processor. This will
provide the ability for the debugger to drive and sense the status of RESET.
VCC
10 k
Reset Sense
Target Reset
Force Reset
H8S/23x9 Debugger
Application Note
Select the device prompt B: for the ICD Debugger, if the device prompt is not active after the
TRACE32 software was started.
b:
2.
3.
If the TRACE32-ICD hardware is installed properly, the following CPU is the default setting:
H8S
4.
This command resets the CPU and enters debug mode. After this command is executed it is possible
to access the registers.Set the chip selects to get access to the target memory.
Data.Set
6.
The option of the Data.LOAD command depends on the file format generated by the compiler. For
information on the compiler options refer to the section Compiler. A detailed description of the
Data.LOAD command is given in the General Commands Reference.
H8S/23x9 Debugger
The start up can be automated using the programming language PRACTICE. A typical start sequence is
shown below:
b::
WinClear
MAP.BOnchip 0x100000++0x0fffff
SYStem.CPU H8S/2339
SYStem.Up
Data.LOAD.COFF GNUSH7.X
Register.Set PC main
Data.List
Register
PER
Break.Set sieve
Break.Set 0x1000 /p
Break.Set 0x101000 /p
;
;
;
;
*) These commands open windows on the screen. The window position can be specified with the WinPOS
command.
H8S/23x9 Debugger
Troubleshooting
SYStem.Up Errors
The SYStem.Up command is the first command of a debug session where communication with the target is
required. If you receive error messages while executing this command this may have the following reasons.
All
All
All
All
All
KEYCODE if does not match FLASH content and FLASH programming disabled
(FWE pin low level)
H8S/23x9 Debugger
Troubleshooting
FAQ
No information available
H8S/23x9 Debugger
Troubleshooting
Configuration
System Overview
PODBUS Cable
PODPC
PODPAR
PODETH
Debug
Interface
EPROM
Simulator
(optional)
...
Debug Cable
CPU CLK
RESET
INT
Target Connector
EPROM
Target
H8S/23x9 Debugger
10
Configuration
System Commands
SYStem.CPU
Format:
SYStem.CPU <cpu>
<cpu>:
H8S/2339
SYStem.CpuAccess
Format:
Default: Denied.
Enable
Denied
Nonstop
Lock all features of the debugger, that affect the run-time behavior.
Nonstop reduces the functionality of the debugger to:
trace display
The debugger inhibits the following:
all features of the debugger that are intrusive (e.g. action Spot for breakpoints, performance analysis via StopAndGo mode, conditional breakpoints etc.)
1989-2016 Lauterbach GmbH
H8S/23x9 Debugger
11
System Commands
SYStem.JtagClock
Format:
SYStem.Option Advanced
Format:
on
H8S/23x9 Debugger
12
System Commands
SYStem.Option BrkVector
Format:
tbd.
SYStem.Option IMASKASM
Format:
Mask interrupts during assembler single steps. Useful to prevent interrupt disturbance during assembler
single stepping.
SYStem.Option IMASKHLL
Format:
Mask interrupts during HLL single steps. Useful to prevent interrupt disturbance during HLL single stepping.
SYStem.Option KEYCODE
Format:
Keycode
During System.UP the KEYCODE is sent to the CPU and compared against certain Flash contents. If the
KEYCODE does not fit, the CPU automatically erases its FLASH before the debug monitor can be
downloaded. This is a special security feature of the CPU.
H8S/2319
Keycode has to be the same value as present in CPU Flash at address 0x78-0x7B
H8S/2367
H8S/2377
H8SX
Keycode has to be the same value as present in CPU Flash at address 0x4-0x7
H8S/23x9 Debugger
13
System Commands
SYStem.MemAccess
Format:
CPU
Denied
Default: Denied.
SYStem.Mode
Format:
SYStem.Mode
<mode>
<mode>:
Down
Go
Up
Down
Go
Resets the target with debug mode enabled and prepares the CPU for debug
mode entry. After this command the CPU is in the system.up mode and running.
Now, the processor can be stopped with the break command or until any break
condition occurs.
Up
Resets the target and sets the CPU to debug mode. After execution of this
command the CPU is stopped and prepared for debugging. All register are set
to the default value.
Attach
Not supported.
NoDebug
Not supported.
StandBy
Not supported.
H8S/23x9 Debugger
14
System Commands
Multicore Debugging
If your H8S device is the only one connected to the JTAG connector then the following system setting should
be left in their default position.
If your H8S CPU is lined up in a target JTAG chain then the debugger has to be informed about the position
of the H8S device inside the JTAG chain. Following system settings have to be done according to your target
configuration.
SYStem.LOCK
Format:
JTAG lock
Default: OFF. If the system is locked (ON) no access to the JTAG port will be performed by the debugger. All
JTAG connector signals of the debugger are tristated.
This command is useful if there are additional CPUs (Cores) on the target which have to use the same JTAG
lines for debugging. By locking the H8S debugger lines a different debugger can own mastership of the
JTAG interface.
It must be ensured that the state of the H8S core JTAG state machine remains unchanged while the system
is locked. To ensure correct hand over between two debuggers a pull-down resistor on TCK and a pull-up
resistor on /TRST is required.
H8S/23x9 Debugger
15
Multicore Debugging
SYStem.CONFIG
Format:
<parameter>
(General):
state
CORE
(JTAG):
DRPRE <bits>
DRPOST <bits>
IRPRE
<bits>
IRPOST <bits>
TAPState <state>
TCKLevel <level>
TriState [ON | OFF]
Slave
[ON | OFF]
<core>
The four parameters IRPRE, IRPOST, DRPRE, DRPOST are required to inform the debugger about the
TAP controller position in the JTAG chain, if there is more than one core in the JTAG chain (e.g. ARM +
DSP). The information is required before the debugger can be activated e.g. by a SYStem.Up. See Daisychain Example.
For some CPU selections (SYStem.CPU) the above setting might be automatically included, since the
required system configuration of these CPUs is known.
TriState has to be used if several debuggers (via separate cables) are connected to a common JTAG port
at the same time in order to ensure that always only one debugger drives the signal lines. TAPState and
TCKLevel define the TAP state and TCK level which is selected when the debugger switches to tristate
mode. Please note: nTRST must have a pull-up resistor on the target, TCK can have a pull-up or pull-down
resistor, other trigger inputs needs to be kept in inactive state.
Multicore debugging is not supported for the DEBUG INTERFACE (LA-7701).
H8S/23x9 Debugger
16
Multicore Debugging
state
CORE
For multicore debugging one TRACE32 GUI has to be started per core.
To bundle several cores in one processor as required by the system this
command has to be used to define core and processor coordinates within
the system topology.
Further information can be found in SYStem.CONFIG.CORE.
DRPRE
DRPOST
(default: 0) <number> of TAPs in the JTAG chain between the TDI signal
of the debugger and the core of interest. If each core in the system
contributes only one TAP to the JTAG chain, DRPOST is the number of
cores between the TDI signal of the debugger and the core of interest.
IRPRE
IRPOST
TAPState
TCKLevel
TriState
(default: OFF) If several debuggers share the same debug port, this
option is required. The debugger switches to tristate mode after each
debug port access. Then other debuggers can access the port. JTAG:
This option must be used, if the JTAG line of multiple debug boxes are
connected by a JTAG joiner adapter to access a single JTAG chain.
Slave
(default: OFF) If more than one debugger share the same debug port, all
except one must have this option active.
JTAG: Only one debugger - the master - is allowed to control the signals
nTRST and nSRST (nRESET).
H8S/23x9 Debugger
17
Multicore Debugging
Daisy-chain Example
TDI
Core A
Core B
Core C
Chip 0
Core D
TDO
Chip 1
Core A: 3 bit
Core B: 5 bit
Core D: 6 bit
SYStem.CONFIG.IRPRE 6
; IR Core D
SYStem.CONFIG.IRPOST 8
; IR Core A + B
SYStem.CONFIG.DRPRE 1
; DR Core D
SYStem.CONFIG.DRPOST 2
; DR Core A + B
SYStem.CONFIG.CORE 0. 1.
H8S/23x9 Debugger
18
Multicore Debugging
TapStates
0
Exit2-DR
Exit1-DR
Shift-DR
Pause-DR
Select-IR-Scan
Update-DR
Capture-DR
Select-DR-Scan
Exit2-IR
Exit1-IR
10
Shift-IR
11
Pause-IR
12
Run-Test/Idle
13
Update-IR
14
Capture-IR
15
Test-Logic-Reset
H8S/23x9 Debugger
19
Multicore Debugging
SYStem.CONFIG.CORE
Format:
<chipindex>:
1i
<coreindex>:
1k
H8S/23x9 Debugger
20
Multicore Debugging
Breakpoints
There are two types of breakpoints available: Software breakpoints (SW-BP) and on-chip breakpoints (HWBP).
Software Breakpoints
Software breakpoints are the default breakpoints. A special breakcode is patched to memory so it only can
be used in RAM areas.There is no restriction in the number of software breakpoints.
On-chip Breakpoints
The following list gives an overview of the usage of the on-chip breakpoints by
TRACE32-ICD:.
CPU Family
Number of
Address Breakpoints
Number of
Data Breakpoints
Sequential
Breakpoints
H8S
---
H8SX
B>A
C>B>A
D>C>B>A
Breakpoint in ROM
With the command MAP.BOnchip <range> it is possible to inform the debugger where you have ROM
(FLASH,EPROM) on the target. If a breakpoint is set within the specified address range the debugger uses
automatically the available on-chip breakpoints.
H8S/23x9 Debugger
21
Breakpoints
1.
2.
Software breakpoints:
; Software Breakpoint 1
; Software Breakpoint 2
; Software Breakpoint 3
On-chip breakpoints:
Break.Set 0x100 /Program
; On-chip Breakpoint 1
; On-chip Breakpoint 2
H8S/23x9 Debugger
22
Breakpoints
TrOnchip Commands
TrOnchip.view
Format:
TrOnchip.view
TrOnchip.CONVert
Format:
The onchip breakpoints can only cover specific ranges. If a range cannot be programmed into the breakpoint
it will automatically be converted into a single address breakpoint when this option is active. This is the
default. Otherwise an error message is generated.
TrOnchip.CONVert ON
Break.Set 0x1000--0x17ff /Write
Break.Set 0x1001--0x17ff /Write
...
TrOnchip.CONVert OFF
Break.Set 0x1000--0x17ff /Write
Break.Set 0x1001--0x17ff /Write
TrOnchip.DMA
Format:
H8S/23x9 Debugger
23
TrOnchip Commands
TrOnchip.DTC
Format:
TrOnchip.SIZE
Format:
If ON, breakpoints on single-byte, two-byte or four-byte addressranges only hit if the CPU accesses this
ranges with a byte, word or long buscycle.
Default: OFF
TrOnchip.RESet
Format:
TrOnchip.RESet
Sets the TrOnchip settings and trigger module to the default settings.
H8S/23x9 Debugger
24
TrOnchip Commands
TrOnchip.SEQ
Sequential breakpoints
Format:
TrOnchip.SEQ <mode>
<mode>:
OFF
BA
CBA
DCBA
BA
CBA
Sequential break, first condition, then second condition, then third conditon.
DCBA
Sequential break, first condition, then second condition, then third conditon and
the fourth condition.
H8S/23x9 Debugger
25
TrOnchip Commands
Memory Classes
The following memory classes are available:
Memory Class
Description
Program
Data
H8S/23x9 Debugger
26
Memory Classes
Trace
To support analysis of the program history the ICD supports following algorithm
FIFO Trace
This CPU includes a 4-stage branch trace. This trace holds the source address of the last four program flow
changes.
The ICD command FIFO opens a window which displays the content of the branch trace.
This trace method does not slow down program execution.
H8S/23x9 Debugger
27
Trace
Runtime Measurement
Runtime measurement is done with about 5us resolution.
The debuggers RUNTIME window gives detailed information about the complete run-time of the application
code and the run-time since the last GO/STEP/STEP-OVER command.
H8S/23x9 Debugger
28
Runtime Measurement
JTAG Connector
Signal
TCK
TRSTTDO
RSTOUTTMS
TDI
RESET-
Pin
1
3
5
7
9
11
13
Pin
2
4
6
8
10
12
14
Signal
GND
GND
GND
VCC
GND
GND
GND
Signal description:
TMS
TDI
TCK
/TRST
TDO
/RESET
/RSTOUT
VCC
H8S/23x9 Debugger
29
JTAG Connector
Support
INSTRUCTION
SIMULATOR
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
POWER
INTEGRATOR
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
ICD
TRACE
ICD
MONITOR
H8S/2319
H8S/2329
H8S/2339
H8S/2367
H8S/2368
H8S/2377
H8S/2378
H8SX/1642
H8SX/1644
H8SX/1648
H8SX/1648G
H8SX/1648H
H8SX/1663
H8SX/1664
H8SX/1668
H8SX/1668M
H8SX/1668R
H8SX/1725
ICD
DEBUG
FIRE
ICE
CPU
Available Tools
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
Compilers
Language
Compiler
Company
Option
Comment
C
C
ICCH8
CH38
UBROF
SYSROF
H8S
H8S
C++
GNU
C++
CH38
IAR Systems AB
Renesas Technology,
Corp.
Free Software
Foundation, Inc.
Renesas Technology,
Corp.
COFF
SYSROF
H8S/23x9 Debugger
30
Support
Company
Comment
CMX-RTX
CMX-TINY
FreeRTOS
Nucleus
osCAN
OSEK
ProOSEK
RTXC 3.2
v7
via ORTI
via ORTI
via ORTI
Tool
Company
ALL
ALL
ALL
ADENEO
X-TOOLS / X32
CODEWRIGHT
ALL
CODE CONFIDENCE
TOOLS
CODE CONFIDENCE
TOOLS
EASYCODE
ECLIPSE
RHAPSODY IN MICROC
RHAPSODY IN C++
CHRONVIEW
LDRA TOOL SUITE
UML DEBUGGER
Adeneo Embedded
blue river software GmbH
Borland Software
Corporation
Code Confidence Ltd
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ATTOL TOOLS
VISUAL BASIC
INTERFACE
LABVIEW
Host
Windows
Windows
Windows
Linux
EASYCODE GmbH
Eclipse Foundation, Inc
IBM Corp.
IBM Corp.
Inchron GmbH
LDRA Technology, Inc.
LieberLieber Software
GmbH
MicroMax Inc.
Microsoft Corporation
Windows
Windows
Windows
Windows
Windows
Windows
Windows
NATIONAL
INSTRUMENTS
Corporation
Windows
Windows
Windows
H8S/23x9 Debugger
31
Support
CPU
Tool
Company
Host
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
CODE::BLOCKS
C++TEST
RAPITIME
DA-C
TRACEANALYZER
SIMULINK
TA INSPECTOR
UNDODB
VECTORCAST UNIT
TESTING
VECTORCAST CODE
COVERAGE
WINDOWS CE PLATF.
BUILDER
Open Source
Parasoft
Rapita Systems Ltd.
RistanCASE
Symtavision GmbH
The MathWorks Inc.
Timing Architects GmbH
Undo Software
Vector Software
Windows
Windows
Windows
Windows
Windows
Windows
Linux
Windows
Vector Software
Windows
Windows
Windows
ALL
ALL
H8S/23x9 Debugger
32
Support
Products
Product Information
OrderNo Code
Text
LA-3745
JTAG-H8SX
LA-3745X
JTAG-H8SX-X
LA-7766
JTAG-H8S
Order Information
Order No.
Code
Text
LA-3745
LA-3745X
LA-7766
JTAG-H8SX
JTAG-H8SX-X
JTAG-H8S
H8S/23x9 Debugger
33
Products