Debugger Mcore

M-Core Debugger
TRACE32 Online Help

TRACE32 Directory
TRACE32 Index
TRACE32 Documents ......................................................................................................................
ICD In-Circuit Debugger ................................................................................................................
Processor Architecture Manuals ..............................................................................................
M-Core ......................................................................................................................................
M-Core Debugger .................................................................................................................
General Note ......................................................................................................................
Brief Overview of Documents for New Users .................................................................
Warning ..............................................................................................................................
Quick Start JTAG/ONCE ...................................................................................................
Breakpoints ........................................................................................................................
Software Breakpoints
On-chip Breakpoints
Breakpoint in ROM
Example for Breakpoints
Troubleshooting ................................................................................................................
10
SYStem.Up Errors
10
Memory Access Errors
10
FAQ .....................................................................................................................................
11
Configuration .....................................................................................................................
15
System Overview
15
Runtime Measurement
16
Memory Classes
16
Memory Coherency
16
General SYStem Settings for the Debugger ...................................................................

SYStem.BdmClock
Define JTAG clock
SYStem.CONFIG
SYStem.CONFIG
17
17
17
Configure debugger according to target topology
17
Daisy-chain Example
20
TapStates
21
SYStem.CONFIG.CORE
SYStem.CPU
1989-2016 Lauterbach GmbH
M-Core Debugger
Assign core to TRACE32 instance
22
Selects the CPU
23
SYStem.CpuAccess
Run-time memory access (intrusive)
24
Sets JTAG clock frequency
25
Tristate the JTAG port
25
Real-time memory access (non-intrusive)
26
Establish the communication with the target
27
SYStem.JtagClock
SYStem.LOCK
SYStem.MemAccess
SYStem.Mode
Stop CPU via debug enable line
28
SYStem.Option DUALPORT
SYStem.Option DE
Update all memory displays during runtime
28
SYStem.Option IMASKASM
Disable interrupts while single stepping
28
Disable interrupts while HLL single stepping
29
SYStem.Option IMASKHLL
SYStem.Option PC
Not supported command
29
Use TRST line to reset the TAP controller
29
Trigger On-chip Commands .............................................................................................
30
SYStem.Option TRST
TrOnchip.CYcle
TrOnchip.A.Address
Define access type
30
Define address selector
31
TrOnchip.CONVert
Adjust range breakpoint in on-chip resource
32
TrOnchip.EXTernal
Generate a trigger for trace on high pulse on in0 or in1
32
Configure unit A and B
33
Adjust complex breakpoint in on-chip resource
34
TrOnchip.Mode
TrOnchip.VarCONVert
TrOnchip.RESet
Set on-chip trigger to default state
34
Display on-chip trigger window
34
JTAG Connector ................................................................................................................
35
Technical Data ...................................................................................................................
36
TrOnchip.view
Operation Voltage
36
Support ...............................................................................................................................
Available Tools
37
37
Compilers
37
Realtime Operation Systems
37
3rd Party Tool Integrations
38
Products .............................................................................................................................
39
Product Information
39
Order Information
39
M-Core Debugger
M-Core Debugger
Version 24-May-2016
#
B::Register
R0
81007FC8
R1
28
R2
0B
R3
666666BE
R4
404F6666
R5
66666666
R6
1
R7
81003953
R8
R9
R10
R11
R12
R13
R14
R15
B::SYStem
Mode
Down
NoDebug
Go
Attach
StandBy
Up (Stand
Up
12345678
9999
1
0
2E002524
81002478
0B
81000A94
PSR
80000001 SS0
1958884A
VBR
81000000 SS1
160F1000
EPSR C3008ADC SS2
E0841008
FPSR 33088171 SS3
0428C10C
EPC
FFFFFFFE SS4
A212880F
FPC
212106CA GCR
0
PC
81000AB2 GSR
0
S S TM 0 TC _ MM _ EE _
IC _ IE _ FE _ AF _ C C
R0'
R1'
82DA8EA3
8543E702
R8'
R9'
MemAccess
CPU
Denied
CpuAccess
Enable
Denied
Nonstop
Option
IMASKASM
IMASKHLL
DE
JtagClock
10.0MHz
CPU
MMC2114
C03A0C4C
57631807
B::Data.List
addr/line
source
int anzahl;
682
anzahl = 0;
684
for ( i = 0 ; i <= SIZE ; flags[ i++ ] = TRUE ) ;
686
for ( i = 0 ; i <= SIZE

{
if ( flags[ i ]
{
primz =
k = i +
while (
{
688
690
691
692
694
695
)
i + i + 3;
primz;
k <= SIZE )
flags[ k ] = FALSE;
k += primz;
}
anzahl++;
697
}
}
M-Core Debugger
; i++ )
General Note
This documentation describes the processor specific settings and features for
TRACE32-ICD for the following CPU families:
MCORE xx (2001, 2107, 2112, )
If some of the described functions, options, signals or connections in this Processor Architecture Manual are
only valid for a single CPU or for specific families, the name(s) of the family(ies) is added in brackets.
Brief Overview of Documents for New Users

Architecture-independent information:
Debugger Basics - Training (training_debugger.pdf): Get familiar with the basic features of a
TRACE32 debugger.
T32Start (app_t32start.pdf): T32Start assists you in starting TRACE32 PowerView instances

for different configurations of the debugger. T32Start is only available for Windows.
General Commands (general_ref_<x>.pdf): Alphabetic list of debug commands.
Architecture-specific information:
Processor Architecture Manuals: These manuals describe commands that are specific for the
processor architecture supported by your debug cable. To access the manual for your processor
architecture, proceed as follows:
-
Choose Help menu > Processor Architecture Manual.
RTOS Debugger (rtos_<x>.pdf): TRACE32 PowerView can be extended for operating systemaware debugging. The appropriate RTOS manual informs you how to enable the OS-aware
debugging.
M-Core Debugger
General Note
Warning
NOTE:
To prevent debugger and target from damage it is recommended to connect or

disconnect the debug cable only while the target power is OFF.
Recommendation for the software start:
1.
Disconnect the debug cable from the target while the target power is
off.
2.
Connect the host system, the TRACE32 hardware and the debug
cable.
3.
Power ON the TRACE32 hardware.
4.
Start the TRACE32 software to load the debugger firmware.
5.
Connect the debug cable to the target.
6.
Switch the target power ON.
7.
Configure your debugger e.g. via a start-up script.
Power down:
1.
Switch off the target power.
2.
Disconnect the debug cable from the target.
3.
Close the TRACE32 software.
4.
Power OFF the TRACE32 hardware.
M-Core Debugger
Warning
Quick Start JTAG/ONCE

Starting up the Debugger is done as follows:
5.
Select the device prompt B: for the ICD Debugger.

b:
If you are working with the PODPC card, a Podbus-Ethernet interface or a Podbus-Parallel adapter
device b:: is already selected.
6.
Select the CPU type to load the CPU specific settings.

SYStem.CPU MMC2107
7.
Tell the debugger wheres FLASH/ROM on the target.

MAP.BOnchip 0x00000000++0x0001FFFF
This command is necessary for the use of on-chip breakpoints.

8.
Enter debug mode

SYStem.Up
This command resets the CPU (RESET) and enters debug mode. After this command is executed it
is possible to access the CPU registers. Set the chip selects to get access to the target memory.
9.
Load the program.

Data.LOAD.ELF diabc.x
; elf specifies the format, diabc.x

; is the file name
The option of the Data.LOAD command depends on the file format generated by the compiler. For
information on the compiler options refer to the section Compiler. A detailed description of the
Data.LOAD command is given in the General Commands Reference.
M-Core Debugger
The start up can be automated using the programming language PRACTICE. A typical start sequence is
shown below:
b::
; Select the ICD device prompt
WinCLEAR
; Clear all windows
MAP.BOnchip
0x00000000++0x0001FFFF
; Specify wheres ROM
SYStem.CPU MMC2107
; Select the processor type
SYStem.Up
; Reset the target and enter debug mode
Data.LOAD.ELF diabc.x
; Load the application
Data.List
; Open disassembly window *)
Register /SpotLight
; Open register window *)
Frame.view /Locals /Caller
; Open the stack frame with

; local variables *)
Var.Watch %Spotlight flags ast
; Open watch window for variables *)
PER.view
; Open window with peripheral register
Break.Set sieve
; Set breakpoint to function sieve
Break.Set 0x800000 /Program
; Set software breakpoint to address

; 800000
; (address 800000 is in RAM)
; Set on-chip breakpoint to address

; 1000 (address 1000 is in ROM)
*) These commands open windows on the screen. The window position can be specified with the WinPOS
command.
M-Core Debugger
Breakpoints
There are two types of breakpoints available: Software breakpoints and on-chip breakpoints.
Software Breakpoints
Software breakpoints are the default breakpoints for program breakpoints. A software breakpoint is
implemented by patching a break code into the memory.
There is no restriction in the number of software breakpoints.
On-chip Breakpoints
The resources for the on-chip breakpoints are provided by the CPU.
The following list gives an overview of the on-chip breakpoints for the MCORE:
On-chip breakpoints: Total amount of available on-chip breakpoints.
Instruction breakpoints: Number of on-chip breakpoints that can be used to set Program
breakpoints into ROM/FLASH/EEPROM.
Read/Write breakpoints: Number of on-chip breakpoints that can be used as Read or Write
breakpoints.
Data breakpoint: Number of on-chip data breakpoints that can be used to stop the program
when a specific data value is written to an address or when a specific data value is read from an
address.
MCORE
On-chip
Breakpoints
Instruction
Breakpoints
Read/Write
Breakpoints
Data
Breakpoint
M-Core Debugger
Breakpoints
Breakpoint in ROM
By default program breakpoints are implemented as software breakpoints.
With the command MAP.BOnchip <range> it is possible to inform the debugger where you have ROM
(FLASH,EPROM) on the target. If a breakpoint is set within the specified address range the debugger uses
automatically the available on-chip breakpoints.
Example for Breakpoints

Assume you have a target with FLASH from 0 to 0x1FFFF and RAM from 0x800000 to 0x801fff. The
command to configure TRACE32 correctly for this configuration is:
Map.BOnchip 0x00000000++0x00001FFF
The following breakpoint combinations are possible.

Software breakpoints:
; Software Breakpoint 1
Break.Set 0x800f00 /Program
On-chip breakpoints:
; On-chip Breakpoint 1
Break.Set 0x0ff00 /Program
On-chip breakpoints on read or write access:

Break.Set 0x5678 /Write
Var.Break.Set flags[3] /Read
M-Core Debugger
Breakpoints
Troubleshooting
SYStem.Up Errors
The SYStem.Up command is the first command of a debug session where communication with the target is
required. If you receive error messages while executing this command this may have the following reasons.
The target has no power.
The pull-up resistor between the JTAG[VCCS] pin and the target VCC is too large.
The target is in reset:

The debugger controls the processor reset and use the RESET line to reset the CPU on every
SYStem.Up. Therefore no external R-C combination or external reset controller is allowed.
There is logic added to the JTAG state machine:

By default the debugger supports only one processor in one JTAG chain. If the processor is only
one member of a JTAG chain the debugger has to be informed about the target JTAG chain
configuration.
There are additional loads or capacities on the JTAG lines
Memory Access Errors

After system up is completed successfully, data can be written to or read from memory. Trying to access
memory not belonging to the memory map of the processor will be refused with the error message:
no memory mapped at address
D:0002000
M-Core Debugger
10
Troubleshooting
FAQ
No information available
Connect a
Nexus Probe to
a PowerTrace
Unit
How do I correctly connect a Nexus Probe to a PowerTrace unit?

A Nexus probe has one, two or three ribbon cables for the connection to the
PowerTrace unit.
The PowerTrace has three connectors which are marked with A, B and C. (C is
close to the black heatsink)
Nexus probe connectors of newer probes are also marked with A, B and C.
Place the appropriate cable into the corresponding connector.
For older probes note the following:
Probes with a single cable: connect the ribbon cable to connector C.
Probes with two cables: connect the upper cable to connecter C, the second
cable underneath to B.
Probes with three cables: connect the upper cable to connecter C, the second
cable underneath to B and the third cable below to connector A. One does not
require an additional JTAG dongle!
Incorrect
Nexus-POD
CPLD Revision
What is the reason for "Incorrect Nexus-POD CPLD revision" message?

There are several reasons for the following message:
Incorrect Nexus-POD CPLD revision - Please call technical support (refer to
AREA)
A wrong T32xxx.EXE has been executed (e.g. Super10.exe for a Copperhead probe)
Just use the right SW.
The current SW contains a new image for the CPLD on the probe.
This reason is very seldom, but it may happen. One have to consider, that it is
just a warning and normally one can continue using the debugger. However only
for the case, the Area window shows a similar "expected CPLD revision
number". It is recommended to contact your next support office. One will get a
SW-Tool and some instructions how to fix it.
The probe is defective.
This reason can be recognized if the expected CPLD revision number is totally
different from the current CPLD revision number, or even 0x00000 or 0xFFFFF.
It is a serious reason and requires to send the probe back for repair. Also
contact your local support office first.
M-Core Debugger
11
FAQ
Missing
Address
Information on
Top of the
Trace
Is there any reason why symbol addresses and names are not displayed
from the beginning of the trace?
The Nexus protocol defines that a full address is transferred only occasionally,
just in a Branch-Trace-Sync-Message and Data-Trace-Sync-Message. Most of
the time only the significant portion of the current address is generated in the
device and transferred in a Nexus message. Therefore the address can only be
reconstructed and displayed after occurrence of a Sync-Message in the trace
memory. A Sync messages is generated automatically after 255 messages
latest.
A single Nexus message without knowing what had happened before is useless!
Look at the T.L /NEXUS , then one will see the location of the DTSM . After that
location the address information is visible.
A Sync message could be missing on top of the trace in the following cases:
Any time Program is running before trace is in ARM state!
Normally if analyzer is armed manually!
In FIFO mode if trace memory overflows.
Selective trace using Watchpoints
Selective trace using CTU
Some other cases.
Nexus
Connector
Pinout on
Target
I don't know exactly which signals from MCU must be connected to which
signal on the AUX-port connector.
Must certain signals be crossed ?
Not at all. The pin out one can find in the manual and at our home page, fits the
description of Nexus standard from the target point of view.
With other words, you have to connect the signals from the device to the
appropriate signals with the same name on the connector. You
must not take care about signal crossing.
M-Core Debugger
12
FAQ
No or wrong
Data in Nexus
Trace
There are no or wrong Nexus Trace entries. What can be wrong ?

There are different reasons for the case the Nexus trace remains empty or the
contents of the trace memory is not correct. Often this happens, if new prototype
targets are used. Provided the Nexus probe is not defective, the Nexus probe target connection should be investigated.
To prevent wrong trace analyzer settings by scripts, enter the command
Analyzer.Reset and disable Performance Analysis , before checking the steps
below.
First check if the Nexus probe or the extension cable is properly connected
to the target.
To be able to trace Nexus messages, the appropriate trace signals must be
activated, available at the connector
and they must fit timing and electrical demands.
Activation of trace signals is the job of the Trace32 SW. The user must not
take care about.
The designer of the target is responsible for the availability of all relevant
Nexus signals, according
to the Nexus standard specifications and the information one can find at the
Lauterbach home page
(Adaptions/Connectors).
It is recommended to check the scheme of the target in case of problems.
The following trace signals (trace clock and status signals) are essential for
trace capture:
MCKO, MSEO0 (and MSEO1 in case it is provided by the CPU). It is
recommended to observe these
signals during real time program execution if the trace record counter does not
change, despite the Analyzer
state is in ARM state. All two (three) signals must change their levels.
Trace data signals (MDO0 ... MDO15 , number depending on the aux port width)
have to follow the same requirements
as the trace clock and control signals, but they can not prevent trace entries.
They just can cause wrong trace entries.
Electrical characteristics are normally given by the device on the target.
Just for the case there are buffer or other circuitry
between the CPU and the trace connector, it is recommended to check signal
integrity regarding signal level and timing
constrains.
A further reason for wrong or no trace data can be, the selected AUX-port width
in the SYSTEM window does not fit to the
aux port width really available at the Nexus connector. That means, if just 4
MDO bits are routed, one can not get proper trace
if 8 bit MDO mode is selected in the System window. The debugger and trace
does not know which port width the user intends
to use. It must be selected manually.
M-Core Debugger
The following hints

may help
to findGmbH
connection and signal level dependent
1989-2016
Lauterbach
issues.
13
FAQ
Target Aux Port

Connector
Location and
Extension
Cables
Can I use a longer extension cable?

Often customer ignore the warnings regarding the locaction of the aux port
connector and regarding additional extension cables between the debugger and
the target.
This can cause a lot of trouble, especially for high speed applications. We
strongly recommend to place the aux port connector as close as possible
nearby the CPU. As closer as better. Take care about the signal trace length.
Do not connect aux port signals to other connectors than the aux port connector
and prevent signal stubs. Connect a proper termination to the signals coming
from the probe, close to the CPU. Signals from the CPU to the probe should not
be terminated.
One can add 0 Ohm resistors in line of each Nexus signal close to the CPU. If
necessary 0 Ohm can be replaced by a better value.
The debugger does normally not need any pull-up or pull-down, except for reset.
Care must just be taken just for non-Nexus signals. Bear in mind that the target
needs possibly a pull-up or pull-down for certain signals if the debugger is not
connected.
Pay attention about the recommendations of the device manufacturer regarding
the circuitry around the Nexus Aux port.
We also recommend to use no other extension cables than the cables which
come with the debugger.
If possible do not use additional cables at all. Longer cables may work, but must
not. It is the customers risk to use longer once as recommended. We can not
guarantee proper operation.
M-Core Debugger
14
FAQ
Configuration
System Overview
HUB
PC or
Workstation
100 MBit Ethernet
Target
Debug Cable
PODBUS IN
TRIG
POWER DEBUG / ETHERNET

LAUTERBACH
RECEIVE
COLLISION
PODBUS OUT
JTAG
Connector
ETHERNET
CON ERR
DEBUG CABLE
TRIGGER
TRANSMIT
POWER
7-9 V
LAUTERBACH
EMULATE
RECORDING
DEBUG CABLE
RESERVED FOR POWER TRACE
SELECT
USB
Ethernet
Cable
POWER
POWER DEBUG / ETHERNET
AC/DC Adapter
PC
Target
Debug Cable
PODBUS IN
USB
Cable
POWER DEBUG INTERFACE / USB2
POWER
DEBUG CABLE
USB
POWER
7-9 V
LAUTERBACH
SELECT
EMULATE
DEBUG CABLE
TRIG
PODBUS OUT
JTAG
Connector
LAUTERBACH
POWER DEBUG INTERFACE / USB 2

AC/DC Adapter
M-Core Debugger
15
Configuration
Runtime Measurement
The command RunTime allows run time measurement based on polling the CPU run status by software.
Therefore the result will be about few milliseconds higher than the real value.
If the signal DE is available on the JTAG connector, the measurement will automatically be based on this
hardware signal which delivers very exact results. Please do not disable the option SYStem.Option DE.
Memory Classes
The following memory classes are available:
Memory Class
Description
Program
Data
NC
No Cache (only physically memory)
Memory Coherency
Memory coherency on access to following memory classes.
Physical Memory
NC:
Yes
D:
Yes
P:
Yes
Restarting the CPU afterwards.
M-Core Debugger
16
Configuration
General SYStem Settings for the Debugger
SYStem.BdmClock
Define JTAG clock
Obsolete command syntax. Use SYStem.JtagClock instead.
SYStem.CONFIG
The SYStem.CONFIG commands are used to configure the behavior of the complete target system for
debugging, e.g., the Debug Interface or the chaining of several CPUs.
This command replaces the SYStem.MultiCore command and uses exactly the same parameters.
SYStem.CONFIG
Configure debugger according to target topology
Format:
SYStem.CONFIG <parameter> <number_or_address>

SYStem.MultiCore <parameter> <number_or_address> (deprecated)
<parameter>
(General):
state
CORE
(JTAG):
DRPRE <bits>
DRPOST <bits>
IRPRE
<bits>
IRPOST <bits>
TAPState <state>
TCKLevel <level>
TriState [ON | OFF]
Slave
[ON | OFF]
<core>
The four parameters IRPRE, IRPOST, DRPRE, DRPOST are required to inform the debugger about the
TAP controller position in the JTAG chain, if there is more than one core in the JTAG chain (e.g. ARM +
DSP). The information is required before the debugger can be activated e.g. by a SYStem.Up. See Daisychain Example.
For some CPU selections (SYStem.CPU) the above setting might be automatically included, since the
required system configuration of these CPUs is known.
M-Core Debugger
17
TriState has to be used if several debuggers (via separate cables) are connected to a common JTAG port
at the same time in order to ensure that always only one debugger drives the signal lines. TAPState and
TCKLevel define the TAP state and TCK level which is selected when the debugger switches to tristate
mode. Please note: nTRST must have a pull-up resistor on the target, TCK can have a pull-up or pull-down
resistor, other trigger inputs needs to be kept in inactive state.
Multicore debugging is not supported for the DEBUG INTERFACE (LA-7701).
M-Core Debugger
18
state
Show multicore settings.
CORE
For multicore debugging one TRACE32 GUI has to be started per core.
To bundle several cores in one processor as required by the system this
command has to be used to define core and processor coordinates within
the system topology.
Further information can be found in SYStem.CONFIG.CORE.
DRPRE
(default: 0) <number> of TAPs in the JTAG chain between the core of

interest and the TDO signal of the debugger. If each core in the system
contributes only one TAP to the JTAG chain, DRPRE is the number of
cores between the core of interest and the TDO signal of the debugger.
DRPOST
(default: 0) <number> of TAPs in the JTAG chain between the TDI signal
of the debugger and the core of interest. If each core in the system
contributes only one TAP to the JTAG chain, DRPOST is the number of
cores between the TDI signal of the debugger and the core of interest.
IRPRE
(default: 0) <number> of instruction register bits in the JTAG chain

between the core of interest and the TDO signal of the debugger. This is
the sum of the instruction register length of all TAPs between the core of
interest and the TDO signal of the debugger.
IRPOST
(default: 0) <number> of instruction register bits in the JTAG chain

between the TDI signal and the core of interest. This is the sum of the
instruction register lengths of all TAPs between the TDI signal of the
debugger and the core of interest.
TAPState
(default: 7 = Select-DR-Scan) This is the state of the TAP controller when

the debugger switches to tristate mode. All states of the JTAG TAP
controller are selectable.
TCKLevel
(default: 0) Level of TCK signal when all debuggers are tristated.
TriState
(default: OFF) If several debuggers share the same debug port, this
option is required. The debugger switches to tristate mode after each
debug port access. Then other debuggers can access the port. JTAG:
This option must be used, if the JTAG line of multiple debug boxes are
connected by a JTAG joiner adapter to access a single JTAG chain.
Slave
(default: OFF) If more than one debugger share the same debug port, all
except one must have this option active.
JTAG: Only one debugger - the master - is allowed to control the signals
nTRST and nSRST (nRESET).
M-Core Debugger
19
Daisy-chain Example
TDI
Core A
Core B
Core C
Chip 0
Core D
TDO
Chip 1
Below, configuration for core C.

Instruction register length of
Core A: 3 bit
Core B: 5 bit
Core D: 6 bit
SYStem.CONFIG.IRPRE 6
; IR Core D
SYStem.CONFIG.IRPOST 8
; IR Core A + B
SYStem.CONFIG.DRPRE 1
; DR Core D
SYStem.CONFIG.DRPOST 2
; DR Core A + B
SYStem.CONFIG.CORE 0. 1.
; Target Core C is Core 0 in Chip 1
M-Core Debugger
20
TapStates
0
Exit2-DR
Exit1-DR
Shift-DR
Pause-DR
Select-IR-Scan
Update-DR
Capture-DR
Select-DR-Scan
Exit2-IR
Exit1-IR
10
Shift-IR
11
Pause-IR
12
Run-Test/Idle
13
Update-IR
14
Capture-IR
15
Test-Logic-Reset
M-Core Debugger
21
SYStem.CONFIG.CORE
Assign core to TRACE32 instance
Format:
SYStem.CONFIG.CORE <coreindex> <chipindex>

SYStem.MultiCore.CORE <coreindex> <chipindex> (deprecated)
<chipindex>:
1i
<coreindex>:
1k
Default coreindex: depends on the CPU, usually 1. for generic chips

Default chipindex: derived from CORE= parameter of the configuration file (config.t32). The CORE
parameter is defined according to the start order of the GUI in T32Start with ascending values.
To provide proper interaction between different parts of the debugger the systems topology must be mapped
to the debuggers topology model. The debugger model abstracts chips and sub-cores of these chips. Every
GUI must be connect to one unused core entry in the debugger topology model. Once the SYStem.CPU is
selected a generic chip or none generic chip is created at the default chipindex.
None Generic Chips
None generic chips have a fixed amount of sub-cores with a fixed CPU type.
First all cores have successive chip numbers at their GUIs. Therefore you have to assign the coreindex and
the chipindex for every core. Usually the debugger does not need further information to access cores in
none generic chips, once the setup is correct.
Generic Chips
Generic chips can accommodate an arbitrary amount of sub-cores. The debugger still needs information
how to connect to the individual cores e.g. by setting the JTAG chain coordinates.
Start-up Process
The debug system must not have an invalid state where a GUI is connected to a wrong core type of a none
generic chip, two GUI are connected to the same coordinate or a GUI is not connected to a core. The initial
state of the system is value since every new GUI uses a new chipindex according to its CORE= parameter
of the configuration file (config.t32). If the system contains fewer chips than initially assumed, the chips must
be merged by calling SYStem.CONFIG.CORE.
M-Core Debugger
22
SYStem.CPU
Selects the CPU
Format:
SYStem.CPU <cpu>
<cpu>:
MMC2001 | MMC2107 | MMC2112 | MMC2113 | MMC2114 |

M310 | M340 | M3401
Selects the processor type.
M-Core Debugger
23
SYStem.CpuAccess
Format:
Run-time memory access (intrusive)
SYStem.CpuAccess Enable | Denied | Nonstop
Default: Denied.
Enable
Allow intrusive run-time memory access.

In order to perform a memory read or write while the CPU is executing the
program the debugger stops the program execution shortly. Each short stop
takes 1 100 ms depending on the speed of the debug interface and on the
number of the read/write accesses required.
A red S in the state line of the TRACE32 screen indicates this intrusive behavior
of the debugger.
Denied
Lock intrusive run-time memory access.
Nonstop
Lock all features of the debugger, that affect the run-time behavior.
Nonstop reduces the functionality of the debugger to:
run-time access to memory and variables
trace display
The debugger inhibits the following:
to stop the program execution
all features of the debugger that are intrusive (e.g. action Spot for breakpoints, performance analysis via StopAndGo mode, conditional breakpoints etc.)
M-Core Debugger
24
SYStem.JtagClock
Sets JTAG clock frequency
Format:
SYStem.JtagClock <rate>
<fixed>:
1 000 000. 15 000 000.
Selects the frequency for the debug interface.

The default frequency is 1 MHz.
NOTE:
Buffers, additional loads or high capacities on the JTAG/COP lines can reduce
the debug speed.
SYStem.LOCK
Format:
Tristate the JTAG port
SYStem.LOCK [ON | OFF]
Default: OFF.
LOCK must be switched on, if several debuggers are used to debug several Cores using the same JTAG
connector. By locking the debug lines for certain cores another debugger can own mastership on the JTAG
interface.
It must be ensured that the state of the MCORE JTAG state machine remains unchanged while the system
is locked.
M-Core Debugger
25
SYStem.MemAccess
Real-time memory access (non-intrusive)
Format:
SYStem.MemAccess CPU | Denied<cpu_specific>

SYStem.ACCESS (deprecated)
CPU
Real-time memory access during program execution to target is enabled.
Denied
Real-time memory access during program execution to target is disabled.
Default: Denied.
This option declares if and how a non-intrusive memory access can take place while the CPU is executing
code. Although the CPU is not halted, run-time memory access creates an additional load on the
processors internal bus.
The run-time memory access has to be activated for each window by using the memory class E: (e.g.
Data.dump E:0x100) or by using the format option %E (e.g. Var.View %E var1). It is also possible to activate
this non-intrusive memory access for all memory ranges displayed on the TRACE32 screen by setting
SYStem.Option DUALPORT ON.
M-Core Debugger
26
SYStem.Mode
Establish the communication with the target
Format:
SYStem.Mode <mode>
<mode>:
Down
NoDebug
Go
Attach
Up
StandBy
The communication between the debugger and the target is established.

Down
Disables the debugger. The state of the CPU remains unchanged.
NoDebug
Resets the target with debug mode disabled. The CPU acts like no debugger is
connected.
Go
Resets the target with debug mode enabled. Afterwards the CPU starts
executing the code.
The CPU can be stopped with the break command or until any break condition
occurs.
Attach
User program remains running (no reset) and the debug mode is activated.
After this command the user program can be stopped with the break command
or if any break condition occurs.
Up
Resets the target (HRESET line) and sets the CPU to debug mode. The CPU
stops at the reset vector afterwards.
StandBy
Not implemented.
M-Core Debugger
27
SYStem.Option DE
Stop CPU via debug enable line
Format:
SYStem.Option DE [ON | OFF]
ON (default)
The debugger stops the CPU via the Debug Enable line.
OFF
The debugger stops the CPU by transferring a special command via the JTAG
interface.
OFF is only recommended if stopping the CPU via the Debug Enable line is not
possible.
SYStem.Option DUALPORT
Format:
Update all memory displays during runtime
SYStem.Option DUALPORT [ON | OFF]
Default: OFF.
ON
(NEXUS only)
Switches the run-time memory access to ON for all windows that display
memory. Use this option if you want all windows to be updated while the
processor is running. This setting has no effect if SYStem.Option.MemAccess
is denied.
SYStem.Option IMASKASM
Format:
Disable interrupts while single stepping
SYStem.Option IMASKASM [ON | OFF]
Default: OFF.
If enabled, the interrupt mask bits of the CPU will be set during assembler single-step operations. The result
is that interrupts are not accepted during single-step operations. After each single step the interrupt mask
bits are restored to the value before the step.
M-Core Debugger
28
SYStem.Option IMASKHLL
Format:
Disable interrupts while HLL single stepping
SYStem.Option IMASKHLL [ON | OFF]
Default: OFF.
If enabled, the interrupt mask bits of the CPU will be set during HLL single-step operations. The result is that
interrupts are not accepted during HLL single-step operations. After each HLL single step the interrupt mask
bits are restored to the value before the step.
SYStem.Option PC
Format:
Not supported command
SYStem.Option PC <addr>
Default address: 0N.

Not supported.
SYStem.Option TRST
Use TRST line to reset the TAP controller
Format:
SYStem.Option TRST [ON | OFF]
ON (default)
Use the TRST line to reset the TAP controller.
OFF
The TAP will be reset by shifting in an adequate TMS sequence.

OFF is only recommended if resetting the TAP controller via the TRST line is
not possible.
M-Core Debugger
29
Trigger On-chip Commands
TrOnchip.CYcle
Define access type
Format:
TrOnchip.A.CYcle <cycle>
TrOnchip.B.CYcle <cycle>
<cycle>:
ANY
Read
Write
Access
Execute
Defines on which cycle the ICE breaker stops the program execution.
ANY
Cycle type doesn't matter.
Read
Stop the program execution on a read access.
Write
Stop the program execution on a write access.
Access
Stop the program execution on a read or write access.
Execute
Stop the program execution on an instruction is executed.
M-Core Debugger
30
TrOnchip.A.Address
Define address selector
Format:
TrOnchip.A.Address <selector>
TrOnchip.B.Address <selector>
<selector>:
OFF
Alpha
Beta
Charly
The address/range for an address selector can not be defined directly. Set an breakpoint of the type Alpha,
Beta or Charly to the address/range.
OFF
No trigger signal will be generated.
Alpha
Use Alpha breakpoint as address selector for selected unit.
Beta
Use Beta breakpoint as address selector for selected unit.
Charly
Use Charly breakpoint as address selector for selected unit.
.
Break.Set 1000 /Alpha
TrOnchip.A.Address Alpha
; set an Alpha breakpoint to 1000

; use Alpha breakpoint as address
; selector for the unit A
Var.Break.Set flags[3] /Beta

TrOnchip.B.Address Beta
; set a Beta breakpoint to flags[3]

; use Beta breakpoint as address
; selector for the unit B
M-Core Debugger
31
TrOnchip.CONVert
Adjust range breakpoint in on-chip resource
Format:
TrOnchip.CONVert [ON | OFF]
The on-chip breakpoints can only cover specific ranges. If a range cannot be programmed into the
breakpoint it will automatically be converted into a single address breakpoint when this option is active. This
is the default. Otherwise an error message is generated.
TrOnchip.CONVert ON
Break.Set 0x1000--0x17ff /Write
; sets breakpoint at range

; 1000--17ff sets single breakpoint
; at address 1001
TrOnchip.CONVert OFF
; sets breakpoint at range

; 1000--17ff
; gives an error message
TrOnchip.EXTernal
Format:
Generate a trigger for trace on high pulse on in0 or in1
TrOnchip EXTernal OFF | IN0 | IN1
Generates a trigger for the trace on a high pulse (at least 20 ns) on the IN0 or IN1 connector of the NEXUS
adapter. IN0 and IN1 are ORed for the trigger.
OFF
No trigger signal will be generated.
IN0
Generate a trigger signal on IN0.
IN1
Generate a trigger signal on IN1.
M-Core Debugger
32
Example: Stop the sampling to the trace if a high pulse is recognized at IN0.
TrOnchip.EXTernal IN0
; Enable IN0 as trigger source for the trace
Go
; Start the program execution
TrOnchip.Mode
Configure unit A and B
Format:
TrOnchip.Mode <mode>
<mode>:
AORB
AANDB
BAFTERA
Not yet implemented.

Defines the way in which unit A and B are used together.
AORB
Stop the program execution if unit A or unit B match.
AANDB
Stop the program execution if both units match.
BAFTERA
Stop the program execution if first unit A and then unit B match.
M-Core Debugger
33
TrOnchip.VarCONVert
Format:
Adjust complex breakpoint in on-chip resource
TrOnchip.VarCONVert [ON | OFF]
The on-chip breakpoints can only cover specific ranges. If you want to set a marker or breakpoint to a
complex variable, the on-chip break resources of the CPU may be not powerful enough to cover the whole
structure. If the option TrOnchip.VarCONVert is ON the breakpoint will automatically be converted into a
single address breakpoint. This is the default setting. Otherwise an error message is generated.
TrOnchip.RESet
Format:
Set on-chip trigger to default state
TrOnchip.RESet
Sets the TrOnchip settings and trigger module to the default settings.
TrOnchip.view
Format:
Display on-chip trigger window
TrOnchip.view
Opens the TrOnchip window.
M-Core Debugger
34
JTAG Connector
Signal
TDI
TDO
TCLK
(GPIO-SI-)
RESETVDD TARGET
(!GPIO-SO)
Pin
1
3
5
7
9
11
13
Pin
2
4
6
8
10
12
14
Signal
GND
GND
GND
N/C
TMS
DETRST-
This is a standard 14 pin double row (two rows of seven pins) connector (pin to pin spacing: 0.100 in.).
(Signals in brackets are not strong necessary for basic debugging, but its recommended to take in
consideration for future designs.)
M-Core Debugger
35
JTAG Connector
Technical Data
Operation Voltage
This list contains information on probes available for other voltage ranges. Probes not noted here supply an
operation voltage range of 4.5 5.5 V.
Adapter
OrderNo
Voltage Range
ONCE Debugger for M-CORE (ICD)
LA-7745
2.5 .. 5.5 V
M-Core Debugger
36
Technical Data
Support
M310
MMC2001
MMC2107
MMC2112
MMC2113
MMC2114
INSTRUCTION
SIMULATOR
POWER
INTEGRATOR
ICD
TRACE
ICD
MONITOR
ICD
DEBUG
FIRE
ICE
CPU
Available Tools
YES
YES
YES
YES
YES
YES
Compilers
Language
Compiler
GNU-C
C
C
Company
Free Software
Foundation, Inc.
HICROSS-MCORE NXP Semiconductors
D-CC
Wind River Systems
Option
Comment
ELF/DWARF
ELF/DWARF
ELF/DWARF
Realtime Operation Systems

Name
Company
Comment
Nucleus
OSEK
ProOSEK
Mentor Graphics Corporation

Elektrobit Automotive GmbH
via ORTI
via ORTI
M-Core Debugger
37
Support
3rd Party Tool Integrations

CPU
Tool
Company
ALL
ALL
ALL
ADENEO
X-TOOLS / X32
CODEWRIGHT
ALL
CODE CONFIDENCE
TOOLS
CODE CONFIDENCE
TOOLS
EASYCODE
ECLIPSE
RHAPSODY IN MICROC
RHAPSODY IN C++
CHRONVIEW
LDRA TOOL SUITE
UML DEBUGGER
Adeneo Embedded
blue river software GmbH
Borland Software
Corporation
Code Confidence Ltd
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ATTOL TOOLS
VISUAL BASIC
INTERFACE
LABVIEW
CODE::BLOCKS
C++TEST
RAPITIME
DA-C
TRACEANALYZER
SIMULINK
TA INSPECTOR
UNDODB
VECTORCAST UNIT
TESTING
VECTORCAST CODE
COVERAGE
WINDOWS CE PLATF.
BUILDER
Host
Windows
Windows
Windows
Code Confidence Ltd
Linux
EASYCODE GmbH
Eclipse Foundation, Inc
IBM Corp.
IBM Corp.
Inchron GmbH
LDRA Technology, Inc.
LieberLieber Software
GmbH
MicroMax Inc.
Microsoft Corporation
Windows
Windows
Windows
Windows
Windows
Windows
Windows
Windows
Windows
NATIONAL
INSTRUMENTS
Corporation
Open Source
Parasoft
Rapita Systems Ltd.
RistanCASE
Symtavision GmbH
The MathWorks Inc.
Timing Architects GmbH
Undo Software
Vector Software
Windows
Windows
Windows
Windows
Windows
Windows
Windows
Linux
Windows
Vector Software
Windows
Windows
Windows
M-Core Debugger
38
Support
Products
Product Information
OrderNo Code
Text
LA-7745
ONCE-MCORE
supports M-CORE derivatives

includes software for Windows, Linux and MacOSX
requires Power Debug Module
debug cable with 14 pin connector
Order Information
Order No.
Code
Text
LA-7745
ONCE-MCORE
M-Core Debugger
39
Products

Debugger Mcore

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M-Core Debugger

TRACE32 Online Help

ICD In-Circuit Debugger ................................................................................................................

Processor Architecture Manuals ..............................................................................................

M-Core Debugger .................................................................................................................

General Note ......................................................................................................................

Brief Overview of Documents for New Users .................................................................

Quick Start JTAG/ONCE ...................................................................................................

Example for Breakpoints

Memory Access Errors

General SYStem Settings for the Debugger ...................................................................

Define JTAG clock

Configure debugger according to target topology

Assign core to TRACE32 instance

Selects the CPU

Run-time memory access (intrusive)

Sets JTAG clock frequency

Tristate the JTAG port

Real-time memory access (non-intrusive)

Establish the communication with the target

Stop CPU via debug enable line

Update all memory displays during runtime

Disable interrupts while single stepping

Disable interrupts while HLL single stepping

Not supported command

Use TRST line to reset the TAP controller

Trigger On-chip Commands .............................................................................................

Define access type

Define address selector

Adjust range breakpoint in on-chip resource

Generate a trigger for trace on high pulse on in0 or in1

Configure unit A and B

Adjust complex breakpoint in on-chip resource

Set on-chip trigger to default state

Display on-chip trigger window

JTAG Connector ................................................................................................................

Technical Data ...................................................................................................................

Realtime Operation Systems

3rd Party Tool Integrations

1989-2016 Lauterbach GmbH

for ( i = 0 ; i <= SIZE ; flags[ i++ ] = TRUE ) ;

for ( i = 0 ; i <= SIZE

1989-2016 Lauterbach GmbH

MCORE xx (2001, 2107, 2112, )

Brief Overview of Documents for New Users

T32Start (app_t32start.pdf): T32Start assists you in starting TRACE32 PowerView instances

General Commands (general_ref_<x>.pdf): Alphabetic list of debug commands.

Choose Help menu > Processor Architecture Manual.

1989-2016 Lauterbach GmbH

To prevent debugger and target from damage it is recommended to connect or

Power ON the TRACE32 hardware.

Start the TRACE32 software to load the debugger firmware.

Connect the debug cable to the target.

Switch the target power ON.

Configure your debugger e.g. via a start-up script.

Switch off the target power.

Disconnect the debug cable from the target.

Close the TRACE32 software.

Power OFF the TRACE32 hardware.

1989-2016 Lauterbach GmbH

Quick Start JTAG/ONCE

Select the device prompt B: for the ICD Debugger.

Select the CPU type to load the CPU specific settings.

Tell the debugger wheres FLASH/ROM on the target.