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# EE 420L

Electronics II Laboratory
Laboratory Exercise #6
Differential Amplifier
Department of Electrical and Computer Engineering
University of Nevada, at Las Vegas
Objective:
The purpose of this lab is to understand characteristics of Bipolar and MOS differential
amplifier.
Equipment Usage
For this lab the following equipment will be used:
Power supply
Multi-meter
Connection wires
Oscilloscope
Function Generator
NTE 2321, NTE2322 and CD4007 transistor array
Background:
Differential amplifier is the basic building block of op-amp and finds extensive use in the
integrated circuit design. Function of the differential amplifier is to amplify the difference
between two input signals and reject common mode signal. As a result, differential
amplifier can operate in noisy environment as it can reject common mode noise. Basic
differential amplifier circuits are shown on Figure 6-1.
VCC

VCC

RC1

RC2

OutIN+
Vin+
1kHz

Rsi1

RD1

Out+

Out-

Q2
B1

Q1

B2
E1

Rsi2

IN-

IN+
Vin1kHz

Rsi1

Vin+
1kHz

Vbias

Q3

RD2

G1

Out+

Q1

Q2

Rsi2

S
Vbias

E1

REE

VEE

VEE

a) BJT Based

b) MOS Based
Figure 6-1

INVin1kHz

Q3

E2

G2

When both signals are equal, both output voltages are equal since both transistor conducts
same current. As a result, difference between the output signals is zero just like the input
signal. When one of the signals rises higher than the other, it steers more current thru the
transistor connected to it and current thru other transistor decreases since we are limited
with constant current supplied by the current source Q3. Therefore, difference in the
output voltages increases. Figure 6-2 shows current flow thru Q1 and Q2 as we apply
differential signal at the input.

Figure 6-2
Differential voltage gain Adm = -gm*RC (for BJT amp); Adm = -gm*RD (for MOS amp);
Common mode Voltage Gain:
Due to finite current source impedance, transistor mismatch and load mismatch,
differential amplifier would have finite common mode voltage gain.
Considering only finite current source output impedance Ro, common mode voltage gain
is as follows:
ACM = -gm*RC/(1+2gm*Ro) (for BJT diff amp); where gm = ICQ/VT
ACM = -gm*RD/(1+2gm*Ro) (for MOS diff amp); where gm = 2IDQ/2IDQ/(VGSQ-VT)
Common mode rejection ratio CMRR = 20*log[Adm/Acm]
Differential mode and Common mode Input Resistance for BJT Diff-amp
Differential mode input impedance is as follows:
Rid = 2[ r + (1 + ) RE ] , where RE is degeneration resistor
Common mode input impedance is as follows:

1
Ricm = [r || (1 + ) Ro || (1 + )ro ] ,where r0 is the output impedance of the input transistor
2
and Ro is the output impedance of the current source.
Differential amplifier with Active Load
To increase the gain of the differential amplifier, we must have large output impedance.
We can implement large resistor with use of active load, saving large chip area. Figure 63 illustrates differential amplifiers with active loads.
VCC

VCC

Q4

Q3

Q5

Q4

Q3

Out

Out
RL

RL

VEE

IN+
Vin+
1kHz

Rsi1

Q2
B1

Q1

B2
E1

Rsi2

IN-

IN+
Vin1kHz

Vin+
1kHz

Vbias

Q6

Rsi1

G1

Q1

Q2
S

Rsi2

INVin1kHz

Vbias

Qss

E2

G2

E1

REE

VEE

VEE

Figure 6-3
Differential mode voltage gains of the amplifiers are as follows:
Adm = gm(r02||r04||RL), where gm = ICQ/VT for BJT amplifier and gm = 2IDQ/(VGSQ-VT)
for MOS amplifier

Design Example - 1:
Design a BJT differential amplifier that meets the following specifications:
Adm = 66 dB = 2000
CMRR = 80 dB = 10000
fu = 10 MHZ when CL = 500 pF
Power Supply = +/- 12V
Vin = 10mV @ 10KHZ
Figure 6-4 shown below is the proposed amplifier:
VCC

Q4
2N3906

Q3
2N3906

Q5
2N3906
Out
VEE

CL
500pF

INP

RS1
50

B1

Q2

Q1
2N3904

2N3904

Vin+
1kHz

RS2

INN

50
VCC

Vin1kHz

E1
RB1
11.666k
QSS

Vb1

2N3904
E3

QB1
2N3904

VEE
VEE

Figure 6-4
Step 1 find the required gm and current of the input pair:
Given unity gain bandwidth of 10 MHz and load capacitance of 500 pF, required gm of
the input differential pair is as follows:
gm
, (since load capacitance dominates all other capacitance)
2C L
g m = 2 *10 MHz * 500 pF = 31.4 mS
fu =

With known gm, we can find the required collector of the input pair using the following
formula:
I CQ
gm =
, ICQ = 817 A.
VT

Lets use collector current of 1mA in our initial design to provide additional flexibility in
meeting the specifications.
IQSS = 2 * ICQ = 2 mA.
RB =

I QSS
VCC VEE VBE
)
, VBE = VT ln(
I QSS
I SS

RB = 11.666 K
Step 2 find the required load output resistance:
Differential mode gain is a function of both input pair trans-conductance and output
impedance as shown on the following equation.

## Adm = g m1, 2 * (r02 || r04 )

With Adm = 2000, we find r02||r04 = 63.7 K.
Output impedance of the transistor is as follows:
ro =

VA
I CQ

Since the early voltage (VA) of the NPN transistor is twice that of PNP transistor, r02||r04 =
r02||(r02/2) = r02/3
Therefore,
r02/3 = 63.7 K;
r02 = 191 K, r02 = 95.5 K
VA2 = r02*ICQ = 191 K * 1 mA = 191 V
VA4 = 95.5 V
Step 3 find the required current source output resistance:
Considering only the finite output impedance of the current source, common voltage gain
of the active load differential amplifier is as follows:
Acm =

g m1, 2

## From the specification above,

CMRR = 80 dB = 10000
Adm = 2000 = gm12*(r02||r04)
Therefore, gm34*Rss = 2.5.
Rss = 2.5/gm34 = 2.5/(1 mA/26 mV) = 65
This low required output impedance is the result of superior common mode rejection
characteristics of differential amplifier with active load.
Design Example - 2:
Design a CMOS differential amplifier that meets the following specifications:
Adm = 30 dB = 32
CMRR = 60 dB = 1000
fu = 10 MHZ when CL = 10 pF
Power Supply = +/- 5 V
Vin = 100mV @ 10KHZ
Figure 6-5 shown below is the proposed amplifier:
VCC

Q3

Q4
P4007

P4007

Out
CL
10pF

INP

RS1
50

Q2

Q1
N4007

N4007

Vin+
1kHz

RS2

VCC
RB1
6.5K
QSS

Vb1

N4007
QB
N4007
VEE
VEE

Figure 6-5
Assume:
W
= 500e 6, Vtn = 1.5V , = .01 ( for NMOS )
Kn
L

INN

50
Vin1kHz

Kp

W
= 500e 6, Vtp = 1.5V , = .04 ( for NMOS )
L

## Step 1 find the required gm and current of the input pair:

Given unity gain bandwidth of 10 MHz and load capacitance of 10 pF, required gm of the
input differential pair is as follows:
gm
, (since load capacitance dominates all other capacitance)
2C L
g m = 2 *10 MHz *10 pF = 628 S
fu =

With known gm, we can find the required collector of the input pair using the following
formula:
W
g m = 2K n I D
L
2
gm
I DQ =
= 395 A.
W
2K n
L

Lets use drain current of .5 mA in our initial design to provide additional flexibility in
meeting the specifications.
IQSS = 2 * IDQ = 1 mA.
Biasing Network:
Drain current of the saturated MOSFET is as follows:
1 Kn W
ID =
(Vgs VT ) 2
2 2 L
Therefore, (Vgs-VT) of the current source is as follows:

Vgs VT =

RB =

2* ID
2 *1 mA
=
= 2 V, Vgs = 3.5 V
W
500
e

6
Kn
L

=
= 6.5 K
I QSS
1 mA

## Step 2 find the required load output resistance:

Differential mode gain is a function of both input pair trans-conductance and output
impedance as shown on the following equation.
Adm = g m1, 2 * (r02 || r04 )

## With Adm = 32, we find r02||r04 = 50 K.

Output impedance of the transistor is as follows:
ro =

1
I D

Since the early voltage (VA) of the NMOS transistor is four that of PNP transistor, r02||r04
= r02||(r02/4) = r03/5
Therefore,
r02/5 = 50 K;
r02 = 250 K, r04 = 62.5 K
2 = 1/(r02*ID2) = 1/(250 K * .5 mA) = .008
4 = 1/(r04*ID4) = 1/(62.5 K * .5 mA) = .032
Device model used is within the range needed to meet the gain specification. Otherwise,
we have to use cascode output to increase output impedance.
Step 3 find the required current source output resistance:
Considering only the finite output impedance of the current source, common voltage gain
of the active load differential amplifier is as follows:
Acm =

g m1, 2

## , RSS is the output impedance of the current source.

CMRR = (1 + 2 g m1, 2 RSS ) g m3, 4 (r02 || ro 4 ) 2 g m1, 2 (ro 2 || ro 4 ) g m 3, 4 RSS
From the specification above,
CMRR = 60 dB = 1000
Adm = 40 dB = 100 = gm12*(r02||r04)
Therefore, gm34*Rss = 5.
Rss = 5/gm34; g m 34 = 2 K n
Rss (required) = 7.07 K

W
I D = 2 * 500e 6 * .5 mA = 707 S
L

## From the device data,

1
1
=
= 100 K
I D .01*1e 3
Therefore, simple current source shown on the initial design is adequate. Otherwise, we
have to use cascode current source to increase output impedance of the current source.
Prelab:
Analysis 1: Design a BJT differential amplifier with NPN input source as shown in
Figure 6-6.
VCC

Q4
NTE2322

Q3
NTE2322
VCC

Q5
NTE2322

VEE
VCC
12V

Out

VEE
-12V

VEE

CL
500pF

INP

RS1
50

B1

Q2

Q1
NTE2321

NTE2321

Vin+
1kHz

RS2

INN

50
VCC

Vin1kHz

E1
RB1
24k
QSS

Vb1

NTE2321
E3

QB1
NTE2321

VEE
VEE

Figure 6-6
Amplifier need to satisfy the following specifications:
ISS = 2 mA (size the resistor RB1 for required current flow)
Assume = 300 and Is = 1.4x10-14
Perform hand calculation to find common mode gain, differential mode gain, common
mode rejection ratio (Adm/Acm), input impedance and output impedance. Find input
common mode range and output common mode range. Perform Spice simulation of the
circuit and compare simulated results with that of hand calculations. Indicate which
input terminal is positive and which terminal is negative and compare input phase with
output phase.
Analysis 2: Design a MOS differential amplifier with NMOS input source as shown in
Figure 6-7.

VCC

VCC

R1
18K

VEE
VCC
5V

R2
18K

VEE
-5V
Outn

Outp
CL1

CL2

10pF
INP

RS1
50

10pF
Q2

Q1
N4007

N4007

Vin+
1kHz

RS2

INN

50
VCC

Vin1kHz

VS
RB1
14K
QSS
Vb1
N4007
QB
N4007
VEE
VEE

Figure 6-7
Amplifier need to satisfy the following specifications:
ISS = 500 uA (size the resistor RB1 for required current flow)
Av > 10
Perform hand calculation to find common mode gain, differential mode gain, common
mode rejection ratio (Adm/Acm), input impedance and output impedance. Find input
common mode range and output common mode range. Perform Spice simulation of the
circuit and compare simulated results with that of hand calculations. Indicate which
input terminal is positive and which terminal is negative and compare input phase with
output phase.
Pre-Lab Deliverables:
1) Submit your completed analysis, schematics, hand calculations and simulation
results.
2) Describe which transistor needs to be matched to have low offset.
3) Differential amplifier requires a single ended to differential circuit if incoming
signal is single ended. Describe a circuit that generates differential signal from a
single ended signal.
4) Which technology BJT or MOS offer higher frequency performance? Explain
Lab Experiments:
Experiment 1: Construct BJT differential amplifier simulated in the pre-lab analysis #1.
Measure common mode gain, differential mode gain, common mode rejection ratio
(Adm/Acm), input impedance and output impedance. AC-couple a 5 K resistor at the
output terminal at mid-band frequency and find gain degradation. Compare measured
values with simulated data and comment on all discrepancies.

Experiment 2: Construct MOS differential amplifier simulated in the pre-lab analysis #2.
Measure common mode gain, differential mode gain, common mode rejection ratio
(Adm/Acm), input impedance and output impedance. Compare measured values with
simulated data and comment on all discrepancies.
Post-Lab Deliverables:
1) Submit your completed analysis, measured data and the lesson learned from
performing this lab.
2) Why input impedance is low for common gate and common base amplifier? What
are the typical applications for such amplifiers?
3) What is the benefit of source (emitter) degeneration resistor?