Transmission Line Protection

Alpha Plane and 87L Over Ethernet

Schweitzer Engineering Laboratories, Inc.

Copyright SEL 2015

Benefits of line current differential

Good performance on

Short lines

Three-terminal lines

Series-compensated lines

Immunity to changing system conditions

High sensitivity
Current-only scheme
Not affected by non-standard sources
Ease of engineering

411L Line Current Differential Relay

Based on SEL-421 (421 with the 87L)
Tried and true alpha plane principle
Multi-terminal applications (3 or 4)
Dual breaker terminals
Asymmetrical channels
In-line transformers
Sub-cycle operation
Line charging current compensation

Communication and I/O Capabilities

Two 87L serial
ports: 422, C37.94,
direct fiber, G.703

Ethernet for IEC

61850 GM, SCADA,
Eng Access

Serial for Mirrored

BitsTM, SCADA,
Eng Access

IRIG-B for 87L

external time
synch

Two 87L
Ethernet ports

400-series I/O boards

Dual CT input

Dual VT input

Typical implementations of 87L

Relay 2

iTX
iRX

Frequency
tracking

Alignment

iD

A/D

iA

iDIF
87L trip
equations
Logic

OUT

87L Protection Function

(ALPHA PLANE)

Current Differential Protection

I2

I3

I1

Zone of differential
protection
I4

...

IN

Traditional issues
Speed
CT saturation
CT trouble
Partial differential

Line Current Differential Protection

New issues due to physical dimension

Distributed scheme
Need wide-area communications
Need to align currents
Channel availability and misbehavior
Time sources, if used
Line-charging current and reactors
High-resistive faults and sensitivity

What Is the Alpha Plane?

Consider a two-current line differential zone

Express the two currents as a complex

ratio

Alpha Plane is the graphical

representation of that ratio

Load Current in Alpha Plane

lm(k)

Re(k)

IL

IR

Load Current in Alpha Plane

lm(k)

Re(k)

Synchronization Errors
lm(k)

Re(k)

IR

IL

CT Saturation
lm(k)

Re(k)

IL

IR

Internal Faults
lm(k)

Re(k)

IL

IR

Internal Faults With Outfeed

lm(k)

Re(k)

Internal Faults With Outfeed

lm(k)

IL
Re(k)

IR

Alpha Plane Operate / Restrain

lm(k)
Internal faults
Synchronism
errors
CT saturation
Re(k)

Internal faults

Benefits of the Alpha Plane

Great immunity
to synchronization
errors

lm(k)

Re(k)
1

Immunity to
CT saturation
High-speed
operation
Easy to test

Percentage Differential Versus Alpha Plane

lm(k)
Differential
Slope (s)

Re(k)

OPERATE

1
RESTRAIN

Restraint

Percentage Differential Versus Alpha Plane

lm(k)
Differences
between two
characteristics

Percentage slope
characteristic

Re(k)

Percentage Differential Versus Alpha Plane

lm(k)
Differences
between two
characteristics

Re(k)

Percentage Differential Versus Alpha Plane

lm(k)
Differences
between two
characteristics

Re(k)

Challenges Percentage
Differential or Alpha Plane
Differential zones with more than two
currents
Fast and deep CT saturation how to
detect external faults?
Charging current compensation how?
In-line transformers how?

87L With More Than Two Currents

How do we define the alpha plane for 6 currents?

Can we avoid communicating all currents to
all terminals?

Multiterminal Alpha Plane

k=

IL EQ
IR EQ

I2
I1
I3

IDIF(N)
IRST(N)
IN

I4

Multiterminal Alpha Plane

3-Terminal Application

2-Terminal Application

IRST
IDIF

I3

I1
I2

Real

IRST
IDIF

Real

Manipulation of Ires and Idiff

External Fault Detection
Harmonic RESTRAINT

External fault detection

iDIF

abs

+
-

1-cycle
buffer

EFD

3/16cyc

DPO

abs

iRST

+
1-cycle
buffer

iDIF

Internal

iDIF External

iRST

iRST

External fault detection

T1 is guaranteed to
detect the fault as
external

iRST(T1) = | iCT-1 | + | iCT-2 | + | iCT-3 + iCT-4 | + | iCT-5 + iCT-6 |

iRST(T2) = | iCT-1 + iCT-2 | + | iCT-3 | + | iCT-4 | + | iCT-5 + iCT-6 |
iRST(T3) = | iCT-1 + iCT-2 | + | iCT-3 + iCT-4 | + | iCT-5 | + | iCT-6 |

External fault detection

10

Dual-CB Example
Alpha Plane working with currents
from all CTs and external fault detector
4

Imaginary

-2

-4
-4

-2

0
Real

iCT-1, A

External fault detection

CT-1

i, A

iCT-2, A

CT-2

iCT-1, A

External fault detection

CT-1

i, B-phase, A

i, A-phase, A

iCT-2, A

CT-2

11

iCT-1, A

External fault detection

CT-1

i, A

iCT-2, A

CT-2

Security for external faults

Restraint signals (P/Q/G) notion of a through
current
External fault detection logic
When EFD bit asserted:

Harmonic restraint added

Phase restraint boosts the Q and G restraints

Extra security from alpha plane

Security for external faults

Alpha plane working with currents
from the two CTs summed with no Harmonic restraint
4

Imaginary

-2

-4
-4

-2

0
Real

12

Security for external faults

Alpha plane working with currents
from all CTs (proper restraint)

Imaginary

-2

-4
-4

-2

0
Real

Imaginary

-2

-4
-4

-2

0
Real

Security for external faults

Alpha plane working with currents
from all CTs and External Fault Detector

Imaginary

-2

-4
-4

-2

0
Real

Imaginary

Imaginary

-2

-4
-4

-2

0
Real

-2

-4
-4

-2

0
Real

SEL-411L
87L Over Ethernet

Copyright SEL 2015

SEL Confidential

13

87L Channels
Serial versus Ethernet
Copper versus fiber
Interface (C37.94 fiber, 422, G.703)
Data rate (56 kbps, 64 kbps, Nx64 kbps)
Direct (point-to-point) fiber versus multiplexed
Symmetrical versus asymmetrical

Channel Requirements
Availability (present and working as
expected)
Low latency
Security (low bit-error rates)
Symmetrical versus asymmetrical
Compatibility of interface
Low losses if direct long-haul fiber

87L Current Alignment

Currents stamped with local relay clocks
Alignment based on local time and offset
Channel-based synchronization

Clock offset measured using ping-pong algorithm

Requires symmetrical channels

External time-based synchronization

Clock offset known to be zero

Works for symmetrical and asymmetrical channels

14

SEL-411L 87L via Ethernet

Two CT inputs per line terminal (scalable)
Maximum of four line terminals at present
(scalable)

More line terminals will Not decrease speed

32 transmit bits per terminal (scalable)

No impact on protection settings
Seven new communications settings

TDM vs Ethernet

87L via Dedicated Ethernet

15

87L via Ethernet Over TDM

MUX

Ethernet
IRIG-B
MUX = Multiplexer

87L

MUX

MUX

87L

87L

87L
MUX

Multiterminal Applications
Using Ethernet Over TDM
87L
(2)

87L
(1)

87L
(3)
87L
(4)

87L
(N)

Segregating Data Services

(Bandwidth Allocation)
Ethernet

WAN Transport
Bandwidth
Protection
TDM

16

Adjust 87ETHJT Setting

STATISTICS
Time Status
High Lost Packet Count
Receive Delay (ms)
Lost Packet Count 40s
Lost Packet Count 24hr

Channel 1
Locked
OK
0.2
0
1786

Channel 2
Locked
OK
0.3
0
1881

MAXIMUM VALUES
Channel 1
Lost Packet Count 24hr
Receive Delay (ms)

1786
1.9

Date and Time (UTC)

01/06/2015 02:50:29
01/06/2015 02:51:01.303

Channel 2
Lost Packet Count 24hr
Receive Delay (ms)

1881
2.0

Date and Time (UTC)

01/06/2015 02:50:29
01/06/2015 02:51:01.303

Channel 3
Lost Packet Count 24hr
Receive Delay (ms)

2296
2.0

Date and Time (UTC)

01/06/2015 02:50:29
01/06/2015 02:51:01.303

HISTOGRAMS
Channel Receive Delay (last 24 hours)
Delay (ms)
Channel 1 (%)
0 - 2
100.0
2 - 4
0.0
4 - 6
0.0
6 - 8
0.0
8 - 10
0.0

Channel 2 (%)
100.0
0.0
0.0
0.0
0.0

Channel 3
Locked
OK
0.4
0
2296

Channel 3 (%)
100.0
0.0
0.0
0.0
0.0

Questions?

17