Question 1: Code for dff using structural style:

entity dff is
port(d,clk: in bit;q,qn:buffer bit);
end dff;

architecture struc of dff is

signal s1,s2,s3,s4, clkbar:bit;
component nor2
port(a,b:in bit;z:out bit);
end component;
component nor3
port(a,b,c:in bit;z:out bit);
end component;
component inv
port(a:in bit;z:out bit);
end component;

begin

I1:inv port map(clk, clkbar);

X1:nor2 port map(d, s2,s1);
X2:nor3 port map(s1,s3,clkbar,s2);
X3:nor2 port map(s4,clkbar,s3);
X4:nor2 port map(s1,s3,s4);
X5:nor2 port map(s3,qn,q);
X6:nor2 port map(s2,q,qn);
end struc;

Codes for components used in the main dff code:

entity nor2 is
port(a,b:in bit;z:out bit);
end nor2;
architecture df of nor2 is
begin
z<=a nor b after 1ns;
end df;

entity nor3 is
port(a,b,c:in bit;z:out bit);
end nor3;
architecture df of nor3 is
begin
z<=not(a or b or c) after 1ns;
end df;

entity inv is

port(a:in bit;z:out bit);

end inv;
architecture df of inv is
begin
z<= not a;
end df;

i)

D flip flop
Z1
0
0
0
0
1
1
1
1

Z0
0
0
1
1
0
0
1
1

X
0
1
0
1
0
1
0
1

Z1
0
0
1
0
0
1
1
0

D0 = Z0; D1 = Z0.X+Z1.Z0.X; Y = Z1.Z0.X

Z0
0
1
0
1
0
1
0
1

D1
0
0
1
0
0
1
1
0

D0
0
1
0
1
0
1
0
1

Y
0
0
0
0
0
0
0
1

Code: Assume all necessary components are provided and just follow the circuit diagram.
entity d_flipflop is
port(x,clk: in bit; y: out bit);
end d_flipflop;
architecture struc of d_flipflop is
signal xn,s2,s3,s4,s0,s0n,s1,s1n:bit;
component d_flip
port(d,clk:in bit; q, qn:out bit);
end component;
component AND2
port(a,b :in bit;z:out bit);
end component;
component AND3
port(a,b,c:in bit; z:out bit);
end component;
component OR2
port(a,b:in bit; z:out bit);
end component;
component INVERTER
port(a:in bit; z:out bit);
end component;
begin

X1:INVERTER port map(x,xn);

X2:AND2 port map(s1,xn,s2);
X3:AND3 port map(s0,x,s1n,s3);
X4:OR2 port map(s2,s3,s4);
X5:d_flip port map(s4,clk,s0,s0n);
X6:d_flip port map(x,clk,s1,s1n);
X7:AND3 port map(s0,x,s1,y);
end struc;

ii)

T flip flop
Z1
0
0
0
0
1
1
1
1

Z0
0
0
1
1
0
0
1
1

X
0
1
0
1
0
1
0
1

Z1
0
0
1
0
0
1
1
0

T0 = Z0^X; T1 = X(Z1^Z0) + Z1.Z0.X

Y= Z1.Z0.X

Code:
entity t_flipflop is
port(x,clk: in bit; y: out bit);
end t_flipflop;

Z0
0
1
0
1
0
1
0
1

T1
0
0
1
0
1
0
0
1

T0
0
1
1
0
0
1
1
0

Y
0
0
0
0
0
0
0
1

architecture struc of t_flipflop is

signal xn,s2,s3,s4,s5,s6,s7,s8,s0,s0n,s1,s1n:bit;
component t_flip
port(t,clk:in bit; q, qn:out bit);
end component;
component AND2
port(a,b :in bit;z:out bit);
end component;
component AND3
port(a,b,c:in bit; z:out bit);
end component;
component OR3
port(a,b:,cin bit; z:out bit);
end component;
component INVERTER
port(a:in bit; z:out bit);
end component;
begin
X1:INVERTER port map(x,xn);
X2:AND3 port map(s0, s1, x,s8);
X3:AND3 port map(s0,xn,s1n,s2);
X4:AND3 port map(xn,s1,s0n,s3);
X5:OR3 port map(s8,s2,s3,s6);
X6:AND2 port map(s1,xn,s4);
X7:AND2 port map(s1n,x,s5);
X8:OR2 port map(s4,s5,s7);
X9:t_flip port map(s6,clk,s0,s0n);
X10:t_flip port map(s7,clk,s1,s1n);
X11:AND3 port map(s0,x,s1,y);

end struc;

iii)

Jk Flip flop
Z1
0
0
0
0
1
1
1
1

Z0
0
0
1
1
0
0
1
1

X
0
1
0
1
0
1
0
1

Z1
0
0
1
0
0
1
1
0

Z0
0
1
0
1
0
1
0
1

J1 = Z0.X; K1 = X+Z0
J0 = X; K0 = X
Y = Z1.Z0.X

Code:
entity jk_flipflop is
port(x,clk: in bit; y: out bit);
end jk_flipflop;

architecture struc of jk_flipflop is

signal xn,s2,s3,s4,s5,s0,s0n,s1,s1n:bit;
component jk_flip

J1
0
0
1
0
X
X
X
X

K1
X
X
X
X
1
0
0
1

J0
0
1
X
X
0
1
X
X

K0
X
X
1
0
X
X
1
0

Y
0
0
0
0
0
0
0
1

port(j,k,clk:in bit; q, qn:out bit);

end component;
component AND2
port(a,b :in bit;z:out bit);
end component;
component AND3
port(a,b,c:in bit; z:out bit);
end component;
component OR2
port(a,b:in bit; z:out bit);
end component;
component INVERTER
port(a:in bit; z:out bit);
end component;
begin
X1:INVERTER port map(x,xn);
X2:AND2 port map(s1,xn,s2);
X3:AND2 port map(s1n,xn,s3);
X4:AND2 port map(s1,x,s4);
X5:OR2 port map(s3,s4,s5);
X6:jk_flip port map(s2,s4,clk,s0,s0n);
X7:jk_flip port map(x, xn,clk,s1,s1n);
X8:AND3 port map(s0,x,s1,y);
end struc;

Part ii) Behavioral style for the above sequence detector:

entity seq_det_1011 is
port (Clock,D:in bit; Z:buffer bit);
end seq_det_1011;
architecture behav of seq_det_1011 is
type state is (s1, s2, s3, s4);
signal n_s:state;

begin
process(Clock, D)
begin
if Clock='1' then
case n_s is
when s1=>
Z <= '0';
if (D='1') then
n_s <= s2;
end if;
when s2=>
Z <= '0';
if D='0' then
n_s <= s3;
end if;
when s3=>
Z <= '0';
if D='1' then
n_s <= s4;
else
n_s <= s1;
end if;
when s4=>
if D='1' then
Z <= '1';
n_s <= s1;
else
n_s <= s3;
end if;
end case;
end if;
end process;
end behav;

Question 4:
Z3
0
0
0
0

Z2
0
0
0
0

Z1
0
0
1
1

Z0
0
1
0
1

Z3
0
0
0
0

Z2
0
0
0
1

Z1
0
1
1
0

Z0
1
0
1
0

J3
0
0
0
0

K3
X
X
X
X

J2
0
0
0
1

K2
X
X
X
X

J1
0
1
X
X

K1
X
X
0
1

0
0
0
1
1

1
1
1
0
0

0
1
1
0
0

0
0
1
0
1

J3 =Z2Z1Z0; K3 = Z0
J2 = Z1Z0; K2 = Z1Z0
J1 = Z3Z0; K1=Z0

0
0
1
1
0

1
1
0
0
0

0
1
0
0
0

1
1
0
1
0

0
0
1
X
X

X
X
X
0
1

X
X
X
0
0

0
0
1
X
X

1
X
X
0
0

X
0
1
X
X