VERILOG HDL

Lab
(ECD-328)

LAB REPORT
SUBMITTED TO:

SUBMITTED BY:

Dr. PHILEMON DANIEL

Vikas

ASSISTANT PROFESSOR

13434

E&CED

E&CED

ELECTRONICS AND COMMUNICATION ENGINEERING

NATIONAL INSTITUTE OF TECHNOLOGY, HAMIRPUR

INDEX
S.No
.

1
2

3
4

Name Of The

P
a
g
Experiment e

TO IMPLEMET 2X1 MULTIPLEXER

TO IMPLEMENT 4X1
MULTIPLEXER
TO IMPLEMENT HALF ADDER
1)STRUCTURAL
2)DATAFLOW
3) BEHAVIOURAL
TO IMPLEMENT FULL ADDER
TO IMPLEMENT 4 BIT-SUBTRACTOR

TO IMPLEMENT 4 BIT COMPARATOR

6

TO IMPLEMENT 8X3 PRIORITY

ENCODER
7
8
9
10
11
12
13
14
15
16
17

TO IMPLEMET 8X3 ENCODER

TO IMPLEMENT 3X8 DECODER
TO IMPLEMENT AIRTHMETIC LOGIC
UNIT
TO IMPLEMENT D FLIPFLOP(ASYNCHRONOUS MODE)
TO IMPLEMENT SYNCHRONOUS D
FLIP-FLOP
TO IMPLEMENT SYNCHRONOUS
RESET AND PRESET D FLIP FLOP
TO DESIGN AN ASYNCHRONOUS
RESET AND PRESET D FLIP-FLOP
TO IMPLEMENT LEFT TO RIGHT
SHIFT REGISTER
TO IMPLEMENT UNIVERSAL SHIFT
REGISTER
TO IMPLEMENT 8 BIT COUNTER

Date

Remark
s

18
19
20
21
22

TO IMPLEMENT A COUNTER
COUNTING FROM 9 TO 67
TO IMPLEMENT NONOVERLAPPING
MELAY SEQUENCE DECETOR
TO IMPLEMENT OVERLAPPING
MELAY SEQUENCE DECETOR
TO IMPLEMENT 64X8 FIFO MEMORY
BLOCK
TO IMPLEMENT BENDING MACHINE

PRACTICLE 1
VERILOG CODE:

module mux2_1(a,b,s,y);
input a,b,s;
output y;
wire s0,x1,x2;
reg cout;
always @(a or b or s) begin
s0=~s;
x1=a&s;
x2=b&s0;
y=x1||x2;
end
endmodule
TESTBENCH CODE:

module mux2_1( );
wire a,b,s;
reg y;
muxgtlev uut (
.q(q),
.e(e),
.w(w),
.r (r)
);
initial
begin
#10 q=2'b01;
#20 e=2'b10;
#25 w=2'b11;
end
initial
begin
$monitor($time,"q=%b,e=%b,w=%b,r=%b",q,e,w,r);

end
endmodule

PRACTICLE 1
AIM: TO IMPLEMET 2X1 MULTIPLEXER.

BLOCK DIAGRAM:

SIMULATED WAVEFORM-

RTL SCHEMATIC-

TECHNOLOGY SCHEMATIC-

UTILIZATION REPORT-

PRACTICLE 2
VERILOG CODE:
module mux4x1 (d3, d2, d1, d0, sel, out);
input d3, d2, d1, d0;
input [1:0] sel;
output out;
reg out;
always @ (d3 or d2 or d1 or d0 or sel)
begin
case (sel)
0 : out = d0;
1 : out = d1;
2 : out = d2;
3 : out = d3;
default : out = 1b0;
default : out = 1b0;
end
endmodule
TESTBENCH CODE:
module mux4x1_test (d3,d2,d1,d0, sel, out);
input out;
output d3,d2,d1,d0;
output [1:0] sel;
reg d3,d2,d1,d0;
reg [1:0] sel;
initial
begin
d0 <= 1'b0;
d1 <= 1'b1;
d0 <= 1'b1;
d1 <= 1'b0;
d2 <= 1'b1;
d3 <= 1'b0;
sel <= 2'd0;
#100;
sel <= 2'd1;
#100;
sel <= 2'd2;
#100;
sel <= 2'd3;
#100;
d1 <= 1'b1;
d2 <= 1'b0;
d3 <= 1'b1;
sel <= 2'd0;
#100;
sel <= 2'd1;
#100;
sel <= 2'd2;
#100;
sel <= 2'd3;
end

endmodule

PRACTICLE 2

AIM: TO IMPLEMENT 4X1 MULTIPLEXER

BLOCK DIAGRAM:

SIMULATED WAVEFORM-

RTL SCHEMATIC-

TECHNOLOGY SCHEMATIC:

UTILIZATION REPORT:

PRACTICLE 3(A)
VERILOG CODE:
module ha_s(
input a,
input b,
output s,
output c
);
xor xor1(s,a,b);
and and1(c,a,b);
endmodule
TESTBENCHCODE:
module ha_d_tb();
reg a,b;
ha_d ha(a,b,s,c);
initial
begin
a=0;b=0;
#100;
a=0;b=1;
#100;
a=0;b=1;
#100;
a=1;b=0;
#100;
a=1; b=1;
end
endmodule

DESIGN 3(A)
AIM: TO IMPLEMENT HALF ADDER (STRUCTURAL).

BLOCK DIAGRAM-

SIMULATED WAVEFORM-

RTL SCHEMATIC-

TECHNOLOGY SCHEMATIC-

UTILIZATION REPORT-

PRACTICLE 3(B)
VERILOG CODE:
module ha_d(
input a,
input b,
output s,
output c

);
assign s=(a&~b)|(~a&b);
assign c=a&b;

endmodule
TEST BENCH CODE:
module ha_d_tb();
reg a,b;
ha_d ha(a,b,s,c);
initial
begin
a=0;b=0;
#100;
a=0;b=1;
#100;
a=0;b=1;
#100;
a=1;b=0;
#100; a=1;
b=1; end
endmodule

RTL SCHEMATIC:

TECHNOLOGY SCHEMATIC:

UTILIZATION REPORT:

PRACTICLE 3(C)
VERILOG CODE:

module ha_b(
input a,
input b,
output reg s,
output reg c);
always@(a,b)
begin
s=(a&~b)|(~a&b);
c=a&b;
end
endmodule
TEST BENCH CODE:

module h_adder_tb(
);
reg in1,in2;
h_adder inst(in1,in2,s,c);
initial
begin
$monitor(in1,in2,s,c,$time);
in1=0;
in2=0;
#20
in1=0;
in2=1;
#20
in1=1;
in2=0;
#20
in1=1;
in2=1;
end
endmodule

PRACTICLR 3(C)

AIM- TO IMPLEMENT HALF ADDER USING(BEHAVIOURAL)

BLOCK DIAGRAM-

SIMULATED WAVEFORM-

RTL SCHEMATIC:

TECHNOLOGY SCHMEATIC:

UTILIZATION REPORT:

PRACTICLE 4
Module:

module fulladder(
input a,
input b,
input Cin,
output sum,
output carry
);
wire x,y,z;
halfadder hf1(a,b,x,y);
halfadder hf2(x,Cin,sum,z);
or or1(carry,z,y);
endmodule
TESTBENCH CODE:
module fulladder_tb( );
reg a,b,cin;
fulladder inst(a,b,cin,sum,carry);
initial
begin
a=0; b=0; cin=0;
#20
cin=1;
#20
b=1;
cin=0;
#20
b=1;
cin=1;
#20
a=1;
b=0;
cin=0;

#20
cin=1;
#20
b=1;
cin=0;
#20
cin=1;
#20
$stop;
end
endmodule
TRUTH TABLE:
a
0
0
0
0
1
1
1
1

b
0
0
1
1
0
0
1
1

c
0
1
0
1
0
1
0
1

S
0
1
1
0
1
0
0
1

Cout
0
0
0
1
0
1
1
1

PRACTICLE 4
AIM-

TO IMPLEMENT FULL ADDER

BLOCK DIAGRAM-

Waveform:

RTL Schematic:

Technology Schematic

UTILIZATION REPORT:

PRACTICLE 5
VERILOG CODE:
module addersubtractor4_bit(
input a1,
input a2,
input a3,
input a4,
input b1,
input b2,
input b3,
input b4,
input cin,
output c1,
output c2,
output c3,
output c4,
output s1,
output s2,
output s3,
output s4
);
wire x1,x2,x3,x4;
xor xor1(x1,b1,cin);
xor xor2(x2,b2,cin);
xor xor3(x3,b3,cin);
xor xor4(x4,b4,cin);
fulladder fa1(a1,x1,cin,s1,c1);
fulladder fa2(a2,x2,c1,s2,c2);
fulladder fa3(a3,x3,c2,s3,c3);
fulladder fa4(a4,x4,c3,s4,c4);
endmodule

TEST BENCH CODE: module addersubtractor4_bit_tb(

);

reg a1,a2,a3,a4,b1,b2,b3,b4,cin;
addersubtractor4_bit
inst(a1,a2,a3,a4,b1,b2,b3,b4,cin,s1,s2,s3,s4,c4);
initial
begin
a1=0;b1=0;a2=0;b2=0;a3=0;b3=0;a4=0;b4=0;cin=1;
#20
a1=1;b1=1;a2=1;b2=1;a3=1;b3=1;a4=1;b4=1;cin=1;
#20
a1=0;b1=0;a2=0;b2=0;a3=0;b3=0;a4=0;b4=0;cin=0;
#20
a1=1;b1=1;a2=1;b2=1;a3=1;b3=1;a4=1;b4=1;cin=0;
#20
$stop;
end
endmodule

PRACTICLE 5:
AIM: To implement 4 bit adder-subtractor using Verilog
BLOCK DIAGRAM:

OUTPUT WAVEFORM:

RTL SCHEMATIC:

TECHNOLOGY SCHEMATIC:

UTILIZATION REPORT:

PRACTICLE 6:

VERILOG CODE:
module comprator_1(
input [3:0] a,
input [3:0] b,
output reg gt,
output reg sl,
output reg eq
);
always @(*)
begin
if (a==b)
begin
eq=1;
sl=0;
gt=0;
end
else if (a>b)
begin
eq=1;
sl=0;
gt=0;
end
else
begin
eq=0;
sl=1;
gt=0;
end
end
endmodule
TESTBENCH CODE:
module comprator_1_tb(
);

reg [3:0]a,b;
comprator_1 inst(a[3:0],b[3:0],gt,sl,eq);
initial
begin
$monitor(a,b,gt,sl,eq,$time);
a=4'b0000; b=4'b0001;
#30;
a=4'b0001; b=4'b0011;
#30;
a=4'b0101; b=4'b0111;
#30;
a=4'b1111; b=4'b0101;
end
endmodule

DESIGN 6

AIM: To Implemnt 4 bit comparator

SIMULATED WAVEFORM:

RTL SCHEMATIC:

TECHNOLOGY SCHEMATIC:

PRACTICLE 7:
VERILOG CODE:
module bit4_priorityencoder(
input d3,
input d2,
input d1,
input d0,
output x1,
output x0
);
wire e,f,g,h;
not not1(e,d3);
not not2(f,d2);
and and1(g,e,d2);
and and2(h,e,f,d1);
or or1(x1,d3,g);
or or2(x0,d3,h);
endmodule
TESTBENCH CODE:
module bit4_priorityencoder_tb(
);
reg d3,d2,d1,d0;
bit4_priorityencoder inst1(d3,d2,d1,d0,x1,x0);
initial
begin
$monitor(d3,d2,d1,d0,x1,x0,$time);
d3=0;
d2=0;
d1=0;
d0=0;
# 20
d3=1;

d2=0;
d1=0;

d0=0;
#20
d3=1;
d2=1;
d1=0;
d0=0;
#20
d3=0;
d2=0;
d1=1;
d0=1;
#20
d3=1;
d2=1;
d1=1;
d0=1;
end
endmodule

PRACTICLE 7
AIM- TO IMPLEMENT 8X3 PRIORITY ENCODER
BLOCK DIAGRAM:

SIMULATED WAVEFORM:

RTL SCHEMATIC

TECHNOLOGY SCHMEATIC:

UTILIZATION REPORT:

PRACTICLE 8
VERILOG CODE:
module encoder8_3(
input [0:7] a,
output [0:2] y
);
assign y[2]=(a[4]|a[5]|a[6]|a[7]);
assign y[1]=(a[2]|a[3]|a[6]|a[7]);
assign y[0]=(a[1]|a[3]|a[5]|a[7]);
endmodule
TESTBENCH CODE:
module encoder_8_3_tb(
);
reg [7:0]a;

wire [2:0]y;
encoder_8_3 inst_1(a,y);
initial
begin
a=8'b10000000;
#20
a=8'b00000001;
#20
a=8'b00000010;
#20
a=8'b00000100;
#20
a=8'b00001000;
#20
a=8'b00010000;
#20
a=8'b00100000;
#20
a=8'b01000000;
#20
$stop;
end
endmodule
PRACTICLE 8
AIM- TO IMPLEMET 8X3 ENCODER
BLOCK DIAGRAM:

Waveform:

RTL Schematic:

Technology Schematic:

Utilization Report:

PRACTICLE 9
VERILOG CODEmodule decoder3_8(
input a,
input b,
input c,
output [0:7] y

);
always @(a,b,c)
begin
if((a)&&(b)&&(c))
y=8'b10000000;
else if((a)&&(b)&&(~c))
y=8'b01000000;
else if((a)&(~b)&(c))
y=8'b00100000;
else if((a)&(~b)&(~c))
y=8'b00010000
else if((~a)&(b)&(c))
y=8'b00001000;
else if((~a)&(b)&(~c))
y=8'b00000100;
else if((~a)&(~b)&(c))
y=8'b00000010;
else
y=8'b00000001;
end
endmodule
TESTBENCH CODE:
module decoder3_8_tb(
);
wire [0:7]y;
reg a,b,c;
decoder3_8 inst(a,b,c,y[0:7]);
initial
begin
a=0;
b=0;
c=0;
#20
a=1;
b=0;
c=0;
#20

a=1;
b=1;
c=0;
#20
a=0;
b=1;
c=1;
#20
a=0;
b=1;
c=0;
#20
a=1;
b=1;
c=1;
$stop;
end
endmodule
PRACTICLE 9
AIM- TO IMPLEMENT 3X8 DECODER
BLOCK DIAGRAM-

SIMULATED WAVEFORM:

RTL SCHEMATIC:

TECHNOLOGY SCHMEATIC:

Utilization Report:

DESIGN 10

VERILOG CODE:
module ALU(
input [7:0] A,
input [7:0] B,
input [2:0]OP,
output [7:0] X,
output [7:0] Y,
output Z,
output C,
output P
);
reg [7:0]X,Y;
reg Z,C,P;
always @(*)
begin
case(OP)
3'b000:begin
{C,X}=A+B;
Y=0;
end
3'b001:begin
{C,X}=A-B;
Y=0;
end
3'b010:begin
{Y,X}=A*B;
C=0;
end
3'b011:begin
if((B%2)==0)
begin
X=A/B;
C=0;
end
else
C=0;

end
3'b100:begin
if(A>B)
begin
X=A;
C=0;
end
else
begin
X=B;
C=0;
end
end
3'b101:begin
X=A<<2;
C=0;
end
3'b110:begin
X=A>>2;
C=0;
end
3'b111:
begin
X={A[0],A[1],A[2],A[3],A[4],A[5],A[6],A[7]};
C=0;
end
endcase
P=^X;
Z=~|X;
end
endmodule
TESTBENCH CODEmodule ALU_tb(
);
reg [7:0]A;
reg [7:0]B;

reg [2:0]OP;
wire [7:0]X;
wire [7:0]Y;
ALU inst1(A,B,OP,X,Y,Z,C,P);
initial
begin
$monitor("A=%b, B=%b, OP=%b, X=%b, Y=%b, Z=%b, C=%b,
P=%b, time=%d",A,B,OP,X,Y,Z,C,P,$time);
A=8'b01001001;
B=8'b00100110;
OP=3'b111;
#20;
OP=3'b101;
#20;
OP=3'b011;
#20;
OP=3'b100;
end
endmodule

DESIGN 10

AIM- TO IMPLEMENT AIRTHMETIC LOGIC UNIT

BLOCK DIAGRAM-

SIMULATED WAVEFORM-

RTL SCHEMETIC-

TECHNOLOGY SCHEMATIC-

UTILIZATION REPORT-

PRACTICLE 11

VERILOG CODEmodule DFF_async(

input D,
input R,
input clk,
output Q
);
reg Q;
always @(R,clk)
begin
if(R)
Q=0;
else
Q=D;
end
endmodule
TESTNENCH CODE:

module DFF_async_tb(
);
reg D,R,clk;
DFF_async inst(D,R,clk,Q);
initial
begin
clk=0;
forever begin
#10 clk=~clk;
end
end
initial
begin
D=0;
R=0;
#50
R=1;
#5
D=1;
#5;
R=0;
D=0;
#10
D=1;
#15
R=1;
#10;
R=0;
D=1;
#50
R=1;
#50
D=1;
R=0;
$stop;
end
endmodule

PRACTICLE 11

AIM- TO IMPLEMENT D FLIP-FLOP(ASYNCHRONOUS MODE)

BLOCK DIAGARM-

SIMULATED WAVEFORM-

RTL Schematic:

Technology Schematic:

Utilization Report:

PACTICLE12
VERILOG CODEmodule DFF_async_P(
input D,
input R,
input clk,
output Q
);
reg Q;
always @(posedge R,posedge clk)
begin
if(R)
Q=0;
else
Q=D;
end
endmodule
TESTBENCH CODE:
module DFF_async_P_tb(

);
reg D,R,clk;
DFF_async_P inst(D,R,clk,Q);
initial
begin
clk=0;
forever begin
#10 clk=~clk;
end
end
initial
begin
D=0;
R=0;
#50
D=1;
#5;
D=0;
#10
D=1;
#15
R=1;
#10;
R=0;
D=1;
#50
R=1;
#50
R=0;
D=0;
#25
D=1;
R=0;
#15
$stop;
end
endmodule

PACTICLE 12

AIM- TO IMPLEMENT SYNCHRONOUS D FLIP-FLOP

BLOCK DIAGRAM-

SIMULATED WAVEFORM-

RTL Schematic:

Synthesised design:

Utilization Report:

PRACTICLE 13
VERILOG CODEmodule DFF_sync_P(
input D,
input R,
input clk,
output Q
);
reg Q;
always @(posedge clk)
begin
if(R)
Q=0;
else
Q=D;
end
endmodule
TESTBENCH CODEmodule DFF_sync_P_tb(
);
reg D,R,clk;

DFF_sync_P inst(D,R,clk,Q);
initial
begin
clk=0;
forever begin
#10 clk=~clk;
end
end
initial
begin
D=0;
R=0;
#20
R=1;
D=1;
#15;
R=0;
D=1;
#5
D=0;
#15
D=1;
R=1;
#20;
R=0;
D=1;
#50
R=1;
#10
D=1;
R=0;
#30
$stop;
end
endmodule

PRACTICLE 13
AIM- TO IMPLEMENT SYNCHRONOUS RESET AND PRESET D
FLIP FLOP.

BLOCK DIAGRAM

SIMULATED WAVEFORM-

RTL SCHEMATIC-

TECHNOLOGY SCHEMATIC-

UTILIZATION REPORT-

PRACTICLE 14
VERILOG CODEmodule DFF_async_P(
input r,
input p,
input d,
input clk,
output Q
);
reg Q;
always @(posedge R,posedge clk)
begin
if(r)
Q=0;
else
Q=d
;

end
endmodule
TESTBENCH CODEmodule DFF_async_P_tb(
);
reg D,R,clk;
DFF_async_P inst(D,R,clk,Q);
initial
begin
clk=0;
forever begin
#10 clk=~clk;
end
end
initial
begin
D=0;
R=0;
#50
D=1;
#5;
D=0;
#10
D=1;
#15
R=1;
#10;
R=0;
D=1;
#50
R=1;
#50
R=0;
D=0;
#25
D=1;
R=0;
#15
$stop;
end

endmodule

PRACTICLE 14

AIM- TO DESIGN AN ASYNCHRONOUS RESET AND PRESET

D FLIP-FLOP

BLOCK DIAGRAM-

SIMULATED WAVEFORM-

RTL SCHEMATIC-

TECHNOLOGY SCHMATIC-

UTILIZATION REPORT-

DESIGN 15
VERILOG CODEmodule L_R_shift_register(
input in,
input clk,
input R,
output OUT
);
reg B,C,D,E;
reg OUT;
always @(posedge clk)
begin
if(R)
begin
B<=0;C<=0;D<=0;E<=0;OUT<=0;
end
else
begin
OUT=E;
E=D;
D=C;
C=B;
B=in;
end
end
endmodule

TESTBENCH CODEmodule LtoR_shift_register_tb(

);
reg in,R,clk;
L_R_shift_register inst(in,clk,R,OUT);
initial
begin
clk=0;
forever
begin
#10
clk=~clk;
end
end
initial
begin

in=1;
R=0;
#100
in=0;
#100
in=1;
#100
in=1;
#100
R=1;
#10
R=0;
in=0;
#100
$stop;
end
endmodule

PRACTICLE 15
AIM- TO IMPLEMENT LEFT TO RIGHT SHIFT REGISTER
BLOCK DIAGRAM-

SIMULATED WAVEFORM-

RTL SCHEMATIC-

TECHNOLOGY SCHEMATIC-

UTILIZATION REPORT-

PRACTICLE 16
VERILOG CODEmodule USR_1(
input SI,
input Clk,
input [1:0] Sel,
input [4:0] PI,
output reg SO,
output reg [4:0] PO
);
reg B,C,D,E,SL,NC;
always@(posedge Clk)
begin
case (Sel)
2'b00: begin
SL<=C;
B<=D;
C<=E;
D<=SO;
end
2'b01: begin
B<=SI;
C<=B;
D<=C;
E<=D;
SO<=E;
end
2'b10: begin
PO<=PI;
end
default: NC<=B;

endcase
end
endmodule

TESTBENCH CODEmodule USR_1_tb(

);
reg SI;
reg [4:0]PI;
reg Clk;
reg [1:0]Sel;
reg SL;
wire SO;
wire [4:0]PO;
wire B,C,D,E,NC;
USR_1 inst(SI,Clk,Sel,PI,SO,PO);
initial
begin
Clk=0;
forever
begin
#10
Clk=~Clk;
end
end
initial
begin
Sel=2'b01;

SI=1;
#20;
SI=0;
#20;
SI=1;
#20;
SI=0;
#20;
SI=0;
#20;
SI=1;
#20;
Sel=2'b00;
SL=0;
#20;
SL=1;
#20;
SL=1;
#20;
SL=0;
#20;
SL=1;
#20;
SL=0;
#20;
Sel=2'b10;
PI=5'b01101;
#20;
PI=5'b10111;
#20;
end
endmodule

PRACTICLE 16
AIM- TO IMPLEMENT UNIVERSAL SHIFT REGISTER
BLOCK DIAGRAM-

SIMULATED WAVEFORM-

RTL SCHEMATIC-

TECHNOLOGY SCHMEATIC:

Utilization Report:

PRACTICLE 17
VERILOG CODEmodule counter_8_bit(
input clk,
input reset,
output reg [7:0] out,
input sel
);
always @ ( posedge clk)
begin
if (reset == 1)
begin
out <= 8'b00000000;
end
else if (sel == 1)
begin
out <= out+1;
end
else if (sel == 0)
begin
out <= out-1;
end
end
endmodule
TESTBENCH CODEmodule counter_8_bit_tb(
);
reg clk;
reg reset;
reg sel;
wire [7:0] out;
counter_8_bit inst (clk,reset,out,sel);
initial
begin
clk = 1;
forever
begin
#10

clk =~clk;
end
end
initial
begin
sel = 0;
reset =1;
#20
reset = 0;
sel = 1;
#180
reset = 0;
sel = 0;
#10
$stop;
end
endmodule

PRACTICLE 17
AIM-TO IMPLEMENT 8 BIT COUNTER
BLOCK DIAGRAM-

SIMULATED WAVEFORM-

RTL SCHEMATIC-

TECHNOLOGY SCHEMATIC-

PRACTICLE 18
VERILOG CODEmodule counternine1(
input clock,
input reset,
input sel,
output reg [7:0] count
);
always@(posedge clock)
begin
if (reset==1) count<=8'b00001001;
else if(count == 8'b01000011)
count<=8'b00001001;
else if(count < 8'b00001001)
count<=8'b00001001;
else
begin
case(sel)
1'b0: count<=count+1;
1'b1:count<=count-1;
default: count<=count+1;
endcase
end
end
endmodule
TESTBENCH CODEmodule counterninetb();
reg clock; reg sel; reg reset;
wire [7:0] count;
counternine1 c(clock,reset,sel,count );
initial
begin clock=0;
forever #10 clock=~clock;
end
initial
begin
$monitor("clock=%b,sel=%b,reset=%b,count=%b,time=
%d",clock,sel,reset,count,$time);
sel=0; reset=1;
#100;
reset=0; sel=0;

#1500;
sel=1;
#1000;
$stop;

end
endmodule
PRACTICLE 18
AIM-TO IMPLEMENT A COUNTER COUNTING FROM 9 TO 67
SIMULATED WVAEFORM-

RTL SCHEMATIC:

TECHNOLOGY SCHEMATIC:

UTILIZATION REPORT:

PRACTICLE 19
VERILOG CODEmodule melaymachine(
input clk,
input i,
input rst,
output y
);
parameter s0=3'b000,s1=3'b001,s2=3'b010,s3=3'b011,s4=3'b100;
reg[2:0]pr_state,nx_state,y;

always@(posedge clk)
begin
if(rst)
pr_state<=s0;
else
pr_state <=nx_state;
end
always @(i,pr_state)
begin
case (pr_state)
s0: if(i) nx_state <=s1;
else nx_state <=s0;
s1:if(i) nx_state <=s2;
else nx_state <=s0;
s2:if(i) nx_state <=s2;
else nx_state <=s3;
s3: if(i) nx_state <=s4;
else nx_state <=s0;
s4: if(i) nx_state <=s0;
else nx_state <=s0;
default nx_state <=s0;
endcase
end
always@(i,pr_state)
begin
case(pr_state)
s0: if(i)
y=0;
s1: if(i)
y=0;
s2: if(i)
y=0;
s3: if(i)
y =0;
s4: if(i)
y =1;
else y=0;
endcase
end

endmodule
TESTBENCH CODEmodule melay_tb(
);
reg i,clk,rst;
melaymachine inst_1(clk ,i ,rst,y);
initial
begin
clk = 0;
forever
#10
clk =~clk;
end
initial
begin
rst = 1;
#20
rst = 0;
i =1;
#20
i = 1;
#20
i = 1;
#20
i = 0;
#20
i = 1;
#20
i = 1;
$stop;
end
endmodule

PRACTICLE 19
AIM- TO IMPLEMENT NON OVERLAPPING SEQUENCE DECETOR
BLOCK DIAGRAM-

SIMULATED WAVEFORM-

RTL SCHEMATIC-

TECHNOLOGY SCHEMATIC-

UTILIZATION REPORT-

PRACTICLE 20
VERILOG CODEmodule overlapmealy(
input clk,
input i,
input rst,
output y
);
parameter s0 =3'b000,s1=3'b001,s2=3'b010,s3=3'b011,s4=3'b101;
always@(posedge clk)
begin
if(rst)
pr_state <=s0;
else pr_state <=nx_state;
end
always@(i,pr_state)
begin
case(pr_state)
s0:
if(i)
nx_state <=s1;
else
nx_state <=s0;
s1: if(i) nx_state <=s2;
else nx_state <=s0;
s2: if(i) nx_state <=s2;
else nx_state <=s3;
s3: if(i) nx_state <=s4;
else nx_state <=s0;
s4: if(i) nx_state <=s2;
else nx_state <=s0;
default:
nx_state <=s0;
endcase
end
always@(i,pr_state)
begin
case(pr_state)
s0: if(i)
y=0;
s1: if(i)
y=0;

s2: if(i)
y=0;
s3: if (i)
y=0;
s4: if(i)
y=1;
else
y=0;
endcase
end
endmodule
TESTBENCH CODEModule overlapmealy_tb(
);
reg i,clk,rst;
overlapmealy inst_1(clk ,i ,rst,y);
initial
begin
clk = 1;
forever
begin
#10
clk =~clk;
end
end
initial
begin
rst =1;
#10
rst = 0;
i = 0;
#20
i =1;
#20
i = 1;
#20
i = 0;
#20
i =1;
#20
i = 1;
#20
$stop;

end
endmodule

PRACTICLE 20
AIM- TO IMPLEMENT OVERLAPPING MELAY SEQUENCE DECETOR

BLOCK DIAGRAM-

SIMULATED WAVEFORM

RTL SCHEMATIC-

TECHNOLOGY SCHEMATIC

UTILIZATION REPORT-

PRACTICLE 21
VERILOG CODE-

module FIFO(
input clk1,
input clk2,
input sel,
input [7:0]buffin,
output reg [7:0]buffout,
output reg F
);
reg [0:6]H,T;
reg [0:7]mem[0:63];
reg [0:6]count;
integer k=0,start=0;
parameter n=63;
always @(posedge clk1)
begin
if(start==0)
begin
H=0;
T=0;
F=0;
start=1;
end
if(k<=n&&F!=1&&sel==0)
begin
mem[k]<=buffin;
T=k;
k=k+1;
end
if(k==n&&F!=1&&sel==0)
begin
mem[k]<=buffin;
T=k;
k=0;

end
if(T==n)
F=1;
end
integer i=0;
always @(posedge clk2)
begin
if(H==T&&sel==1)
buffout<=8'Bxxxxxxxx;
else if(i<n&&sel==1)
begin
buffout<=mem[i];
i=i+1;
H=i;
end
if(i==n&&sel==1)begin
buffout<=mem[i];
i=0;
H=i;
end
end
endmodule

TESTBENCH Code:
module FIFO_tb(
);
reg clk1,clk2,sel;
reg [7:0]buffin;
wire [7:0]buffout;
wire F;
FIFO inst(clk1,clk2,sel,buffin,buffout,F);
initial
begin
clk1=0;
forever
#5
clk1=~clk1;
end
initial
begin
clk2=0;
forever
#10
clk2=~clk2;
end
initial
begin
$monitor(mem=%b,buffin=%b,F=%b,H=%d,T=
%d,inst.mem,buffin,F,inst.H,inst.T);
sel=0;
buffin=8b00011101;
#20

buffin=8b10011101;
#20
buffin=8b01011101;
#20
buffin=8b00011111;
#20
buffin=8b00100101;
#20
#50
sel=1;
#200
$stop;
end
endmodule

PRACTICLE 21
AIM- TO IMPLEMENT 64X8 FIFO MEMORY BLOCK

BLOCK DIAGRAM-

SIMULATE WAVEFORM-

RTL Schematic :

Utlization Report:

PRACTICLE 22
VERILOG CODEmodule VendingMC(input clk,R,
input [1:0]m,
input sel,
output reg [1:0]y,ba
);
parameter one=2'b00,two=2'b01,five=2'b10;
parameter a=4'b0001,b=4'b0010,c=4'b0011;
parameter d=4'b0100,e=4'b0101,f=4'b0110;
parameter g=4'b0111,h=4'b1000,i=4'b1001,j=4'b0000;
reg [3:0]pr_state,nx_state;
always @(posedge clk)
begin
if(R)
begin
pr_state<=j;
end
else
pr_state<=nx_state;
end
always @(sel,m,pr_state)
begin
if(sel==0)
begin
case(pr_state)
j:if(m==one) nx_state<=a;
else if(m==two) nx_state<=b;
else if(m==five)nx_state<=j;
else nx_state<=j;
a: if(m==one) nx_state<=b;
else if(m==two) nx_state<=c;
else nx_state<=a;
b: if(m==one) nx_state<=c;
else if(m==two) nx_state<=d;
else nx_state<=b;
c: if(m==one) nx_state<=d;
else if(m==two) nx_state<=j;
else nx_state<=c;
d: if(m==one) nx_state<=j;
else if(m==two) nx_state<=j;
else nx_state<=d;
default: nx_state<=j;
endcase
end
else
begin
case(pr_state)
j:if(m==one) nx_state<=a;
else if(m==two) nx_state<=b;
else if(m==five)nx_state<=e;
else nx_state<=j;

a: if(m==one) nx_state<=b;
else if(m==two) nx_state<=c;
else if(m==five)nx_state<=f;
else nx_state<=a;
b: if(m==one) nx_state<=c;
else if(m==two) nx_state<=d;
else if(m==five)nx_state<=g;
else nx_state<=b;
c: if(m==one) nx_state<=d;
else if(m==two) nx_state<=e;
else if(m==five)nx_state<=h;
else nx_state<=c;
d: if(m==one) nx_state<=e;
else if(m==two) nx_state<=f;
else if(m==five)nx_state<=i;
else nx_state<=d;
e:if(m==one) nx_state<=f;
else if(m==two) nx_state<=g;
else if(m==five)nx_state<=j;
else nx_state<=e;
f: if(m==one) nx_state<=g;
else if(m==two) nx_state<=h;
else if(m==five)nx_state<=j;
else nx_state<=f;
g: if(m==one) nx_state<=h;
else if(m==two) nx_state<=i;
else if(m==five)nx_state<=j;
else nx_state<=g;
h: if(m==one) nx_state<=i;
else if(m==two) nx_state<=j;
else if(m==five)nx_state<=j;
else nx_state<=h;
i: if(m==one) nx_state<=j;
else if(m==two) nx_state<=j;
else if(m==five)nx_state<=j;
else nx_state<=i;
default: nx_state<=j;
endcase
end
end
always @(*)
begin
if(sel==0)
begin
case(pr_state)
j: if(m==five) begin y<=2'b01;
ba<=2'b00;end
c: if(m==two)begin y<=2'b01;
ba<=2'b00; end
d: if(m==one)begin y<=2'b01;
ba<=2'b00; end
else if(m==two)begin y<=2'b01;
ba<=2'b01; end
endcase
end

else
begin
case(pr_state)
e: if(m==five) begin
y=2'b10;
ba=2'b00;
end
h: if(m==two) begin
y=2'b10;
ba=2'b00;
end
i: if(m==one) begin
y=2'b10;
ba=2'b00;
end
else if(m==two) begin
y=2'b10;
ba=2'b01;
end
endcase
end
end
endmodule

Simulation Code:
module VendingMC_tb(
);
reg clk,R;
reg [1:0]m;
reg sel;
wire [1:0]y,ba;
VendingMC inst(clk,R,m,sel,y,ba);
initial
begin
clk=0;
forever
#5
clk=~clk;
end
initial
begin
$monitor("m=%b,clk=%b,y=%b,sel=%b,pr_state=
%b",m,clk,y,sel,inst.pr_state);
R=1;
#10
R=0;
sel=0;
m=2'b00;

#100
m=2'b01;
#100
m=2'b10;
#40
sel=1;
m=2'b00;
#100
$stop;
end
endmodule

Utilization Report:

Simulation Waveform:

RTL Schematic:

Technology Schematic: