Recapitulate

BJT and MOSFET Comparison

VLSI Background & Moores Law
VLSI Industry Components

VLSI Design Flow

VLSI Design Styles
Relation between Chip Performance and VLSI

Design Style
Abstraction and Y Chart
VLSI Design Strategy

Syllabus
1. Introduction to CMOS digital circuit Design
2. Circuit Characterization & performance Estimation
3. Combinational Circuit Design
4. Sequential Circuit Design
5. Array Subsystem Design

6. CMOS Layout

Syllabus
1. Introduction to CMOS digital circuit Design
2. Circuit Characterization & performance Estimation
3. Combinational Circuit Design
4. Sequential Circuit Design
5. Array Subsystem Design

6. CMOS Layout

Text Books:
Sung-Mo-Kang, Usuf Leblebici ,CMOS digital integrated
circuits: Analysis and Design, Tata McGrawhill,2003
Neil H E Weste, David Harris, Ayan Bannerjee, CMOS
VLSI design, Pearson

Reference Books :
Jan M Rabaey, Digital integrated circuits
Yuan Taur, Tak H Ning, Fundamentals of Modern VLSI
devices
Stephen Brown, Fundamentals of digital logic with VHDL
design
Razavi, Design of Analog CMOS Integrated circuits
5

MOS Capacitor

MOS Capacitor

MOS Capacitor C-V Curve

Space charge density variation wrt. surface

potential in MOS Capacitor

p ni e( Ei EF )/ KT
n ni e( EF Ei )/ KT

MOS Capacitor C-V Curve

When negative voltage is applied at gate of MOS capacitor then an

equal positive charge is deposited near the surface of

semiconductor. Accumulation occurs when there is a buildup of
majority charge carrier i.e. hole near the interface due to the
negative voltage applied to them gate. There is no change in the
Fermi level of semiconductor as zero current flows through the
MOS structure.

Now consider when a small positive voltage is applied at gate

terminal of p MOS capacitor the surface region of bulk near to

interface gets depleted of holes leaving behind uncompensated
ionized acceptors (negatively charged). This region of operation of
C-V characteristics is depletion region.

With further increase of positive gate bias band bending is

increased further in downward direction. At sufficiently large

positive voltage inversion occurs i.e. top portion of p type
substrate which is near to interface turn into n type.

 Electron affinity potential difference between conduction band level and

vacuum level
Work Function Fermi level to vacuum level

 Now the three components of ideal MOS Capacitor are

brought into physical contact.

In equilibrium, Fermi Level all three must line up.
Because of work function difference between metal and
semiconductor , a voltage drop occurs across MOS system
Part of this voltage occurs insulating oxide layer and rest
across silicon surface next to silicon-oxide interface , forcing
the band bending of MOS system near interface.
Bulk potential and surface potential

MOS Capacitor at Inversion

Recapitulate
MOS Capacitor C-V Characteristics
Accumulation , Depletion , Inversion Region
High frequency and Low frequency region

Energy Band Diagram of semiconductor

Work Function and Electron affinity
Flatband Voltage

Band Bending in MOS capacitor

Accumulation , Depletion , Inversion Region
Fermi Potential, Surface potential
Charge Density in depletion and inversion region

MOSFET

MOSFET Drain Current

ID

nCox W
2
2 VGS VT VDS VDS

kn'
ID
2

2
V

V
V

GS
T
DS
DS

k
I D n 2 VGS VT VDS VDS 2
2

where,
kn' nCox

where,
W
kn kn'
L

MOSFET Threshold Voltage

Four physical components of the Threshold Voltage
Work Function Difference between gate and channel
Gate voltage to change surface potential
Gate voltage to offset the depletion region charge
Gate voltage to offset fixed charges in gate oxide and
silicon-oxide interface.

MOSFET Threshold Voltage1

Four physical components of the Threshold Voltage
Work Function Difference between gate and channel

GC F (substrate) M

GC F (substrate) F ( gate)

For metal gate

For polysilicon
gate

MOSFET Threshold Voltage2

Four physical components of the Threshold Voltage
Gate voltage to change surface potential

2F

MOSFET Threshold Voltage3

Four physical components of the Threshold Voltage
Gate voltage to offset the depletion region charge
QB 0 2q.N A . Si . 2F
QB 2q.N A . Si . 2F VSB

QB
Cox

QB 0 CoxV

MOSFET Threshold Voltage4

Four physical components of the Threshold Voltage
Gate voltage to offset fixed charges in gate oxide and
silicon-oxide interface
Qox

Qox
Cox

Let Qox is density of fixed charges

in gate oxide and silicon-oxide
interface.

MOSFET Threshold Voltage

QB 0 Qox
VT 0 GC 2F

Cox Cox
QB Qox
VT GC 2F

Cox Cox

No substrate bias effect ( VSB=0)

Considering substrate bias effect

QB 0 Qox QB QB 0
VT GC 2F

Cox Cox
Cox

QB QB 0
VT VT 0
Cox

where,
VT 0 GC 2F

QB 0 Qox

Cox Cox

QB QB 0
VT VT 0
Cox

QB 0 2q.N A . Si . 2F
QB 2q.N A . Si . 2F VSB

QB QB 0 2q.N A . Si

VT VT 0

VT VT 0

2q.N A . Si

2F VSB 2F
Cox

2F VSB 2F

2F VSB 2F

2q.N A . Si

Cox
Substrate Bias
coefficient

Numerical
Calculate the threshold voltage VT0 at VBS = 0,

for a polysilicon gate n-channel MOS transistor

with the following parameters:
o substrate doping density NA = 1016 cm-3,
o polysilicon doping density ND = 2 x 1020 cm-3,
o gate oxide thickness tox = 500 Angstroms,
o oxide-interface fixed charge density Nox = 4 x 1010 cm-2,

Channel Length Modulation

QI : Inversion
Layer charge

Channel Pinched
off at drain when
Vds = Vdssat
Consequently the
effective channel
length is reduced

So, VCS at L is still VDS,sat.

The electron travelling from source towards drain traverse the inverted channel
(length L) and then are injected into the depletion region of L

Channel Length Modulation

Channel Length Modulation

Substrate Bias Effect

When source and substrate (bod) of MOSFET

are at different potential then the threshold

voltage of MOSFET gets modified.

Channel Length Modulation &

Substrate Bias Effect