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TPS81256
SLVSAZ9C JUNE 2012 REVISED FEBRUARY 2016
3 Description
2 Applications
PACKAGE
TPS81256
SIP (9)
2.925 mm 2.575 mm
Typical Application
TPS81256SIP
L
VO = 5.0 V
100
DC/DC Converter
VOUT = 5.0 V
90
VOUT
80
VIN
2.5 V .. 4.85 V
70
VIN
EN
GND
4.7F
16V X5R (0603)
60
Efficiency - %
CO
CI
50
40
.
30
20
ENABLE
t Cu
tpu
Ou
IO -
t-m
rren
397.9
199.4
50.1
25.1
12.6
6.3
3.2
1.6
0.8
0.4
0.2
3.1
ge -
2.9
0.1
ut V
olta
3.7
Inp
3.5
VI -
GND
3.3
5.5
5.5
5.3
5.1
4.9
4.7
4.5
4.3
4.1
3.9
100.0
10
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. UNLESS OTHERWISE NOTED, this document contains PRODUCTION
DATA.
TPS81256
SLVSAZ9C JUNE 2012 REVISED FEBRUARY 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Device Options.......................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
3
4
7.1
7.2
7.3
7.4
7.5
7.6
4
4
4
5
5
5
Overview ................................................................... 9
Functional Block Diagram ......................................... 9
Feature Description................................................... 9
Device Functional Modes........................................ 11
17
17
18
18
Device Support......................................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
20
20
20
20
20
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (February 2015) to Revision C
Page
Reversed D & E dimensions in MicroSiP DC/DC Module Package Dimensions to match MECHANICAL DATA
drawing; and, changed "8-bump" to "9-bump" in the description. ........................................................................................ 21
Page
Added Device Information and ESD Ratings tables, Feature Description section, Device Functional Modes,
Application and Implementation section, System Examples, Power Supply Recommendations section, Device and
Documentation Support section, and Mechanical, Packaging, and Orderable Information section. .................................... 1
Changed the pinout drawing to match the device orientation shown on the MECHANICAL DATA drawing. ...................... 3
Changed SIP Package "Top View" image orientation to correctly match "YML LSB" symbolization with pin A1. .............. 21
Page
TPS81256
www.ti.com
5 Device Options
PART NUMBER
OUTPUT VOLTAGE
PACKAGE MARKING
CHIP CODE
TPS81256
5.0V
TT
VIN
SIP-9
(BOTTOM VIEW)
C1
VIN
B2
C2
VIN
B3
C3
VOUT
A1
GND
GND
A1
B1
B2
A2
GND
GND
A2
B3
A3
VOUT
VOUT
A3
C1
B1
VIN
C2
VOUT
C3
EN
EN
Pin Functions
PIN
NAME
NO.
EN
B2
I/O
DESCRIPTION
This is the enable pin of the device. Connecting this pin to ground forces the device into shutdown
mode. Pulling this pin high enables the device. This pin must not be left floating and must be
terminated.
GND
A1, A2, B1
VIN
C1, C2
A3, B3, C3
VOUT
Ground pin.
TPS81256
SLVSAZ9C JUNE 2012 REVISED FEBRUARY 2016
www.ti.com
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
(1)
Input voltage
Input current
MIN
MAX
UNIT
0.3
1.05
1.3
(3)
Power dissipation
Internally limited
40
85
40
150
55
125
(1)
(2)
(3)
(4)
(5)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltages are with respect to network ground terminal.
Limit the junction and the (top side) inductor case temperature to 110C, limit the (top side) capacitor case temperature to 85C for
2000h operation at maximum output power. Contact TI for more details on lifetime estimation.
Limit the (top side) inductor case temperature to 140C and the (top side) capacitor temperature to 115C for 100h operation. Contact TI
for more details on lifetime estimation.
In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may
have to be derated. Maximum ambient temperature (TA(max)) is dependent on the maximum operating junction temperature (TJ(max)), the
maximum power dissipation of the device in the application (PD(max)), and the junction-to-ambient thermal resistance of the part/package
in the application (JA), as given by the following equation: TA(max)= TJ(max)(JA X PD(max)). To achieve optimum performance, it is
recommended to operate the device with a maximum junction temperature of 125C, a maximum inductor case temperature of 125C
and a maximum capacitor case temperature of 85C.
V(ESD)
(1)
(2)
Electrostatic discharge
2000
1000
200
UNIT
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
2.5
RL
65
CEXT
Output capacitance
TA
NOM
MAX
UNIT
5.5
30
Ambient temperature
40
85
TJ
40
125
TCASE_IND
125
TCASE_CAP
85
TPS81256
www.ti.com
62
JB
31
JT
(1)
UNIT
C/W
Thermal data have been simulated with high-K board (per JEDEC standard).
TEST CONDITIONS
MIN
TYP
MAX
UNIT
30
50
20
SUPPLY CURRENT
Operating quiescent current into VIN
IQ
(1)
ISD
Shutdown current
VUVLO
(1)
(1)
0.85
5.0
Falling
2.0
2.1
Hysteresis
0.1
EN = GND
ENABLE
VIL
VIH
Ilkg
0.4
0.5
1.0
OUTPUT
VOUT
VOUT
4.92
5.08
4.85
5.2
4.85
5.2
35
mVpk
mVpk
POWER SWITCH
rDS(on)
Input-to-output On-resistance
Ilkg
EN = GND
ILIM
320
m
5
1180
mA
Overtemperature protection
140
Overtemperature hysteresis
20
MHz
IOUT = 0mA
Time from active EN to start switching
70
400
OSCILLATOR
fOSC
Oscillator frequency
TIMING
Start-up time
(1)
IOUT = 0mA
Time from active EN to VOUT
Maximum values can vary over lifetime due to intrinsic capacitor ageing effects. For more details, refer to Thermal and Reliability
Information section.
Efficiency
vs Output current
vs Input voltage
Figure 1, Figure 3
Figure 2
Submit Documentation Feedback
TPS81256
SLVSAZ9C JUNE 2012 REVISED FEBRUARY 2016
www.ti.com
Figure 4, Figure 5,
Figure 6
VO
DC output voltage
vs Input voltage
Figure 7
IO
vs Input voltage
Figure 8
VO
vs Output current
Figure 8
ICC
Supply current
vs Input voltage
Figure 10
ILIM
Input current
vs Output current
Figure 11
Video 1
Video 2
Video 3
Video 4
Video 5
Video 6
Video 7
Video 8
Video 9
Overload Response
Video 10
Start-Up Response
TPS81256
www.ti.com
100
100
95
VI = 4.2 V
98
VI = 3.6 V
IO = 300 mA
96
90 VI = 4.5 V
94
92
80
VI = 2.7 V
75
VI = 2.9 V
Efficiency - %
85
Efficiency - %
VO = 5 V,
PFM/PWM Operation
VI = 3.3
70
IO = 100 mA
90
88
86
84
IO = 10 mA
82
IO = 1 mA
80
65
IO = 500 mA
78
60
76
74
VO = 5 V,
PFM/PWM Operation
55
50
0.1
10
100
IO - Output Current - mA
72
70
2.7
1000
2.9
VO - DC Output Voltage - V
Efficiency - %
TA = 85C
75
70
4.5
5.1
5.05
VI = 4.5 V
VI = 3.6 V
5
VI = 2.7 V
65
60
0.1
10
100
IO - Output Current - mA
4.95
0.1
1000
VI = 3.2 V, TA = 85C
VI = 3.6 V, TA = 85C
10
100
IO - Output Current - mA
1000
5.05
VI = 4.3 V,
TA = 85C
VO = 5 V,
PWM Operation
5
VI = 3.2 V, TA = 25C
VI = 4.3 V,
TA = 25C
VO - DC Output Voltage - V
5.03
VO - DC Output Voltage - V
4.3
VI = 5.1 V
TA = 25C
80
4.1
VO = 5 V,
PFM/PWM Operation
TA = -40C
90
85
100
VI = 3.6 V,
95 VO = 5 V,
PFM/PWM Operation
3.1
VI = 3.6 V, TA = 25C
5.01
VI = 4.3 V, TA = -40C
VI = 3.6 V, TA = -40C
4.99
VI = 3.2 V, TA = -40C
4.97
10
100
IO - Output Current - mA
VI = 2.9 V
4.9
VI = 3.2 V
VI = 3.3 V
VI = 3.6 V
4.85
VI = 4.2 V
VI = 4.5 V
4.8
VO = 5 V,
PFM/PWM Operation
4.95
0.1
VI = 2.7 V
4.95
1000
4.75
200
300
400
TPS81256
SLVSAZ9C JUNE 2012 REVISED FEBRUARY 2016
www.ti.com
5.55
1200
VO = 5 V,
5.5 PFM/PWM Operation
VO = 5 V,
1100 PWM Operation
VO - DC Output Voltage - V
5.45
5.4
IO = 500 mA
5.35
5.3
IO = 100 mA
5.25
IO = 10 mA
5.2
5.15
5.1
5.05
800
TA = -40C
700
TA = 25C
600
500
TA = 85C
400
200
2.5 2.75
4.95
2.9 3.1 3.3 3.5 3.7 3.9 4.1 4.3 4.5 4.7 4.9 5.1 5.3 5.5
VI - Input Voltage - V
75
VO = 5 V,
PFM/PWM Operation
45
70
65
Supply Current - mA
30
25
VI = 3.3 V
20
VI = 3.6 V
VI = 2.7 V
15
VO = 5 V,
IO = 0 mA
TA = 85C
60
40
35
50
VO - Peak-to-Peak Output Ripple Voltage - mV
900
300
TA = 25C
55
50
45
40
35
30
TA = -40C
25
20
15
10
VI = 4.2 V
10
5
0
1000
100
200
300
400
500
600
700
0
2.5 2.7 2.9 3.1 3.3 3.5 3.7 3.9 4.1 4.3 4.5 4.7 4.9
VI - Input Voltage - V
1.3
VO = 5 V,
PFM/PWM Operation
1.2
1.1
VI = 2.6 V
1
0.9
VI = 3 V
0.8
VI = 3.3 V
VI = 3.6 V
0.7
VI = 4.2 V
0.6
VI = 4.5 V
0.5
0.4
0.3
0.2
0.1
0
100 200 300 400 500 600 700 800 900 1000
TPS81256
www.ti.com
8 Detailed Description
8.1 Overview
The TPS81256 is a stand-alone, synchronous, step-up converter module. The converter operates at a quasiconstant 4-MHz frequency pulse width modulation (PWM) at moderate to heavy load currents. At light load
currents, the TPS81256 converter operates in power-save mode with pulse frequency modulation (PFM).
L
1H
DC/DC CONVERTER
VOUT
PMOS
NMOS
2.2F
Valley
Current
Sense
Modulator
Softstart
EN
Control
Logic
x2
Error
Amplifier
Gate Driver
CO
VREF
Thermal
Shutdown
Undervoltage
Lockout
GND
TPS81256
SLVSAZ9C JUNE 2012 REVISED FEBRUARY 2016
www.ti.com
IOUT(DC) = IIN(CL) g
VOUT
g h
VIN
(1)
The output current, IOUT(DC), is the average of the rectifier ripple current waveform. When the load current is
increased such that the lower peak is above the current limit threshold, the off-time is increased to allow the
current to decrease to this threshold before the next on-time begins (so called frequency fold-back mechanism).
When the current limit is reached the output voltage decreases during further load increase.
10
TPS81256
www.ti.com
11
TPS81256
SLVSAZ9C JUNE 2012 REVISED FEBRUARY 2016
www.ti.com
DC/DC Converter
L
VIN
VOUT
VOUT
VIN
Co
CI
CEXT
EN
GND
ENABLE
GND
IOUT g (VOUT
VIN )
C g VOUT g f
(2)
Where f is the switching frequency which is 4MHz (typically.) and C is the effective output capacitance. Notice
the TPS81256 device already incorporates ca. 1.2F effective output capacitance.
In practice, the total ripple is larger due to the ESR of the output capacitor. This additional component of the
ripple can be calculated using Equation 3:
12
(3)
TPS81256
www.ti.com
PFM/PWM efficiency
PFM/PWM and PWM load transient response
During the recovery time from a load transient, the output voltage can be monitored for settling time, overshoot or
ringing that helps judge the converters stability. Without any ringing, the loop has usually more than 45 of phase
margin.
Table 3. Recommended Capacitor CEXT
(1)
REFERENCE
DESCRIPTION
CEXT
GRM188R61C475KAAJ, muRata
13
TPS81256
SLVSAZ9C JUNE 2012 REVISED FEBRUARY 2016
www.ti.com
VI = 3.6 V,
VO = 5.0 V
VI = 2.7 V
VI = 4.5 V
VI = 3.6 V
670mA
830mA
VO = 5.0 V,
IO = 0 mA
VI = 3.6 V,
VO = 5.0 V
VI = 3.6 V,
VO = 5.0 V
VI = 2.7 V,
VO = 5.0 V
VI = 4.5 V,
VO = 5.0 V
14
TPS81256
www.ti.com
VO = 5.0 V
40mA to 400mA
Load Step
DC/DC Converter
L
5.0 V, up to 550mA
VOUT
(1)
CDECOUPLING
VIN
3.3 V .. 4.8 V
4.7F
VIN
CO
EN
CI
GND
CLASS-D APA
Audio Input
Audio Input
EN APA
EN DC/DC
GND
(1)
The capacitor is not only required to decouple the audio power amplifier,
but is also required to stable operation of the SMPS converter.
The SMPS converter should be located in the close vicinity of the audio power amplifier.
15
TPS81256
SLVSAZ9C JUNE 2012 REVISED FEBRUARY 2016
www.ti.com
DC/DC Converter
L
VIN
3.0 V .. 4.35 V
VUSB
VOUT
5V, 500mA
USB-DCP Port
VIN
CO
CI
EN
GND
4.7F
16V X5R (0603)
ENABLE
GND
bq24156A
VBUS = +5V
VBUS
CIN
LO 1.0 mH
RSNS
VBAT
68mW
CO
CO
10 mF
47 mF
SW
CBOOT
1 mF
10 nF
PMID
CIN
PACK+
BOOT
CCSIN
PGND
4.7 mF
0.1 mF
CSIN
SCL
CSOUT
SDA
0.1 mF
STAT
OTG
CD
PACK
CCSOUT
VREF
CVREF
1 mF
16
TPS81256
www.ti.com
11 Layout
11.1 Layout Guidelines
In making the pad size for the SiP LGA balls, it is recommended that the layout use non-solder-mask defined
(NSMD) land. With this method, the solder mask opening is made larger than the desired land area, and the
opening size is defined by the copper pad width. Figure 23 shows the appropriate diameters for a MicroSiP
layout.
M0200-01
COPPER PAD
Non-solder-mask
defined (NSMD)
0.30mm
(1)
(2)
(3)
(4)
(5)
(6)
SOLDER MASK
OPENING
0.360mm
(5)
COPPER
THICKNESS
STENCIL (6)
OPENING
STENCIL THICKNESS
0.34mm diameter
0.1mm thick
Circuit traces from non-solder-mask defined PWB lands should be 75m to 100m wide in the exposed area inside the solder mask
opening. Wider trace widths reduce device stand off and affect reliability.
Best reliability results are achieved when the PWB laminate glass transition temperature is above the operating the range of the
intended application.
Recommend solder paste is Type 3 or Type 4.
For a PWB using a Ni/Au surface finish, the gold thickness should be less than 0.5mm to avoid a reduction in thermal fatigue
performance.
Solder mask thickness should be less than 20 m on top of the copper circuit pattern.
For best solder stencil performance use laser cut stencils with electro polishing. Chemically etched stencils give inferior solder paste
volume control.
17
TPS81256
SLVSAZ9C JUNE 2012 REVISED FEBRUARY 2016
www.ti.com
The TPS81256 is equipped with a thermal shutdown that will inhibit power switching at high junction
temperatures. The activation threshold of this function, however, is above 125C to avoid interfering with normal
operation. Thus, it follows that prolonged or repetitive operation under a condition in which the thermal shutdown
activates necessarily means that the components internal to the MicroSiP package are subjected to high
temperatures for prolonged or repetitive intervals, which may damage or impair the reliability of the device.
MLCC capacitor reliability/lifetime is dependant on temperature and applied voltage conditions. At higher
temperatures, MLCC capacitors are subject to stronger stress. On the basis of frequently evaluated failure rates
determined at standardized test conditions, the reliability of all MLCC capacitors can be calculated for their actual
operating temperature and voltage.
18
TPS81256
www.ti.com
1000
100
10
0.1
0.01
20
40
60
80
100
120
Capacitor Case Temperature ( C)
140
G000
19
TPS81256
SLVSAZ9C JUNE 2012 REVISED FEBRUARY 2016
www.ti.com
12.3 Trademarks
MicroSiP, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
12.5 Glossary
SLYZ022 TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
20
TPS81256
www.ti.com
BOTTOM VIEW
YML
LSB
CC
A1
B1
C1
A2
B2
C2
A3
B3
C3
Code:
CC Package marking Chip Code (see Package Option Addendum for more details)
21
www.ti.com
2-Feb-2016
PACKAGING INFORMATION
Orderable Device
Status
(1)
Eco Plan
Lead/Ball Finish
(2)
(6)
(3)
Op Temp (C)
Device Marking
(4/5)
TPS81256SIPR
ACTIVE
uSiP
SIP
3000
Green (RoHS
& no Sb/Br)
Call TI
Level-2-260C-1 YEAR
-40 to 85
TT
TXI256
TPS81256SIPT
ACTIVE
uSiP
SIP
250
Green (RoHS
& no Sb/Br)
Call TI
Level-2-260C-1 YEAR
-40 to 85
TT
TXI256
(1)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
Samples
www.ti.com
2-Feb-2016
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
2-Feb-2016
Device
TPS81256SIPR
SIP
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
3000
178.0
9.0
Pack Materials-Page 1
2.83
B0
(mm)
K0
(mm)
P1
(mm)
3.18
1.2
4.0
W
Pin1
(mm) Quadrant
8.0
Q2
2-Feb-2016
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TPS81256SIPR
uSiP
SIP
3000
223.0
194.0
35.0
Pack Materials-Page 2
IMPORTANT NOTICE
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changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest
issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and
complete. All semiconductor products (also referred to herein as components) are sold subject to TIs terms and conditions of sale
supplied at the time of order acknowledgment.
TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TIs terms
and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary
to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily
performed.
TI assumes no liability for applications assistance or the design of Buyers products. Buyers are responsible for their products and
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Applications
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