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Kuwait University

Computer Engineering Department


Computer Architecture Lab
Lab 4: Partitioning the Single Cycle MIPS Processor into Five Pipeline Stages
Prepared By: Eng. Ibrahim Sorkhoh

1. LEARNING OBJECTIVES

To understand the idea of partitioning the processor into pipelined stages.

To know how to build a code without any dependency in a pipelined system

To know how to test a pipelined system using vector waveforms.

2. THE MIPS FIVE STAGES


The mips pipelined processor has five stages that perform the following operations.
1. Instruction fetch stage:
a. Increments the PC
b. Fetches the instruction
c. Executes a jump if needed.
2. Instruction decode stage:
a. Extracts from the instruction the required fields such as the register indices and
the constants for every instruction format.
b. It also generates the required control signals
c. Computes any branch or jump address will be used to jump to an instruction in
the code.
3. Instruction Execution:
a. performs any operation required in the ALU.
4. Memory Stage:
a. reads or writes to the memory.
5. Write-Back Stage:
a. Writes to the register file.

LAB EXERCISE #4:


PARTITIONING THE MIPS PROCESSOR INTO FIVE PIPELINE STAGES
Name:
Name:

ID:
ID:

1. PROBLEM STATEMENT
Modify the single cycle MIPS processor by partitioning it into 5 stages. The stages must
perform the operations specified above. After you finish from partitioning the stages, you have to
write a code that will not cause any dependency between the instructions. This is can be done by
inserting NOP instructions (opcode = (0000)2) between every two instructions in the code.

2. DESIGN PROCEDURE
1. Determine the components of every stage by filling Table 2.
#

Instruction
Fetch

Increments
the PC

Extracts from the


instruc5on the required
elds such as the register
indices and the constants
for every instruc5on
format.

Computes The
addresses for the
Data Memory

Writes to the
memory

Fetches the
instruc5on

Generates the required


control signals

Computes values
to be stored in
the register le.

Reads from the


memory

---

---

---

---

---

---

---

3
---

Instruction Decode

Computes any branch or


jump address will be used
to jump to an instruc5on in
the code.

Execution

Memory

Write Back
Writes to the
registers le.

Reads R[rs.] and R[rt.].


---

Table 1. Stages Tasks.

Instruction
Fetch

Incrementer

Instruc5ons
Memory

Instruction
Decode

Execution

Memory

Write Back

PC
Table 2. Stages Components.

1. Determine the values, the indices and the fields required in each stage and its source
stage. Fill Table 3.
#
1
2

Instruction
Fetch

Instruction
Decode

Execution

Instruc5on
rd

3
4
5
6
7
8
9
10
11
12
13
14
15
Table 3. Value needed in each stage.

2. Determine the signals required in each stage. Fill Table 4.

Memory

Write Back

# Instruction
Decode

Execution

Memory

Write Back

1
2
3
4
5
6
7
8
9
10
11
Table 4. Control Signals

3. Modify Figure 1 by adding a flip-flop in every point that separates a stage from another.
4. After finishing adding the pipeline registers, modify the stages so they implement the
required logic correctly.
5. Open Quartus project that includes the single-cycle implementation of the MIPS
processor.
6. Open the single-cycle BDF file and copy all the file content.
7. Create a new BDF file and paste all the single-cycle design there.
8. Open Quartus Mega wizard and create 1-bit, 2-bits, 3-bits, 4-bits, 12-bits and 16-bits
flips-flops. We need in all of these flip-flops an enable signal and a synchronous clear.
9. Use the flip-flops created in step 6 to partition the stages and add the necessary logic.
10. Test your design by creating a code that does not exhibit any dependency between the
instructions and a proper vector waveform file.

3. WHAT TO SUBMIT
1. The Exercise Sheet.
2. The BDF design file.

3. The testing code.


4. The vector waveform simulation files.

Figure 1. MIPS processor.