Core Elective II
Open Elective I
Laboratory I
Seminar I
Course Title
Transform Techniques
Advanced Digital Signal Processing
Random Processes and Time Series Analysis
Biomedical Signal Processing
Radar Signal Processing
VLSI Signal Processing
Advanced Data Communications
Detection and Estimation Theory
Digital System Design
Wireless Communications and Networks
Embedded System Design
Device Modeling
Signal Processing Lab-I
Seminar
Total Credits
I Year II Semester
Category
Core Course IV
Core Course V
Core Course VI
Core Elective III
Core Elective IV
Open Elective II
Laboratory II
Seminar II
Total Credits
Course Title
Int.
Ext.
marks marks
25
75
25
75
25
75
25
75
4
4
4
4
-----
4
4
4
4
25
75
--
25
75
--
25
50
75
--
--24
4
4
8
2
2
28
Int.
Ext.
marks marks
25
75
25
75
25
75
25
75
4
4
4
4
-----
4
4
4
4
25
75
--
25
75
--
25
50
75
--
--24
4
4
8
2
2
28
II Year - I Semester
Course Title
Comprehensive Viva-Voce
Project work Review I
Int.
Ext.
marks marks
-100
50
--
Int.
Ext.
marks marks
50
--150
Total Credits
----
-24
24
4
12
16
8
16
24
4
12
16
II Year - II Semester
Course Title
Project work Review II
Project Evaluation (Viva-Voce)
Total Credits
----
(Core Elective I)
(Core Elective I)
RADAR SIGNAL PROCESSING
UNIT-I:
Introduction: Radar Block Diagram, Radar Equation, Information Available from Radar Echo, Review of
Radar Range Performance General Radar Range Equation, Radar Detection with Noise Jamming, Beacon
and Repeater Equations, Bistatic Radar.
Matched Filter Receiver Impulse Response, Frequency Response Characteristic and its Derivation,
Matched Filter and Correlation Function, Correlation Detection and Cross-Correlation Receiver, Efficiency of
Non-Matched Filters, Matched Filter for Non-White Noise.
UNIT II:
Detection of Radar Signals in Noise: Detection Criteria Neyman-Pearson Observer, Likelihood-Ratio
Receiver, Inverse Probability Receiver, Sequential Observer, Detectors Envelope Detector, Logarithmic
Detector, I/Q Detector. Automatic Detection - CFAR Receiver, Cell Averaging CFAR Receiver, CFAR Loss,
CFAR Uses in Radar, Radar Signal Management Schematics, Component Parts, Resources and
Constraints.
UNIT III:
Waveform Selection: Radar Ambiguity Function and Ambiguity Diagram Principles and Properties;
Specific Cases Ideal Case, Single Pulse of Sine Wave, Periodic Pulse Train, Single Linear FM Pulse,
Noiselike Waveforms, Waveform Design Requirements, Optimum Waveforms for Detection in Clutter,
Family of Radar Waveforms.
UNIT IV:
Pulse Compression in Radar Signals: Introduction, Significance, Types. Linear FM Pulse Compression
Block Diagram, Characteristics, Reduction of Time Sidelobes, Stretch Techniques, Generation and
Decoding of FM Waveforms Block Schematic and Characteristics of Passive System, Digital Compression,
SAW Pulse Compression.
UNIT V:
Phase Coding Techniques: Principles, Binary Phase Coding, Barker Codes, Maximal Length Sequences
(MLS/LRS/PN), Block Diagram of a Phase Coded CW Radar.
Poly Phase Codes: Frank Codes, Costas Codes, Non-Linear FM Pulse Compression, Doppler Tolerant PC
Waveforms Short Pulse, Linear Period Modulation (LPM/HFM). Sidelobe Reduction for Phase Coded PC
Signals.
TEXT BOOKS:
nd
1. Radar Handbook - M.I. Skolnik, 2 Ed., 1991, McGraw Hill.
2. Radar Design Principles: Signal Processing and The Environment - Fred E. Nathanson, 2nd Ed.,
1999, PHI.
rd
3. Introduction to Radar Systems - M.I. Skolnik, 3 Ed., 2001, TMH.
REFERENCE BOOKS:
1.
Radar Principles - Peyton Z. Peebles, Jr., 2004, John Wiley.
2.
Radar Signal Processing and Adaptive Systems - R. Nitzberg, 1999, Artech House.
3.
Radar Design Principles - F.E. Nathanson, 1st Ed., 1969, McGraw Hill.
(Core Elective I)
VLSI SIGNAL PROCESSING
UNIT -I:
Introduction to DSP: Typical DSP algorithms, DSP algorithms benefits, Representation of DSP
algorithms
Pipelining and Parallel Processing: Introduction, Pipelining of FIR Digital filters, Parallel
Processing, Pipelining and Parallel Processing for Low Power
Retiming: Introduction Definitions and Properties Solving System of Inequalities Retiming
Techniques
UNIT II:
Folding and Unfolding: Folding: Introduction -Folding Transform - Register minimization
Techniques Register minimization in folded architectures folding of multirate systems
Unfolding: Introduction An Algorithm for Unfolding Properties of Unfolding critical Path,
Unfolding and Retiming Applications of Unfolding
UNIT -III:
Systolic Architecture Design: Introduction Systolic Array Design Methodology FIR Systolic
Arrays Selection of Scheduling Vector Matrix Multiplication and 2D Systolic Array Design
Systolic Design for Space Representations contain Delays
UNIT -IV:
Fast Convolution: Introduction Cook-Toom Algorithm Winogard algorithm Iterated Convolution
Cyclic Convolution Design of Fast Convolution algorithm by Inspection
UNIT -V:
Low Power Design: Scaling Vs Power Consumption Power Analysis, Power Reduction techniques
Power Estimation Approaches
Programmable DSP: Evaluation of Programmable Digital Signal Processors, DSP Processors for
Mobile and Wireless Communications, Processors for Multimedia Signal Processing
TEXT BOOKS:
1. VLSI Digital Signal Processing- System Design and Implementation Keshab K. Parhi, 1998,
Wiley Inter Science.
2. VLSI and Modern Signal Processing Kung S. Y, H. J. While House, T. Kailath, 1985,
Prentice Hall.
REFERENCE BOOKS:
1. Design of Analog Digital VLSI Circuits for Telecommunications and Signal
Processing Jose E. France, Yannis Tsividis, 1994, Prentice Hall.
2. VLSI Digital Signal Processing Medisetti V. K, 1995, IEEE Press (NY), USA.
UNIT -I:
Minimization and Transformation of Sequential Machines: The Finite State Model Capabilities
and limitations of FSM State equivalence and machine minimization Simplification of incompletely
specified machines.
Fundamental mode model Flow table State reduction Minimal closed covers Races, Cycles
and Hazards.
UNIT -II:
Digital Design: Digital Design Using ROMs, PALs and PLAs, BCD Adder, 32 bit adder, State
graphs for control circuits, Scoreboard and Controller, A shift and add multiplier, Array multiplier,
Keypad Scanner, Binary divider.
UNIT -III:
SM Charts: State machine charts, Derivation of SM Charts, Realization of SM Chart, Implementation
of Binary Multiplier, dice game controller.
UNIT -IV:
Fault Modeling & Test Pattern Generation: Logic Fault model Fault detection & RedundancyFault equivalence and fault location Fault dominance Single stuck at fault model Multiple stuck at
fault models Bridging fault model.
Fault diagnosis of combinational circuits by conventional methods Path sensitization techniques,
Boolean Difference method Kohavi algorithm Test algorithms D algorithm, PODEM, Random
testing, Transition count testing, Signature analysis and test bridging faults.
UNIT - V:
Fault Diagnosis in Sequential Circuits: Circuit Test Approach, Transition Check Approach State
identification and fault detection experiment, Machine identification, Design of fault detection
experiment
TEXT BOOKS:
1. Fundamentals of Logic Design Charles H. Roth, 5th Ed., Cengage Learning.
2. Digital Systems Testing and Testable Design Miron Abramovici, Melvin A.
Breuer and Arthur D. Friedman- John Wiley & Sons Inc.
3. Logic Design Theory N. N. Biswas, PHI
REFERENCE BOOKS:
1. Switching and Finite Automata Theory Z. Kohavi , 2nd Ed., 2001, TMH
th
2. Digital Design Morris Mano, M.D.Ciletti, 4 Edition, PHI.
3. Digital Circuits and Logic Design Samuel C. Lee , PHI
10
(Open Elective I)
11
REFERENCE BOOKS:
1. Principles of Wireless Networks Kaveh Pah Laven and P. Krishna Murthy, 2002, PE.
2. Wireless Communication Technology-Roy Blacke, CENGAGE Learning, 2012
3. Wireless Digital Communications Kamilo Feher, 1999, PHI.
4. Wireless Communication and Networking William Stallings, 2003, PHI.
5. Wireless Communication Upen Dalal, Oxford Univ. Press.
6. Wireless Communications and Networking Vijay K. Gary, Elsevier.
12
(Open Elective I)
EMBEDDED SYSTEM DESIGN
UNIT -I:
Introduction to Embedded Systems: Definition of Embedded System, Embedded Systems Vs
General Computing Systems, History of Embedded Systems, Classification, Major Application Areas,
Purpose of Embedded Systems, Characteristics and Quality Attributes of Embedded Systems.
UNIT -II:
Typical Embedded System: Core of the Embedded System: General Purpose and Domain Specific
Processors, ASICs, PLDs, Commercial Off-The-Shelf Components (COTS), Memory: ROM, RAM,
Memory according to the type of Interface, Memory Shadowing, Memory selection for Embedded
Systems, Sensors and Actuators, Communication Interface: Onboard and External Communication
Interfaces.
UNIT -III:
Embedded Firmware: Reset Circuit, Brown-out Protection Circuit, Oscillator Unit, Real Time Clock,
Watchdog Timer, Embedded Firmware Design Approaches and Development Languages.
UNIT -IV:
RTOS Based Embedded System Design: Operating System Basics, Types of Operating Systems,
Tasks, Process and Threads, Multiprocessing and Multitasking, Task Scheduling.
UNIT -V:
Task Communication: Shared Memory, Message Passing, Remote Procedure Call and Sockets,
Task Synchronization: Task Communication/Synchronization Issues, Task Synchronization
Techniques, Device Drivers, How to Choose an RTOS.
TEXT BOOKS:
1.
Introduction to Embedded Systems - Shibu K.V, Mc Graw Hill.
REFERENCE BOOKS:
1.
Embedded Systems - Raj Kamal, TMH.
2.
Embedded System Design - Frank Vahid, Tony Givargis, John Wiley.
3.
Embedded Systems Lyla, Pearson, 2013
4.
An Embedded Software Primer - David E. Simon, Pearson Education.
13
(Open Elective I)
DEVICE MODELING
UNIT -I:
Introduction to Semiconductor Physics: Review of Quantum Mechanics, Boltzman transport
equation, Continuity equation, Poisson equation.
Integrated Passive Devices: Types and Structures of resistors and capacitors in monolithic
technology, Dependence of model parameters on structures
UNIT -II:
Integrated Diodes: Junction and Schottky diodes in monolithic technologies Static and Dynamic
behavior Small and large signal models SPICE models
Integrated Bipolar Transistor: Types and structures in monolithic technologies Basic model (EberMoll) Gunmel - Poon model- dynamic model, Parasitic effects SPICE model Parameter
extraction
UNIT -III:
Integrated MOS Transistor: NMOS and PMOS transistor Threshold voltage Threshold voltage
equations MOS device equations Basic DC equations second order effects MOS models small
signal AC characteristics MOS FET SPICE model level 1, 2, 3 and 4
UNIT -IV:
VLSI Fabrication Techniques: An overview of wafer fabrication, Wafer Processing Oxidation
Patterning Diffusion Ion Implantation Deposition Silicon gate nMOS process CMOS
processes n-well- p-well- twin tub- Silicon on insulator CMOS process enhancements
Interconnects circuit elements
UNIT -V:
Modeling of Hetero Junction Devices: Band gap Engineering, Band gap Offset at abrupt Hetero
Junction, Modified current continuity equations, Hetero Junction bipolar transistors (HBTs), SiGe
TEXT BOOKS:
1. Introduction to Semiconductor Materials and Devices Tyagi M. S, 2008, John Wiley Student
Edition.
2. Solid State Circuits Ben G. Streetman, Prentice Hall, 1997
REFERENCE BOOKS:
1. Physics of Semiconductor Devices Sze S. M, 2nd Edition, Mcgraw Hill, New York, 1981.
2. Introduction to Device Modeling and Circuit Simulation Tor A. Fijedly, Wiley-Interscience,
1997.
3. Introduction to VLSI Systems: A Logic, Circuit and System Perspective Ming-BO Lin, CRC
Press, 2011
14
Basic Operations on Signals, Generation of Various Signals and finding its FFT.
Program to verify Decimation and Interpolation of a given Sequences.
Program to Convert CD data into DVD data
Generation of Dual Tone Multiple Frequency (DTMF) Signals
Plot the Periodogram of a Noisy Signal and estimate PSD using Periodogram and Modified
Periodogram methods
Estimation of Power Spectrum using Bartlett and Welch methods
Verification of Autocorrelation Theorem
Parametric methods (Yule-Walker and Burg) of Power Spectrum Estimation
Estimation of data series using Nth order Forward Predictor and comparing to the Original
Signal
Design of LPC filter using Levinson-Durbin Algorithm
Computation of Reflection Coefficients using Schur Algorithm
To study Finite Length Effects using Simulink
ECG signal compression.
Design and verification of Matched filter
Adaptive Noise Cancellation using Simulink
Design and Simulation of Notch Filter to remove 60Hz Hum/any unwanted frequency
component of given Signal (Speech/ECG)
15