International Journal of Innovative Research in Engineering Applications (IJIREA) Volume 1, Issue 1 Mar

2017

A STUDY OF DOUBLE DATA RATE

SYNCHRONOUS DYNAMIC RANDOM
ACCESS MEMORY CONTROLLER
IMPLEMENTED ON FPGA
Salim Ahmad, Amrita Khera*
Dept. of ECE
TITR, Bhopal
Madhya Pradesh, India
*
engg.ams@gmail.com

Abstract Electronic Engineering with prime focus Memory enhancement and controllers has become the most

popular engineering discipline within a short panel time. Fundamentally this engineering discipline deals with the
best practice for developing semi-conductor devices for various digital communication and networking based
applications. Most of the world is dependent upon memory system which in fact signifies the predominance of
electronic devices to address various issues pertaining to high performance, architecture, and quality read/write
access.
In this paper, different novel methods and frameworks are being proposed for the reduction/suppression of idle
cycles required due to frequent switching between read and write operations over the memory. To improve the
quality in the memory controller along with improvement in the basic hardware attributes i.e. power, area and delay.
The main objective of this paper is to develop an innovative understanding over control algorithms for the
improvisation of memory R/W operations within the permissible constraints of the hardware attributes. Extensive
literature survey was carried out on the identified research problem that is being solved by various strategies one by
one in the following sections along with the simulation, modeling in FPGA, HDL and/or VERILOG environment
and with some theoretical analysis.

1. INTRODUCTION
In current digital electronics era, memory access and control via any hardware based language (such as HDL,
FPGA, and etc) has been evolving into active search area which encompasses initialization, r/w operations, access
control and other formal and informal analysis. In general, languages are exploited to address the circuit
connectivity between operator to a memory location (for example flip-flop) and hierarchy based architecture is
properly designed and implemented within the proposed constraints of hardware and/or operator.
The history around Double Data Rate (DDR) Synchronous Dynamic Random Access Memory research reveals that
the prime focus of various memory controllers proposed and designed exploit the initialization, read/write accesses
and memory refresh. Even though operations performed over storage domain is considered as a complex process
which induces a significant delay and its design requires considerable command interface. Due to the recent
developments in parallel processing, FPGA architecture, processor speeds and etc presented a platform for the
improvement of the pipeline features allow the possibility to enhance speed and burst access through simple
reference to system interface which in turn reduces the latency (or delay) of the entire process.

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CONTROLLER IMPLEMENTED ON FPGA
This is a commonly accepted fact that exploiting the architectural design would address the issues related to area
and delay in an effective and efficient manner. This paper is initiated with a clear focus to boost this fact into reality
and introduce a detail literature survey on existing memory controllers in DDR SDRAM domain that offers
significant improvements in delay and area while performance improvements are limited. In this paper, the detail
analysis was carried out in phases which deals with study of existing approach and evaluate corresponding
advantages and limitations; progressively analyzing r/w process and data path pipelining for its effective operation
in FPGAs. The design would be consisting of several complex modules that operate on various operands and
commands which contribute significantly to equal by-pass module that reduces the overall latency and power of the
design. To ensure the feasibility of these designs a detail analysis was also carried by experimenting i.e. trading off
some resources (or factors) with others resources while keeping some of factors constant to optimize the delay of
the system effectively.
The vast majority of modern digital circuit-design revolves around these languages that offer the desired
control over circuit, device, or subsystem. The rapid escalations in digital communication and networking over the
years have paved ways for the need of high speed control operations over the memory access to utilize for various
applications and read/write operations. DDR SDRAM controllers have become a critical and imperative issue
among the researchers involved in hardware engineering and have evolved into active research area involving
analysis, coding, and pipelining. These coding techniques have similar coding and arithmetic operations associated
but the objectives, conditions, & purpose of using them differ from one another. There are several designs and
frameworks to address these issues that offer considerable advantages and limitations depending on the application
and the corresponding coding and hardware constraints.
Most of the present industrial clients are having conflicting demands about computation time, power
dissipation factor, and architecture quality. These demands are really troubling the present industry. This is a serious
need to think much about this situation in order to overcome the challenges arise due to conflicting demands. It can
be seen that memory access controller plays a imperative role in most of the designs that needs to be coded in
optimized way as most of the processor utilize r/w operations for the storage/retrieval of the digital information bits
while expressing in coding, the errors are often caused by the devices due to various coding factors making the
entire operation ubiquitous [1]. The current digital world is driven by the necessity rather than the requirement,
consider various banking and financial applications ranging from accounting to loans operated over memory control
domain. When proposed architecture of the hardware is insufficient or when the performance of hardware is limited
then more often we alter the programming logic design to ensure proper working of the system as expected.
Unfortunately, these changes arrive at a later stage of the testing and quality check process, and on occasions results
would be unanticipated and unforeseen which adds to the delay of the system over assessed. Due to the constant
exploration within the field of semiconductor and introduction of nano-technology, there are several commonly used
approaches were proposed for various classes of applications. Based on the simulation results, we observe that each
of existing approach has advantages as well as drawback in comparison with other approaches, as their advantages
and limitations are often complimentary to each other. To understand the advantages and limitation of any method it
is very important to know when you can use which method as the often tradeoff between area, power and
performance of the system which is widely accepted process for efficient and effective design of the system.

Figure 1: Attributes that define the effectiveness of the hardware design

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CONTROLLER IMPLEMENTED ON FPGA

Now-a-days significant amount of multimedia applications incorporate the Memory unit as a critical block
for major and complex operations. It is an evident fact that the complex problem that doesnt has a precise delay
response that could be easily deciphered because there are several parameters used in the computation. Typical
controller often provides an opportunity to fairly judge the delay and minimize based on defined factors and in
designated schedule of operations [1]. With the development of e-commerce, monetary transactions are shifting to
digital domain (internet) which led to need of financial transactions be conducted in real time. Engineers and
researchers have been actively investigating control operations in frequent accessing the memory with a prime focus
on chip area, performance and power will be appealing to computer manufacturer and user.
The primary steps in any design process were to comprehend, evaluate, analyze and characterize the
architecture of the system based on the requirement and application in which it would be incorporated. In some case,
it is subtle, imperceptible, and inflexible making it essentially a difficult task to recognize and approximate a
complex product or proposed method that cant be shown wrong and touched the initial aspects, but analyzed based
on the outcome as it changes with reference to application [3]. In this context, the main objective is the suppression
of the delays which are injected by the controller due to the frequent r/w switching of the memory access, there by
affecting the performance of the system. The affecting issues are classified based on the impact as LI delays;
switching impact delays; and HI delays. The current delays are generated due to switching action, if injected into the
hardware system interconnected memory, definitely would cause the malfunction of some of the sensitive apparatus
which are interconnected to the same system. According to the standards, which determine the level of impact on the
system, the power should attenuate/suppress the, thus safeguarding the data from damaging.
To achieve this, a number of methods are being proposed which are being considered in the following
sections while most of the present existing mitigation/reduction based control techniques are having conflicting
hardware characteristics about time, power, and area. These demands are really troubling the present electronic
industry. This is a serious need to think much about this situation in order to overcome the challenges arise due to
DDR SDRAM in particular.
To deal with the above challenges proper care should be taken while designing the controller in terms of
time, power, and area estimates. Hence our work was focused on gaining extensive knowledge about the SDRAM
control models. The inexactness of the development of this architecture is the main cause of frustration. The
excellence and scope of control based approaches doesnt limit to the SDRAM, but based on the time taken for the
possible read/write operations whose estimate is vital aspect for enhancing accurate system. It is evident that more
than one approach is essential so that there is a meaningful resource available for the estimation of the accurate
actual controller that is critical for unique application. Now-a-days, any of the existing or proposed memory
controller based application can be reviewed based on what it offers and how well it can be used.

2. Literature Survey
The main motive for the growing importance on understanding the essential concepts of a Double Data
Rate (DDR) Synchronous Dynamic Random Access Memory (SDRAM) is that it offers the general conceptual
model and frameworks of economic (in terms of power, area, delay) analysis and memory based operational,
transitional and maintenance phase requirements and characteristics. It is evident fact that there is no clear definition
of the process which could calculate and perform memory control benefit analysis without some logically accurate
approach. Furthermore, the model that offers the improvement largely depends on the sheer quantity of read/write
operations and pipeline architecture.
Based on the recent survey, it has been documented that nearly 23.6% of the delay in the system is due to
the un-optimized memory control. In addition, around 34% of the memory failure is due substantial amount of r/w
operations without proper parallel pipelining structure. Henceforth in this section, we want review existing control

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CONTROLLER IMPLEMENTED ON FPGA
structures and analyze its effects on the hardware attributes which acts as a vital factor in making efficient decisions
in memory controller design and implementation perspective. Several issues that plague the progress of the effort are
the common understanding which it very complex and highly improbable to precisely assess the entire memory
control hierarchy from design to development to timely delivering of the command [3]. The primary steps in any
process were to comprehend, evaluate, analyze and characterize the hardware system based on the requirement and
application in which it would be incorporated. Programming building is the procedure of concentrating on utilization
of designing to outline, improvement and upkeep of programming [1]. Engineering was instituted to address low
quality of programming, get activities surpassing time and plan under control, and guarantee that product is
fabricated efficiently, thoroughly, measurably, on time, on plan, and inside.
Programming procedure is that the one in the entire viewpoint being created of the item handle in
methodology. The examination sweat strategy could be a technique for evaluating the term of programming building
ventures [3]. Its ideally equipped to making introductory appraisals for the length of associate degree occupation in
light-weight of a proverbial time term for fixing a determination. These, with a span for fixing the merchandise
specific will be utilized as an area of a flip upward table (which contains variables in light weight of past
experience) to focus with length of every of the incidental periods of the work.

2.1 Background
Sharma, S., & Singh, B [4] presented a Synchronous Dynamic Random Access Memory (SDRAM) architecture
which offers high speed memory access controller called Zero Bus Turnaround. Zero Bus Turnaround has been
designed to exploit SRAM for applications wherein READ/WRITE is frequently executed. These transitions often
induce idle cycles that enhance delay of the system which in turn affect the performance of system. The ZBT
exploits this feature through parallel structuring and enhances the overall system performance on the basis of power,
delay and area. This structure is highly efficient while incorporated for networking based applications.
Reddy, N. S., Chokkakula, G., Devendra, B., &Sivasankaran, K. [5] presented an approach whose
preliminary consideration is based on the time taken for the possible operation to converge to the actual delay in the
entire memory control compilation. Henceforth, it is evident that the principle behind architecture should ensure that
controller is adaptive so as the memory receives/transmits the assigned bit which vital aspect for enhancing
performance of the system. It is defined by set of executable arithmetic logic which performs a computational
complex problem in an optimum manner as per the application requirement that concurrently run multi applications.
Hence, there is concern of delayed response after each operation over Double Data Rate Synchronous DRAM (DDR
SDRAM) a bit for the particular form is the major concern that was addressed. To extend the speed, burst access and
pipeline attributes to different applications in support DDR for both r/w based operations.
In addition, to achieve the improve performance while several ancillary issues regarding fall and rise in
edges are associated with double the bandwidth. Even though the controller is simple and easy to exploit
communication between modules and DRAM memory unit unfortunately there are several issues that needed to be
addressed such as; burst length, delay and area which are major problems. The simulation analysis was performed
over Modelsim and results show an improvement in bandwidth, latency and length of burst.
Zain, S., Puchner, H., Anderson, W., &Navalpakam, K. [6] presented a device that is simple and adaptive in
exploiting the hardware design and development to configure queries associated with the memory access into signals
in an effective and efficient manner. Without these reasonably improved attributes like buffer memory, address
values and interfacing, the capability of their architecture is limited. The leading and trailing edges are employed to
read and write information bits into memory. The simulation analysis was performed over various applications and
results show an improvement in power, latency and area based attributes
Naidu, G. B. S. R., & Rao, U. V. [7] presented that the primary steps involved in this design process were to realize,
represent, analyze and the characteristics of the system which it would be incorporated. In case of system
bandwidth, high density, flexible improved bandwidth and minimal cost with reference to code and architecture
drafted. When proposed architecture of the hardware is in sufficient or when the performance of hardware is limited
then look-up tables are employed to ensure proper working of the system. Hash Cam based framework is exploited
to optimize burst access that simulates using Xilinx FPGA for architecture as presented in the figure 2.

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CONTROLLER IMPLEMENTED ON FPGA

Figure 2: Third generation DDR architecture

Li, Q., Wang, M., & Yu, Y. [8] modified SDRAM controller technique that has been proved to be effective and
efficient in high speed 3GSPS data acquisition. This proposed approach starts with DDR SDRAM based principles
and the corresponding controller to provide an overview of the overhead-reduce strategy for the entire data access
requirements, factors that needs to be considered, hardware and software issues are also discussed. Furthermore,
analysis and results show that this design and implementation is effective in addressing the subsequent issues
associated with DDR SDRAM controller calls a memory location to merge their TOF-MS signal processing in an
effective manner. Software and hardware analysis shows that the feasibility and accuracy of this structure and
corresponding read/write operation would be around 93.6%.
Viswa, P. S., Krishna, R., &Taddi, G. [9] introduced a novel dedicated memory controller that offers efficient
operations that deals with execution read/write, revive of memory locations, and instatement of SDRAM within the
constraints of hardware attributes. This consists of a productive usage ASIC design that supports the reconfigurable
module of controller that offers an interface between bus-master and DDR SDRAM during execution phase.
Memory units are practically found in all frameworks and these days fast and elite recollections are in extraordinary
interest. The simulations results show promising results in terms of speed and latency.
Chen, G., Xiao, L., & Zhang, J. [10] introduces the basic working characteristics and timing analysis of DDR
SDRAM that are studied, and a universal DDR SDRAM controller based on FPGA is designed. The design function
simulation is performed under Modelsim, and testing and verification of the hardware was also completed under the
FPGA. Simulation results show that the controller can realize read-write control over DDR SDRAM with high readwrite efficiency and simple interface circuit
Bakshi, A., Pandey, S. S., Pradhan, T., &Dey, R. [11] introduced a novel memory controller structure that address
high-speed and great storage of image data processing. By the idea of ASIC design, some operations such as the
refresh and r/w basic operations over the memory layer unit, the user interface module and the control module are
integrated to manage the DDR2 SDRAM. Based on this technique simulation analysis prove that, the design is
feasible and effective, and the maximum transmission rate of 32 bit bus can reach 12.8Gbit/s.
Himabindu, P., Prasad, G. M. V., & Rao, A. S. [12] proposed a DDR SDRAM memory controller with FIFO
concept for logic functions such as read module, write module and refresh module are combined over Advanced
High-performance Bus (AHB). For the implementation of controller, all other blocks of operation are implemented
using serial interface implemented by considering the location between SDRAM and AHB wherein same
operational r/w and refresh commands are performed. The Variable Early Read command, where the read command
is issued one CAS latency before the termination of an ongoing data burst By using the Variable Early Read
command the effect of the CAS latency is minimized in terms of the effect on bandwidth. The enhanced bandwidth
technology achieved with this invention optimizes the remaining two access latencies (tRP and tRCD) for optimal
bandwidth. These optimizations in the AHB allow for much better bandwidth in real world applications
Singh, P., Reniwal, B., Vijayvargiya, V., &Vishvakarma, S. K. [13] introduced an in-expensive controller to
enhance the data transfer rate and to see how they impact frequency, latency and area of the system. The test signal

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CONTROLLER IMPLEMENTED ON FPGA
is given as the input (Vt), to controller was rigged up with high frequency clock by using Kintex7 FPGA which was
designed from the basic principles; refresh, r/w operations and initialization are checked for the optimized latency.
From the results, it can be observed that the power utilized is reduced, latency has been improved, and there was lot
of slice utilization present in the system. Thus, this system operates at higher speed within the constraints of
hardware constraints.
Bibay, P., Sahu, A. K., & Chandra, V. K. [14] presented a design that could efficient and feasible DDR SDRAM
controller. It is operated by incorporating various command and timing based signals that are associated with flow of
edge signals without affecting the performance of DDR. The memory operations that incorporate significantly high
amount of buffers which have enhanced the area, power, and delay associated with the system.
Sreehari, S., & Jacob, J. [15] presented that the original problem of memory controllers was in perspective to
initializing and refreshing the burst access of the DDR in an efficient and effective manner. This problem is solved
with high performance AMBA which is employed along with optimized pipelined architecture that could support
and sustain speedy operations. The enhanced controller would be able to mitigate the latency in memory access
based operations that would improve the performance of the system. The simulation results were operated over
MODELSIM while coding was implemented in VHDL. The results show an enhanced improvement in access time.
With escalation in hardware engineering, the integration of these systems in our everyday life has been growing
exponential with applications ranging from defense to agriculture. The requirement and memory control attributes
changes with the complexity of the application while data rate and latency are prime concerns of every application
now-a-days. Wang, S. H., Tian, Y. Y., & Chen, S. W. [16] illustrated the scope and developments in the memory
controller technology with a prime focus on DDR2 SDRAM with FPGA as basis. It is configured so as to register,
initialize, prioritize, and generate along with other functional command for control the memory based operations in
an effective manner. They referred delay as function of the power and commands sequence executed with the
amount of buffer employed. A DDR memory controller is described wherein a core domain capture clock is created
by programmable delaying the core clock of the memory controller.
The delay of this capture clock is typically calibrated during a power on the initialization sequence in
concert with a DDR memory in a system environment, thereby minimizing the effects of system delays and
increasing both device and system yield. An additional embodiment also includes programmable delaying the
incoming dqs signal. To compensate for voltage and temperature variations over time during normal operation, a
runtime dynamic calibration mechanism and procedure is also provided
Kagdelwar, M. M. N., &Lokhande, M. P. S [17] expressed that the architectural optimization provides the strength
of pipelining, Sub-pipelining and buffer analysis. Commonly speed is increased by operating with maximum buffers
simultaneously at the cost of increased area for architectures. Sub-pipelining can provide maximum speed up and the
better speed and area ratio as it optimizes the buffer allocation by resource sharing. DDR3 SDRAM (Double Data
Rate Three Synchronous Dynamic Random Access Memory) is employed for applications (such as image/video
processing and etc) wherein high speed is required. DDR3 SDRAM has addressed the growing demand on higher
bandwidth for storing in automated systems. Memory Controller controls and manages the flow of data in and from
memory unit in an optimized manner. Furthermore, the execution of controller is dictated by well-defined functions
that help in accomplishing improved performance with lower power consumption. The simulations results were
verified using VHDL wherein the work shows that the MC reduces delay by exploiting parallel processing by
pipelined stages.
Xinqiang, J., Xuefei, B., & Fan, Z. [18] presented a new approach for memory controller for DDR SDRAM based
on the introduction of the key technologies of the DDR SDRAM controller design. It provided an optimized address
mapping strategy, which improves the efficiency of burst access, then completed chip tape -out with 0.18 m CMOS
process. The PCB board -level test shows that this DDR SDRAM controller achieves the expected design
requirements and offers desired performance within the constraints associated with the application.
Wang, L., Wang, J., & Zhang, Q. [19] expressed that detail understanding of the memory transmission and control is
essential for designing an effective and efficient memory controller that addresses all attributes of hardware
engineering and its applications. This memory cycle incorporates all necessary engineering parameters and factors
that focus on the design and development of the executable codes essential for the application in consideration i.e.
satellite navigation system. The requirement of the high capacity and speed is evolving into a minimal requirement

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CONTROLLER IMPLEMENTED ON FPGA
of DDR SDRAM for navigation signal processing algorithms. A novel architecture with defined functions for
reading/writing operations associated with MC is presented. Software simulation and hardware experimental tests
prove the correctness and feasibility of this design with improved performance
Reddy, S. L., &Kumari, A. K [20] presented an approach that uses memory bandwidth or latency while formulating
the optimization strategy within constraints proposed. The need for efficient and optimum economic operation and
planning occupies a prominent position in the performance on memory controller. The controller needs to access the
processor speeds for search the memory locations via AHB with constraints over frequency and performance. This
architecture exploits FIFO, ping-ponging and burst access based transferring of the data which enhanced controller
performance.
Lakis, E., &Schoeberl, M. [21] defined a process of determining the most awful cases based on the execution time
of memory control in the system, so that the entire platform can meet the scheduling in a most economically manner.
In case the components need to be fixed (i.e. caches, operating system processor, memory and etc), the objective is
to calculate, for a single period of time, the power of every memory unit. Unfortunately the timing of refresh or
read/write operations is always changing, so the controller responds in a similar manner i.e. with increase in the
burst length and frequency that produces more power and vice-versa. This entails for optimal allocation of controller
participation in sharing the memory at the current interval of time to meet real-time system requirements. The results
show that the controller is optimized for the worst case and constant latency to provide a base of the memory
hierarchy for time-predictable system.
Gang, H. A. N. [22] presented an approach for enhancing the bandwidth of DDR memory in SDRAM system is
discussed in detail. DDR memory has an inherent feature called the Variable Early Read command, where the read
command is issued on CAS latency before the completion of the ongoing data burst and the effect of the CAS
latency is minimized in terms of the effect on bandwidth. The system and method optimizes the remaining two
access latencies (tRP and tRCD) for optimal bandwidth. The simulation results were promising in comparison with
other data processing systems.

3.Analysis
The hardware design is an expensive and gruesome process as the feasibility of design and its synthesis analysis
tend to have significant amount of variations; we cannot make realistic tradeoff between hardware and software
feasibility at the initial phase but its easy to address the issues pertaining to software in the mid-process which not
possible in hardware design. This may lead to optimistic designs which in turn results in high power and lower
performance as a consequence. Moreover hardware analysis is required to be evaluated by means of a well defined
process that must be properly evaluated for consistency. The complexity level is determined based on some of
system characteristics of DDR SDRAM are presented below [23-27].
1.
2.
3.
4.
5.
6.
7.
8.

Data Communication
Information refreshing and processing
Buffer and pipelining interfacing
Detailed composition of memory location
Operational data rate/bandwidth
Regular dynamic updating
A thorough analysis/processing
Either modular and complete reusability for different applications

The evaluation of DDR SDRAM Memory Controller design and development complexity should also be taken into
consideration obscure program interfaces, database configuration along with detail interfacing, and supported
optimized approaches. The evaluation of the complexity can be illustrated based up on levels of complexity which
will focus based on the application in consideration [28].

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4.Conclusion
In this paper, we illustrated different methods and designs that are commonly employed for the
reduction/suppression of idle cycles (during allocation of buffer locations and refresh process) required due to
frequent switching between read and write operations over the memory. To improve the performance of the DDR
SDRAM memory controller, we conclude that the improvements in the basic hardware attributes i.e. power, area
and delay are possible by optimized pipelining and routing of data to buffer locations in an effective manner. The
main objective of this paper was to initiate a process to study the feasibility of existing control algorithms for the
improvisation of memory R/W operations within the permissible constraints of the hardware attributes. Extensive
literature survey shows that on the identified research problem could be addressed with pipelining and optimization
of buffer that could verified and tested with the simulation, modeling in FPGA, HDL and/or VERILOG
environment.

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