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List of experiments

Ex.
No
1.

Date

Name of the experiment


Design and Testing of Adder/Subtractor

2.

Design and Testing of BCD Adder

a) Design and testing of 4 to 1 multiplexer.


b) Design and testing of 1 to 4 demultiplexer

4.

Design and Testing of Comparator

5.

Design and Testing of Array Multiplier

6.

Design and Testing of Flip-Flops

7.

Design and Testing of Synchronous


Counters

8.

Design and Testing of Scrambler and


De-scrambler

Page
No

Remarks

INTRODUCTION TO VHDL
VHDL is a hardware description language. It describes the behavior of an
electronic circuit or system from which the physical circuit or system can be
implemented. VHDL stands for VHSIC hardware description language. VHSIC
is itself an abbreviation for Very High Speed Integrated Circuits. VHDL is
intended for circuit synthesis as well as circuit simulation. A fundamental
motivation to use VHDL is that VHDL is standard, technology/vendor
independent language, and is therefore portable and reusable. The two main
immediate applications of VHDL are in the field of programmable logic devices
(including CPLDs Complex Programmable Logic Devices and FPGAs Field
Programmable Gate Arrays) and in the field of ASICs (Application specific
integrated circuit). VHDL in contrary to regular computer programs which are
sequential are inherently concurrent (parallel). In VHDL only statements placed
inside PROCESS, FUNCTION or PROCEDURE are executed sequentially.
Fundamental VHDL units
LIBRARY declaration: contains a list of libraries to be used in the design.
ENTITY: specifies I/O pins of the circuit.
ARCHITECTURE: contains the VHDL code which describes how the
circuit should behave (function).

1.1 Levels of representation and abstraction


3

A digital system can be represented at different levels of abstraction. This keeps the
description and design of complex systems manageable. The Figure showed below
shows different levels of abstraction.

Levels of abstraction: Behavioral, Structural and Physical


The highest level of abstraction is the behavioral level that describes a system in
terms of what it does (or how it behaves) rather than in terms of its components
and interconnection between them. A behavioral description specifies the
relationship between the input and output signals. This could be a Boolean
expression or a more abstract description such as the Register Transfer or
Algorithmic level.
The structural level, on the other hand, describes a system as a collection of gates
and components that are interconnected to perform a desired function. A structural

description could be compared to a schematic of interconnected logic gates. It is a


representation that is usually closer to the physical realization of a system.
VHDL allows one to describe a digital system at the structural or the behavioral
level. The behavioral level can be further divided into two kinds of styles: Data
flow and Algorithmic. The dataflow representation describes how data moves
through the system. This is typically done in terms of data flow between registers
(Register Transfer level). The data flow model makes use of concurrent statements
that are executed in parallel as soon as data arrives at the input. On the other hand,
sequential statements are executed in the sequence that they are specified. VHDL
allows both concurrent and sequential signal assignments that will determine the
manner in which they are executed.
1.2 Basic Structure of a VHDL file
A digital system is usually designed as a hierarchical collection of modules. Each
module has a set of ports which constitute its interface to the outside world. In
VHDL, an entity is such a module which may be used as a component in a design,
or which may be the top level module of the design. Each entity is modeled by
an entity declaration and an architecture body. One can consider the entity
declaration as the interface to the outside world that defines the input and output
signals, while the architecture body contains the description of the entity and is
composed of interconnected entities, processes and components, all operating
concurrently, as schematically shown in Figure below. In a typical design there
will be many such entities connected together to perform the desired function.

A VHDL entity consisting of an interface (entity declaration) and a body


(architectural description).
VHDL uses reserved keywords that cannot be used as signal names or
identifiers. Keywords and user-defined identifiers are case insensitive. Lines with
comments start with two adjacent hyphens (--) and will be ignored by the compiler.
VHDL also ignores line breaks and extra spaces. VHDL is a strongly
typed language which implies that one has always to declare the type of every
object that can have a value, such as signals, constants and variables.
1.2.1. Entity Declaration
The entity declaration defines the NAME of the entity and lists the input and
output ports. The general form is as follows,
entity NAME_OF_ENTITY is [ generic generic declarations);]
port (signal names: mode type;
signal names: mode type;
:
signal names: mode type);
end [NAME_OF_ENTITY] ;
6

An entity always starts with the keyword entity, followed by its name and the
keyword is. Next are the port declarations using the keyword port. An entity
declaration always ends with the keyword end, optionally followed by the name of
the entity.

The NAME_OF_ENTITY is a user-selected identifier


o Signal names consist of a comma separated list of one or more
user-selected identifiers that specify external interface signals.

Mode: is one of the reserved words to indicate the signal direction


o in : indicates that the signal is an input
o out: indicates that the signal is an output of the entity whose
value can only be read by other entities that use it.
o buffer: indicates that the signal is an output of the entity whose
value can be read inside the entitys architecture
o inout: the signal can be an input or an output.

Type: a built-in or user-defined signal type. Examples of types are bit,


bit_vector, Boolean, character, std_logic, and std_ulogic.
o bit : can have the value 0 and 1
o bit_vector : is a vector of bit values (e.g. bit_vector (0 to 7)
o std_logic, std_ulogic, std_logic_vector, std_ulogic_vector: can
have 9 values to indicate the value and strength of a signal.
Std_ulogic and std_logic are preferred over the bit or bit_vector
types.
o boolean : can have the value TRUE and FALSE
o integer: can have a range of integer values
7

o real: can have a range of real values


o character : any printing character
o

time : to indicate time

Generic: generic declarations are optional and determine the local


constants used for timing and sizing (e.g. bus widths) the entity. A
generic can have a default value. The syntax for a generic follows,
generic (
constant_name: type [:=value];
constant_name: type [:=value];
:
constant_name: type [:=value]);

1.2.2. Architecture body


Architecture assigned to an entity describes internal relationship between input
and output ports of the entity. It consists of two parts: declarations and concurrent
statements.
First

(declarative)

part

of

architecture

may

contain

declarations

of types, signals, constants, subprograms (functions and procedures), components,


and groups.
Concurrent statements in the architecture body define the relationship between
inputs and outputs. This relationship can be specified using different types of
statements: concurrent
instantiation, and

signal

concurrent

assignment, process
procedure

call, generate

statement, component
statement, concurrent

assertion statement and block statement. It can be written in different styles:


structural, dataflow, behavioral (functional) or mixed.

The description of a structural body is based on component instantiation and


generate statements. It allows to create hierarchical projects, from simple gates to
very complex components, describing entire subsystems. The connections among
components are realized through ports.
The Dataflow description is built with concurrent signal assignment statements.
Each of the statements can be activated when any of its input signals changes its
value. While these statements describe the behavior of the circuit, a lot of
information about its structure can be extracted form the description as well.
The architecture body describes only the expected functionality (behavior) of the
circuit, without any direct indication as to the hardware implementation. Such
description consists only of one or more processes, each of which contains
sequential statements.
The architecture body may contain statements that define both behavior and
structure of the circuit at the same time. Such architecture description is
called mixed.
The architecture body looks as follows,
architecture architecture_name of NAME_OF_ENTITY is
-- Declarations
-- components declarations
-- signal declarations
-- constant declarations
-- function declarations
-- procedure declarations
-- type declarations
9

:
begin
-- Statements
:
end architecture_name;

1.2.3. Library and Packages


A library can be considered as a place where the compiler stores information about
a design project. A VHDL package is a file or module that contains declarations of
commonly used objects, data type, component declarations, signal, procedures and
functions that can be shared among different VHDL models.
In order to use the std_logic one needs to specify the library and package. This is
done at the beginning of the VHDL file using the library and
the use keywords as follows:
library ieee;
use ieee.std_logic_1164.all;
The .all extension indicates to use the entire ieee.std_logic_1164 package.
The Xilinx Foundation Express comes with several packages in ieee Library:
std_logic_1164 : defines the standard datatypes
std_logic_arith : provides arithmetic, conversion and comparison functions
for the signed, unsigned, integer, std_ulogic, std_logic and std_logic_vector
types
std_logic_unsigned
10

std_logic_misc : defines supplemental types, subtypes, constants and


functions for the std_logic_1164 package.
To use any of these one must include the library and use clause:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
One can add other libraries and packages. The syntax to declare a package is
as follows:
-- Package declaration
package name_of_package is
package declarations
end package name_of_package;
-- Package body declarations
package body name_of_package is
package body declarations
end package body name_of_package;
The STANDARD package is a part of the Language Specification. It defines basic
types, subtypes, and functions, together with operators available for each of the
(sub) types defined. The operators are specified implicitly. Below is a complete list
of declared types, together with their predefined operators.

11

The STANDARD package declares following types


BOOLEAN (with predefined operators "and", "or", "nand", "nor", "xor",
"xnor", "not", "=", "/=", "<", "<=", ">", ">="),
BIT (with predefined operators "and", "or", "nand", "nor", "xor", "xnor",
"not", "=", "/=", "<", "<=", ">", ">="),
CHARACTER (with predefined operators "=", "/=", "<", "<=", ">", ">="),
SEVERITY_LEVEL (with predefined operators "=", "/=", "<", "<=", ">",
">="),
INTEGER (with predefined operators "=", "/=", "<", "<=", ">", ">=", "+",
"-", "abs", "*", "/", "mod", "rem", "**"),
REAL (with predefined operators "=", "/=", "<", "<=", ">", ">=", "+", "-",
"abs", "*", "/", "**"),
TIME (with predefined operators "=", "/=", "<", "<=", ">", ">=", "+", "-",
"abs", "*", "/"),
STRING (with predefined operators "=", "/=", "<", "<=", ">", ">=", "&"),

BIT_VECTOR (with predefined operators "and", "or", "nand", "nor", "xor", "xnor",
"not", "sll", "srl", "sla", "sra", "rol", "ror", "=", "/=", "<", "<=", ">", ">=", "&"),

FILE_OPEN_KIND (with predefined operators "=", "/=", "<", "<=", ">", ">="),

FILE_OPEN_STATUS (with predefined operators "=", "/=", "<", "<=", ">", ">=").

12

Three subtypes in standarad package


DELAY_LENGTH (subtype of TIME),
POSITIVE (subtype of INTEGER),

NATURAL (subtype of INTEGER).

The Std_Logic_1164 Package contains definitions of types, subtypes, and


functions, which extend the VHDL into a multi-value logic. It is not a part of the
VHDL Standard, but it is a separate Standard of the same standardization body
(Institute of Electrical and Electronics Engineers, IEEE).
Main reason for development and standardization of Std_Logic_1164 was the need
for more logical values (than the two defined by the type Bit in the Standard
package) with resolution function. The types Std_Logic and Std_Logic_Vector
(declared in Std_Logic_1164 package) became de facto industrial standards.
The package contains the following declarations:
type std_ulogic: unresolved logic type of 9 values;
type std_ulogic_vector: vector of std_ulogic;
function resolved resolving a std_ulogic_vector into std_ulogic;
subtype std_logic as a resolved version of std_ulogic;
type std_logic_vector: vector of std_logic;
subtypes X01, X01Z, UX01, UX01Z: subtypes of resolved std_ulogic
containing the values listed in the names of subtypes (i.e. UX01 contains
values 'U', 'X', '0', and '1', etc.);
13

logical functions for std_logic, std_ulogic, std_logic_vector and


std_ulogic_vector;
conversion functions between std_ulogic and bit, std_ulogic and bit_vector,
std_logic_vector and bit_vector and vice-versa;
functions rising_edge and falling_edge for edge detection of signals.
x-value detection functions, is x, which detect values 'U', 'X', 'Z', 'W', '-' in the
actual parameter.

An example of an enumerated type that has been defined in the


std_logic_1164 package is the std_ulogic type, defined as follows
type STD_ULOGIC is (
U,
-- uninitialized
X,
-- forcing unknown
0,
-- forcing 0
1,
-- forcing 1
Z,
-- high impedance
W,
-- weak unknown
L,
-- weak 0
H.
-- weak 1
-);
-- dont care
In order to use this type one has to include the clause before each entity
declaration.
library ieee; use ieee.std_logic_1164.all;
1.3. Component Declarations
A component represents an entity/architecture pair. It specifies a subsystem, which
can be instantiated in another architecture leading to a hierarchical specification.
14

Component instantiation is like plugging a hardware component into a socket in a


board. A component must be declared before it is instantiated. The component
declaration defines the virtual interface of the instantiated design entity but it does
not directly indicate the design entity.
-- Component_declaration
component component_name
port (port_list);
end component component_name;

A component defined in architecture may be instantiated


using the syntax
--component_instantiation_statement
label: component_name

port map (port1=>signal1,

port2=> signal2, port3=>signaln);


This indicates that the architecture contains an instance of the named component,
with actual values specified for connected to actual signals or entity ports.

1.4. Data Objects: Signals, Variables and Constants


A

data

object

is

created

by

an object

declaration and

has

a value and type associated with it. An object can be a Constant, Variable, Signal
or a File. Signals can be considered wires in a schematic that can have a current
value and future values, and that are a function of the signal assignment
statements. On the other hand, Variables and Constants are used to model the
15

behavior of a circuit and are used in processes, procedures and functions, similarly
as they would be in a programming language.
Signals can be explicitly declared in the declarative part of:
package declaration; signals declared in a package are visible in all design
entities using the package (through the use clause);
architecture (see architecture); such signals are visible inside the architecture
only;
block ; the scope of such signals is limited to the block itself;
Subprogram (function and procedure); such signals are visible in respective
subprogram.
Moreover, a port declaration in an entity is an implicit signal declaration. A signal
declared this way is visible in all architectures assigned to that entity. The syntax
for signal declaration is
signal list_of_signal_names: type [ := initial value] ;
Signals are updated when their signal assignment statement is executed, as
illustrated below,
SUM <= (A xor B) ;
A variable can have a single value and can be updated using a variable
assignment statement. The variable is updated without any delay as soon as the
statement is executed. Variables must be declared inside a process (and are local to
the process). The variable declaration is as follows:

16

variable list_of_variable_names: type [ := initial value] ;


A constant can have a single value of a given type and cannot be changed during
the simulation. A constant is declared as follows,
constant list_of_name_of_constant: type [ := initial value] ;
where the initial value is optional. Constants can be declared at the start of an
architecture and can then be used anywhere within the architecture. Constants
declared within a process can only be used inside that specific process.

17

Introduction to Programmable Logic Devices


Programmable devices are a class of general-purpose chips that can be configured
for a wide variety of applications. The first programmable device which achieved a
wide spread was the PROM (Programmable-Read-Only Memory). PROMs, onetime programmable device come in two basic versions.
1) The mask-programmable chip programmed only by the manufacturer.
2) The field-programmable chip programmed by the end user.
The field-programmable PROM developed into two types, the Erasable
Programmable Read-Only Memory (EPROM) and the Electrically Erasable
Programmable Read-Only Memory (EEPROM).
Another development in this field is the programmable logic devices (PLD).
These devices were constructed to implement logic circuits. The PLDs consists
of an array of AND gates connected to an array of OR gates. The PAL
(programmable array logic) and PLA (programmable logic array) are commonly
used PLDs. PAL consists of a programmable AND plane followed by fixed ORplane, where in PLAs both AND and OR plane are programmable.
FPGA:
The field-Programmable Gate Arrays (FPGAs) provide the benefits of custom
CMOS VLSI, while avoiding the initial cost, time delay and inherent risk of a
conventional masked gate array. The FPGAs are customized by loading
configuration data into the internal memory cells.
The FPGA has three major configurable elements: configurable logic blocks
(CLBs), Input/Output blocks (IOBs) and interconnects. The CLBs provide the
functional elements for constructing users logic. The IOBs provide the
18

FPGA Architecture

CPLD Architecture

19

interface between package pins and internal signal lines. The programmable
interconnect resources provide routing paths to connect the inputs and outputs
of the CLBs and IOBs on to the appropriate networks.
CPLD:
Complex Programmable Logic Devices that consists of an arrangement of multiple
simple PLD like blocks with general purpose interconnect among the blocks. The
CPLD has three major configurable blocks: functional blocks (FB), input/output
blocks and interconnects. The devices are programmed using programmable
elements depending on the technology of the manufacturer, which can be EPROM
cells, EEPROM cells or flash EPROM cells

20

21

Date:

1. Design and Testing of Adder/Subtractor

Aim
To design a Four-bit Adder/Subtractor using VHDL.

Requirements
1. Simulation and synthesis tool: Xilinx ISE.
2. FPGA/CPLD Trainer kit.

Theory
An Adder/Subtractor is a combinational circuit that is capable of adding or
subtracting binary numbers. The choice of addition or subtraction operation is
based on the value of control input M. When the control input, M=0 the circuit
performs addition operation and if M=1, the circuit performs subtraction operation.
The design is based on the fact that subtraction operation can be realized using an
adder by complementing (2s complement) subtrahend and adding with minuend.
A four-bit adder/subtractor circuit can be realized from four full-adders and four XOR gates, where carry-out of each full-adder is connected to carry-in of next
higher order full-adder. This type of adder is called ripple carry adder.

22

FOUR-BIT ADDER/SUBTRACTOR

23

VHDL Code for adder/subtractor

24

25

Observation

Synthesis Report
Selected device:
Logic Utilization

Used

Available

% Utilization

Result
Thus the four-bit adder/subtractor is designed using VHDL and its
functionality has been verified.

26

27

Date:

2. Design and Testing of BCD Adder

Aim
To design a Four-bit BCD Adder using VHDL.

Requirements
1. Simulation and synthesis tool: Xilinx ISE.
2. FPGA/CPLD Trainer kit.

Theory
A BCD (Binary Coded Decimal) adder consists of two binary 4-bit parallel
adders and a few combinational gates. The first 4-bit adder sums the two BCD
inputs, resulting in a binary representation of this sum. The second 4-bit adder and
combinational logic converts the output of the first 4-bit adder from binary to
BCD. The highest possible value that can result from summing two BCD numbers
and a carry bit is 19 (1001 + 1001 + 1 = 1910). Table 2.1 lists the possible binary
outputs from the first 4-bit adder, along with the desired BCD correction.
If the sum is between 0 and 9, then no correction is needed, i.e nothing is added
to binary sum.
If the sum is between 10 and 19, then the carry bit becomes a 1 and binary value
0110 is added to binary sum through the bottom 4-bit binary adder.

Possible sum outputs of BCD addition of two four bit numbers


28

BINARY SUM

BCD SUM

DECIMAL

S4

S3

S2

S1

S0

Z4

Z3

Z2

Z1

Z0

10

11

12

13

14

15

16

17

18

19

The

output

carry

can

be

expressed
29

in

Boolean

function

cout = s4 + s3s2 + s3s1

30

Four bit BCD adder

31

VHDL Code for BCD adder

32

33

Observation

Synthesis Report
Selected device:
Logic Utilization

Used

Available

% Utilization

Result
Thus the four-bit BCD adder is designed using VHDL and its
functionality has been verified.

34

35

Date:

3a. Design and Testing of Multiplexer

Aim
To design a 4 to 1 multiplexer using VHDL.

Requirements
1. Simulation and synthesis tool: Xilinx ISE.
2. FPGA/CPLD Trainer kit.

Theory
A Digital multiplexer is a combinational circuit that selects binary
information from one of many input lines and directs it to a single output line.
Multiplexing in the sense is transmitting a large number of information units over a
smaller number of channels or lines. The selection of a particular input line is
controlled by a set of selection lines. Normally there are 2n input lines and n
selection lines whose bit combinations determine which input is to be selected.
Multiplexer circuits may have an enable input to control the operation of the unit.
The enable input (sometimes called strobe) can be used to expand two or more
multiplexers to digital multiplexers with larger number of inputs. The size of the
multiplexer is specified by the number of input lines and the single output line. The
Boolean functions for the output of 4 to 1 multiplexer is
Y = ( S1.S0.I) + (S1.S0.I1) + (S1.S0.I2) + (S1.S0.I3).

36

4 TO 1 MULTIPLEXER
Block Diagram

Truth Table
Control Inputs
Select lines
S1

Output

Enable

S0

I0

I1

I2

I3

VHDL Code for 4 to 1 Multiplexer


37

38

LOGIC DIAGRAM FOR 4 TO 1 MULTIPLEXER

39

40

41

Synthesis Report

Selected device:
Logic Utilization

Used

Available

% Utilization

Result
Thus the 4 to 1 multiplexer is designed using VHDL and its functionality
has been verified.

42

43

Date:

3b. Design and Testing of De-Multiplexer

Aim
To design a 1 to 4 De-multiplexer using VHDL.

Requirements
1. Simulation and synthesis tool: Xilinx ISE.
2. FPGA/CPLD Trainer kit.

Theory
The De-multiplexer performs the reverse operation of a multiplexer. It is a
combinational circuit which accepts a single input and distributes it overall several
outputs. The selection of a particular output line is controlled by a set of selection
lines. Normally, there are 2n output lines and n selection lines. De-multiplexer
circuit may have an enable input to control the operation of the unit. The circuit
functions as normal de-multiplexer only if the enable or strobe input line is
activated. The size of the de-multiplexer is specified by the single input line and
the number 2n of its output lines. The Boolean functions for the outputs of 1 to 4
De-multiplexer are
D0 = S1.S0.I; D1 = S1.S0.I; D2 = S1.S0.I;

44

D3 = S1.S0.I.

1 to 4 De-multiplexer
Block Diagram

Truth Table
Control inputs
Select lines

Outputs
Enable

S1

S0

D0

D1

D2

D3

45

VHDL Code for 1 to 4 De-multiplexer

46

LOGIC DIAGRAM FOR 1 TO 4 DE-MULTIPLEXER

47

Synthesis Report
Selected device:
Logic Utilization

Used

Available

% Utilization

Result
Thus the 1 to 4 de-multiplexer is designed using VHDL and its
functionality has been verified.

48

49

Date:

4. Design and Testing of Comparator


Aim
To design a four-bit comparator using VHDL.

Requirements
1. Simulation and synthesis tool: Xilinx ISE.
2. FPGA/CPLD Trainer kit.

Theory
A Four-bit comparator compares two four-bit binary words, A and B, and
asserts outputs indicating whether the decimal equivalent of word A is less than,
greater than, or equal to that of word B. A four-bit comparator can be implemented
from two two-bit comparators with additional logic to generate the appropriate
outputs that result from comparing four-bit binary words. The logic for connecting
the two-bit comparators is based on the observation that a strict inequality in the
higher order bit pairs determines relative magnitude of the four-bit words; on the
otherhand, if the high order bit pairs are equal, the lowerorder bit pairs determine
the output. The simplified Boolean equations for the three outputs of two-bit
comparator are

(X > Y)

X.gt. Y = (X0 Y1 Y0) + (X1 Y1) + (X1 X0 Y0)

(X =Y)

X .eq.Y = (X0

(X < Y)

X .lt.Y = (X1 X0 Y0) + (X0 Y1 Y0) + (X1 Y1)

Y0) (X1

Y1)

50

Truth Table for 2-bit comparator

INPUTS

OUTPUTS

X1

X0

Y1

Y0

X.gt.Y

X.eq.Y

X.lt.Y

51

52

Logic Diagram for 2-bit comparator

53

VHDL Code for Four-bit Comparator

54

Hierarchical Structure of four-bit Comparator

55

Observation

Synthesis Report
Selected device:
Logic Utilization

Used

Available

% Utilization

Result
Thus the logic circuit for four-bit comparator is designed using VHDL and
its functionality has been verified.

56

57

Date:

5. Design and Testing of Array Multiplier


Aim
To design a four-bit array multiplier using VHDL.

Requirements
1. Simulation and synthesis tool: Xilinx ISE.
2. FPGA/CPLD Trainer kit.

Theory
An Array Multiplier accepts the multiplier (A) and multiplicand (B)
inputs and uses an array of cells to calculate the bit products aj.bk individually in
parallel fashion.
a3 a2 a1 a0 x

b3 b2 b1 b0

a3 b0 a2 b0 a1b0 a0b0
a3b1 a2b1 a1b1 a0b1
a3b2 a2b2 a1b2 a0b2
a3b3 a2b3 a1b3 a0b3
O7

O6

O5

O4

O3

58

O2

O1

O0

Partial Products

59

Each row, called partial product, is formed by bit-by-bit multiplication of each


operand. For example a partial product is formed when each bit of operand a is
multiplied by b0 resulting in a3 b0, a2 b0, a1b0 and a0b0. Each product bit Ox is formed
by adding partial product columns. The product equations including the carry-in,
Cx from column (x-1), are
O0 = a0b0
O1 = a1b0 + a0b1 + C0
O2 = a2b0 + a1b1 + a0b2 + C1
O3 = a3 b0 + a2b1 + a1b2 + a0b3 + C2
O4 = a3b1 + a2b2 + a1b3 + C3
O5 = a3b2 + a2b3 + C4
O6 = a3b3 + C5
O7 =

C6

Each product term Px is formed by AND gates. By adding appropriate product term
outputs the multiplier equations are realized. The adders are arranged in a carrysave chain where, the carry-out bits are fed to the next available adder in the
column to the left.

60

Four-bit Array Multiplier

FA Full Adder
HA Half Adder

61

VHDL Code for Four-bit Array Multiplier

62

63

Observation

Synthesis Report
Selected device:
Logic Utilization

Used

Available

% Utilization

Result
Thus the logic circuit for four-bit array multiplier is designed in VHDL and
its functionality has been verified.

64

65

66

Date:

6. Design and Testing of Flip-flops


Aim
To design S-R, J-K, D and T Flip-flops using VHDL.

Requirements
1. Simulation and synthesis tool: Xilinx ISE.
2. FPGA/CPLD Trainer kit.

Theory
The Flip-flop is an electronic circuit (bi-stable multivibrator) that has two
stable states and therefore they are commonly used memory devices in sequential
circuits. The flip-flop can be realized using NAND or NOR gates. The flip-flop is
usually controlled by one or two control signals and/or gate or clock signal. The
output often includes the complement as well as the normal output. The names flipflops and latches are sometimes used interchangeably; however, the term flip-flop
is more appropriately associated with devices that change state only on a clock
edge or pulse whereas latches change state without being clocked. Four types of
flip-flops are commonly considered: SR, JK, D and T.

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S-R FLIP-FLOP
Truth table

INPUTS
CL
K

OUTPUTS
R

Qt

Qt+1

STATE

NO CHANGE

NO CHANGE

RESET

RESET

SET

SET

INDETERMINAT
E

INDETERMINAT
E

NO CHANGE

^
^
^

0
0

NO CHANGE

Logic Diagram

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i)

S-R flip-flop
An S-R flip-flop is similar to an S-R latch in that S=1 sets the Q output to
1, and R=1 resets Q output to 0. The essential difference is that the flipflop has clock input and the Q output can change only after an active
clock edge. When both S and R inputs are 0 the state of the flip-flop
output Q does not change. When both S and R inputs are high, state of
the flip-flop output Q is indeterminate. The characteristic equation for SR flip-flop is Qt+1 = S+RQt .

ii)

J-K flip-flop
The J-K flip-flop does not have an indeterminate input combination as in
the S-R flip-flop. The J and K inputs are analogous to the S (set) and R
(reset) inputs respectively of S-R flip-flop. The indeterminate input
condition of the R-S latch causes the J-k flip-flop to toggle; when J=K=1
then . This toggling phenomenon is accomplished by connecting Q and
Q outputs back to J and K excitation inputs. The characteristic equation
for J-K flip-flop is

Qt+1 =JQt+KQt

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J-K FLIP-FLOP
Truth Table
PREVIOU
S STATE

INPUTS

OUTPUTS

Qt

Qt+1

Logic Diagram

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iii)

D flip-flop
The data or D fip-flophas two inputs D and clock. The output changes
only in response to the clock edge. The state of the flip-flop after the
active clock edge (Qt +i) is equal to the input (D) before the active edge.
The characteristic equation of the D flip-flop is Qt+1 = D.

iv)

T flip-flop
In the T flip-flop also called the toggle flip-flop, when T = 1 the flip-flop
changes the state after the active edge of clock. When T = 0 no change of
state occurs. The characteristic equation for T flip-flop is Qt+1 = T

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Qt

D FLIP-FLOP
Truth table

INPUT

OUTPUT

STATE

CLK

Qt

Qt+1

RESET

SET

Qt

NO
CHANGE

Logic Diagram

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VHDL Code for Flip-flops

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T FLIP-FLOP
Truth table

PREVIOUS

INPUT

OUTPUT

Qt

Qt+1

STATE

Logic Diagram

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Synthesis Report
Selected device:
S-R FLIP-FLOP
Logic Utilization

Used

Available

% Utilization

Used

Available

% Utilization

J-K FLIP-FLOP
Logic Utilization

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D FLIP-FLOP
Logic Utilization

Used

Available

% Utilization

Used

Available

% Utilization

T FLIP-FLOP
Logic Utilization

Result
Thus the logic circuits for S-R, J-K, D and T flip-flops are designed using
VHDL and their functionalities have been verified.

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Date:

7. Design and testing of Synchronous Counters


Aim
To design a three-bit synchronous up and down counters using VHDL.

Requirements
1. Simulation and synthesis tool: Xilinx ISE.
2. FPGA/CPLD Trainer kit.

Theory
In Synchronous counters, all the flip-flops are triggered by same
clock pulse thus all the flip-flops change their states simultaneously. Synchronous
counters have regular pattern and can be easily constructed with complementing
flip-flops (J-K with J and K tied or T type) and logic gates. Synchronous binary
counter can be classified into two types: up-counter, which increments its output
by one for every clock transition and down-counter, which decrements its output
by one for every clock transition. In up-counters, the flip-flop in the LSB position
is complemented for every clock whereas other flip-flops are complemented only
when all their lower order bits are equal to 1. Similarly, for down-counters the flipflop in the LSB position is complemented for every clock whereas other flip-flops
are complemented only when all their lower order bits are equal to 0.

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Excitation table for three-bit synchronous up-counter

Present State

Next State

Flip-flop inputs

Q2

Q1

Q0

Q2

Q1

Q0

T2

T1

T0

Flip-flop input equations


(J-K)2 = T2 = Q1 . Q0
(J-K)1 = T1 = Q0
(J-K)0 = T0 =1

VHDL Code for three-bit synchronous up-counter


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Three-bit synchronous up-counter

Waveform

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Excitation table for three-bit synchronous down-counter

Present State

Next State

Flip-flop inputs

Q2

Q1

Q0

Q2

Q1

Q0

T2

T1

T0

Flip-flop input equations


(J-K)2 = T2 = Q1 . Q0
(J-K)1 = T1 = Q0
(J-K)0 = T0 =1

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VHDL Code for three-bit synchronous down-counter

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Three-bit synchronous down-counter

Waveform

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Synthesis Report
Selected device:
Up Counter
Logic Utilization

Used

Available

% Utilization

Used

Available

% Utilization

Down Counter
Logic Utilization

Result
Thus the three-bit synchronous up and down binary counters are designed
using VHDL and their functionalities have been verified.
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Date:

8. Design and testing of Scrambler and De-Scrambler


Aim
To design Scrambler and de-scrambler circuit using VHDL.

Requirements
1. Simulation and synthesis tool: Xilinx ISE.
2. FPGA/CPLD Trainer kit.

Theory
Scramblers are circuits that pseudo-randomly change the values of some
bits in a data block with the purpose of whitening (that is spread it so that no strong
spectral component will exist, thus reducing electromagnetic interference) or to
introduce security. In addition to its use as a stream cipher, a scrambler is
commonly used to avoid long strings of 0s and 1s which are responsible for DC
wander and synchronization problems in communication circuits. Scramblers can
be implemented using a linear feedback shift register (LFSR). An LFSR is a simple
register composed of memory elements (flip-flops) and modulo-2 adders (XOR
gates). Feedback is taken from two or more memory elements, which are XOR ed
and feedback to the first stage of the LFSR.
There are two types of scramblers, additive scramblers and multiplicative
scramblers. Additive scramblers are also called synchronous (because they require

91

Scrambler

DATA OUT

D
F/F
1

D
F/F
2

D
F/F
3

D
F/F
4

D
F/F
5

D
F/F
6

D
F/F
7

D
F/F
2

D
F/F
3

D
F/F
4

D
F/F
5

D
F/F
6

D
F/F
7

DATA IN

De-scrambler

DATA IN
D
F/F
1

DATA OUT
MODULO 2 ADDER(XOR GATE)

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the initial state of both scrambler and descrambler to be same) or non-recursive


(because they do not have feedback loops) transform the input data stream by
applying pseudo-random binary sequence. For synchronous operation transmitting
and receiver LFSR, sync-word must be used. Multiplicative scramblers are also
called asynchronous (because they do not need LFSR synchronization) or recursive
(they have feedback loops) the input signal by scramblers transfer function. They
are discrete time-invariant systems. Multiplicative scramblers/descramblers are
self- synchronizing, that they do not need to start from the same initial state

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VHDL code for scrambler and De-scrambler

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Synthesis Report
SCRAMBLER

Selected device:
Logic Utilization

Used

Available

% Utilization

Used

Available

% Utilization

DE SCRAMBLER

Selected device:

Logic Utilization

Result
Thus the logic circuit for Scrambler and De-scrambler is designed using
VHDL and its functionality has been verified.
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