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Remarks
INTRODUCTION TO VHDL
VHDL is a hardware description language. It describes the behavior of an
electronic circuit or system from which the physical circuit or system can be
implemented. VHDL stands for VHSIC hardware description language. VHSIC
is itself an abbreviation for Very High Speed Integrated Circuits. VHDL is
intended for circuit synthesis as well as circuit simulation. A fundamental
motivation to use VHDL is that VHDL is standard, technology/vendor
independent language, and is therefore portable and reusable. The two main
immediate applications of VHDL are in the field of programmable logic devices
(including CPLDs Complex Programmable Logic Devices and FPGAs Field
Programmable Gate Arrays) and in the field of ASICs (Application specific
integrated circuit). VHDL in contrary to regular computer programs which are
sequential are inherently concurrent (parallel). In VHDL only statements placed
inside PROCESS, FUNCTION or PROCEDURE are executed sequentially.
Fundamental VHDL units
LIBRARY declaration: contains a list of libraries to be used in the design.
ENTITY: specifies I/O pins of the circuit.
ARCHITECTURE: contains the VHDL code which describes how the
circuit should behave (function).
A digital system can be represented at different levels of abstraction. This keeps the
description and design of complex systems manageable. The Figure showed below
shows different levels of abstraction.
An entity always starts with the keyword entity, followed by its name and the
keyword is. Next are the port declarations using the keyword port. An entity
declaration always ends with the keyword end, optionally followed by the name of
the entity.
(declarative)
part
of
architecture
may
contain
declarations
signal
concurrent
assignment, process
procedure
call, generate
statement, component
statement, concurrent
:
begin
-- Statements
:
end architecture_name;
11
BIT_VECTOR (with predefined operators "and", "or", "nand", "nor", "xor", "xnor",
"not", "sll", "srl", "sla", "sra", "rol", "ror", "=", "/=", "<", "<=", ">", ">=", "&"),
FILE_OPEN_KIND (with predefined operators "=", "/=", "<", "<=", ">", ">="),
FILE_OPEN_STATUS (with predefined operators "=", "/=", "<", "<=", ">", ">=").
12
data
object
is
created
by
an object
declaration and
has
a value and type associated with it. An object can be a Constant, Variable, Signal
or a File. Signals can be considered wires in a schematic that can have a current
value and future values, and that are a function of the signal assignment
statements. On the other hand, Variables and Constants are used to model the
15
behavior of a circuit and are used in processes, procedures and functions, similarly
as they would be in a programming language.
Signals can be explicitly declared in the declarative part of:
package declaration; signals declared in a package are visible in all design
entities using the package (through the use clause);
architecture (see architecture); such signals are visible inside the architecture
only;
block ; the scope of such signals is limited to the block itself;
Subprogram (function and procedure); such signals are visible in respective
subprogram.
Moreover, a port declaration in an entity is an implicit signal declaration. A signal
declared this way is visible in all architectures assigned to that entity. The syntax
for signal declaration is
signal list_of_signal_names: type [ := initial value] ;
Signals are updated when their signal assignment statement is executed, as
illustrated below,
SUM <= (A xor B) ;
A variable can have a single value and can be updated using a variable
assignment statement. The variable is updated without any delay as soon as the
statement is executed. Variables must be declared inside a process (and are local to
the process). The variable declaration is as follows:
16
17
FPGA Architecture
CPLD Architecture
19
interface between package pins and internal signal lines. The programmable
interconnect resources provide routing paths to connect the inputs and outputs
of the CLBs and IOBs on to the appropriate networks.
CPLD:
Complex Programmable Logic Devices that consists of an arrangement of multiple
simple PLD like blocks with general purpose interconnect among the blocks. The
CPLD has three major configurable blocks: functional blocks (FB), input/output
blocks and interconnects. The devices are programmed using programmable
elements depending on the technology of the manufacturer, which can be EPROM
cells, EEPROM cells or flash EPROM cells
20
21
Date:
Aim
To design a Four-bit Adder/Subtractor using VHDL.
Requirements
1. Simulation and synthesis tool: Xilinx ISE.
2. FPGA/CPLD Trainer kit.
Theory
An Adder/Subtractor is a combinational circuit that is capable of adding or
subtracting binary numbers. The choice of addition or subtraction operation is
based on the value of control input M. When the control input, M=0 the circuit
performs addition operation and if M=1, the circuit performs subtraction operation.
The design is based on the fact that subtraction operation can be realized using an
adder by complementing (2s complement) subtrahend and adding with minuend.
A four-bit adder/subtractor circuit can be realized from four full-adders and four XOR gates, where carry-out of each full-adder is connected to carry-in of next
higher order full-adder. This type of adder is called ripple carry adder.
22
FOUR-BIT ADDER/SUBTRACTOR
23
24
25
Observation
Synthesis Report
Selected device:
Logic Utilization
Used
Available
% Utilization
Result
Thus the four-bit adder/subtractor is designed using VHDL and its
functionality has been verified.
26
27
Date:
Aim
To design a Four-bit BCD Adder using VHDL.
Requirements
1. Simulation and synthesis tool: Xilinx ISE.
2. FPGA/CPLD Trainer kit.
Theory
A BCD (Binary Coded Decimal) adder consists of two binary 4-bit parallel
adders and a few combinational gates. The first 4-bit adder sums the two BCD
inputs, resulting in a binary representation of this sum. The second 4-bit adder and
combinational logic converts the output of the first 4-bit adder from binary to
BCD. The highest possible value that can result from summing two BCD numbers
and a carry bit is 19 (1001 + 1001 + 1 = 1910). Table 2.1 lists the possible binary
outputs from the first 4-bit adder, along with the desired BCD correction.
If the sum is between 0 and 9, then no correction is needed, i.e nothing is added
to binary sum.
If the sum is between 10 and 19, then the carry bit becomes a 1 and binary value
0110 is added to binary sum through the bottom 4-bit binary adder.
BINARY SUM
BCD SUM
DECIMAL
S4
S3
S2
S1
S0
Z4
Z3
Z2
Z1
Z0
10
11
12
13
14
15
16
17
18
19
The
output
carry
can
be
expressed
29
in
Boolean
function
30
31
32
33
Observation
Synthesis Report
Selected device:
Logic Utilization
Used
Available
% Utilization
Result
Thus the four-bit BCD adder is designed using VHDL and its
functionality has been verified.
34
35
Date:
Aim
To design a 4 to 1 multiplexer using VHDL.
Requirements
1. Simulation and synthesis tool: Xilinx ISE.
2. FPGA/CPLD Trainer kit.
Theory
A Digital multiplexer is a combinational circuit that selects binary
information from one of many input lines and directs it to a single output line.
Multiplexing in the sense is transmitting a large number of information units over a
smaller number of channels or lines. The selection of a particular input line is
controlled by a set of selection lines. Normally there are 2n input lines and n
selection lines whose bit combinations determine which input is to be selected.
Multiplexer circuits may have an enable input to control the operation of the unit.
The enable input (sometimes called strobe) can be used to expand two or more
multiplexers to digital multiplexers with larger number of inputs. The size of the
multiplexer is specified by the number of input lines and the single output line. The
Boolean functions for the output of 4 to 1 multiplexer is
Y = ( S1.S0.I) + (S1.S0.I1) + (S1.S0.I2) + (S1.S0.I3).
36
4 TO 1 MULTIPLEXER
Block Diagram
Truth Table
Control Inputs
Select lines
S1
Output
Enable
S0
I0
I1
I2
I3
38
39
40
41
Synthesis Report
Selected device:
Logic Utilization
Used
Available
% Utilization
Result
Thus the 4 to 1 multiplexer is designed using VHDL and its functionality
has been verified.
42
43
Date:
Aim
To design a 1 to 4 De-multiplexer using VHDL.
Requirements
1. Simulation and synthesis tool: Xilinx ISE.
2. FPGA/CPLD Trainer kit.
Theory
The De-multiplexer performs the reverse operation of a multiplexer. It is a
combinational circuit which accepts a single input and distributes it overall several
outputs. The selection of a particular output line is controlled by a set of selection
lines. Normally, there are 2n output lines and n selection lines. De-multiplexer
circuit may have an enable input to control the operation of the unit. The circuit
functions as normal de-multiplexer only if the enable or strobe input line is
activated. The size of the de-multiplexer is specified by the single input line and
the number 2n of its output lines. The Boolean functions for the outputs of 1 to 4
De-multiplexer are
D0 = S1.S0.I; D1 = S1.S0.I; D2 = S1.S0.I;
44
D3 = S1.S0.I.
1 to 4 De-multiplexer
Block Diagram
Truth Table
Control inputs
Select lines
Outputs
Enable
S1
S0
D0
D1
D2
D3
45
46
47
Synthesis Report
Selected device:
Logic Utilization
Used
Available
% Utilization
Result
Thus the 1 to 4 de-multiplexer is designed using VHDL and its
functionality has been verified.
48
49
Date:
Requirements
1. Simulation and synthesis tool: Xilinx ISE.
2. FPGA/CPLD Trainer kit.
Theory
A Four-bit comparator compares two four-bit binary words, A and B, and
asserts outputs indicating whether the decimal equivalent of word A is less than,
greater than, or equal to that of word B. A four-bit comparator can be implemented
from two two-bit comparators with additional logic to generate the appropriate
outputs that result from comparing four-bit binary words. The logic for connecting
the two-bit comparators is based on the observation that a strict inequality in the
higher order bit pairs determines relative magnitude of the four-bit words; on the
otherhand, if the high order bit pairs are equal, the lowerorder bit pairs determine
the output. The simplified Boolean equations for the three outputs of two-bit
comparator are
(X > Y)
(X =Y)
X .eq.Y = (X0
(X < Y)
Y0) (X1
Y1)
50
INPUTS
OUTPUTS
X1
X0
Y1
Y0
X.gt.Y
X.eq.Y
X.lt.Y
51
52
53
54
55
Observation
Synthesis Report
Selected device:
Logic Utilization
Used
Available
% Utilization
Result
Thus the logic circuit for four-bit comparator is designed using VHDL and
its functionality has been verified.
56
57
Date:
Requirements
1. Simulation and synthesis tool: Xilinx ISE.
2. FPGA/CPLD Trainer kit.
Theory
An Array Multiplier accepts the multiplier (A) and multiplicand (B)
inputs and uses an array of cells to calculate the bit products aj.bk individually in
parallel fashion.
a3 a2 a1 a0 x
b3 b2 b1 b0
a3 b0 a2 b0 a1b0 a0b0
a3b1 a2b1 a1b1 a0b1
a3b2 a2b2 a1b2 a0b2
a3b3 a2b3 a1b3 a0b3
O7
O6
O5
O4
O3
58
O2
O1
O0
Partial Products
59
C6
Each product term Px is formed by AND gates. By adding appropriate product term
outputs the multiplier equations are realized. The adders are arranged in a carrysave chain where, the carry-out bits are fed to the next available adder in the
column to the left.
60
FA Full Adder
HA Half Adder
61
62
63
Observation
Synthesis Report
Selected device:
Logic Utilization
Used
Available
% Utilization
Result
Thus the logic circuit for four-bit array multiplier is designed in VHDL and
its functionality has been verified.
64
65
66
Date:
Requirements
1. Simulation and synthesis tool: Xilinx ISE.
2. FPGA/CPLD Trainer kit.
Theory
The Flip-flop is an electronic circuit (bi-stable multivibrator) that has two
stable states and therefore they are commonly used memory devices in sequential
circuits. The flip-flop can be realized using NAND or NOR gates. The flip-flop is
usually controlled by one or two control signals and/or gate or clock signal. The
output often includes the complement as well as the normal output. The names flipflops and latches are sometimes used interchangeably; however, the term flip-flop
is more appropriately associated with devices that change state only on a clock
edge or pulse whereas latches change state without being clocked. Four types of
flip-flops are commonly considered: SR, JK, D and T.
67
S-R FLIP-FLOP
Truth table
INPUTS
CL
K
OUTPUTS
R
Qt
Qt+1
STATE
NO CHANGE
NO CHANGE
RESET
RESET
SET
SET
INDETERMINAT
E
INDETERMINAT
E
NO CHANGE
^
^
^
0
0
NO CHANGE
Logic Diagram
68
69
i)
S-R flip-flop
An S-R flip-flop is similar to an S-R latch in that S=1 sets the Q output to
1, and R=1 resets Q output to 0. The essential difference is that the flipflop has clock input and the Q output can change only after an active
clock edge. When both S and R inputs are 0 the state of the flip-flop
output Q does not change. When both S and R inputs are high, state of
the flip-flop output Q is indeterminate. The characteristic equation for SR flip-flop is Qt+1 = S+RQt .
ii)
J-K flip-flop
The J-K flip-flop does not have an indeterminate input combination as in
the S-R flip-flop. The J and K inputs are analogous to the S (set) and R
(reset) inputs respectively of S-R flip-flop. The indeterminate input
condition of the R-S latch causes the J-k flip-flop to toggle; when J=K=1
then . This toggling phenomenon is accomplished by connecting Q and
Q outputs back to J and K excitation inputs. The characteristic equation
for J-K flip-flop is
Qt+1 =JQt+KQt
70
J-K FLIP-FLOP
Truth Table
PREVIOU
S STATE
INPUTS
OUTPUTS
Qt
Qt+1
Logic Diagram
71
iii)
D flip-flop
The data or D fip-flophas two inputs D and clock. The output changes
only in response to the clock edge. The state of the flip-flop after the
active clock edge (Qt +i) is equal to the input (D) before the active edge.
The characteristic equation of the D flip-flop is Qt+1 = D.
iv)
T flip-flop
In the T flip-flop also called the toggle flip-flop, when T = 1 the flip-flop
changes the state after the active edge of clock. When T = 0 no change of
state occurs. The characteristic equation for T flip-flop is Qt+1 = T
72
Qt
D FLIP-FLOP
Truth table
INPUT
OUTPUT
STATE
CLK
Qt
Qt+1
RESET
SET
Qt
NO
CHANGE
Logic Diagram
73
74
T FLIP-FLOP
Truth table
PREVIOUS
INPUT
OUTPUT
Qt
Qt+1
STATE
Logic Diagram
75
76
Synthesis Report
Selected device:
S-R FLIP-FLOP
Logic Utilization
Used
Available
% Utilization
Used
Available
% Utilization
J-K FLIP-FLOP
Logic Utilization
77
78
D FLIP-FLOP
Logic Utilization
Used
Available
% Utilization
Used
Available
% Utilization
T FLIP-FLOP
Logic Utilization
Result
Thus the logic circuits for S-R, J-K, D and T flip-flops are designed using
VHDL and their functionalities have been verified.
79
80
Date:
Requirements
1. Simulation and synthesis tool: Xilinx ISE.
2. FPGA/CPLD Trainer kit.
Theory
In Synchronous counters, all the flip-flops are triggered by same
clock pulse thus all the flip-flops change their states simultaneously. Synchronous
counters have regular pattern and can be easily constructed with complementing
flip-flops (J-K with J and K tied or T type) and logic gates. Synchronous binary
counter can be classified into two types: up-counter, which increments its output
by one for every clock transition and down-counter, which decrements its output
by one for every clock transition. In up-counters, the flip-flop in the LSB position
is complemented for every clock whereas other flip-flops are complemented only
when all their lower order bits are equal to 1. Similarly, for down-counters the flipflop in the LSB position is complemented for every clock whereas other flip-flops
are complemented only when all their lower order bits are equal to 0.
81
Present State
Next State
Flip-flop inputs
Q2
Q1
Q0
Q2
Q1
Q0
T2
T1
T0
83
Waveform
84
85
Present State
Next State
Flip-flop inputs
Q2
Q1
Q0
Q2
Q1
Q0
T2
T1
T0
86
87
Waveform
88
Synthesis Report
Selected device:
Up Counter
Logic Utilization
Used
Available
% Utilization
Used
Available
% Utilization
Down Counter
Logic Utilization
Result
Thus the three-bit synchronous up and down binary counters are designed
using VHDL and their functionalities have been verified.
89
90
Date:
Requirements
1. Simulation and synthesis tool: Xilinx ISE.
2. FPGA/CPLD Trainer kit.
Theory
Scramblers are circuits that pseudo-randomly change the values of some
bits in a data block with the purpose of whitening (that is spread it so that no strong
spectral component will exist, thus reducing electromagnetic interference) or to
introduce security. In addition to its use as a stream cipher, a scrambler is
commonly used to avoid long strings of 0s and 1s which are responsible for DC
wander and synchronization problems in communication circuits. Scramblers can
be implemented using a linear feedback shift register (LFSR). An LFSR is a simple
register composed of memory elements (flip-flops) and modulo-2 adders (XOR
gates). Feedback is taken from two or more memory elements, which are XOR ed
and feedback to the first stage of the LFSR.
There are two types of scramblers, additive scramblers and multiplicative
scramblers. Additive scramblers are also called synchronous (because they require
91
Scrambler
DATA OUT
D
F/F
1
D
F/F
2
D
F/F
3
D
F/F
4
D
F/F
5
D
F/F
6
D
F/F
7
D
F/F
2
D
F/F
3
D
F/F
4
D
F/F
5
D
F/F
6
D
F/F
7
DATA IN
De-scrambler
DATA IN
D
F/F
1
DATA OUT
MODULO 2 ADDER(XOR GATE)
92
93
94
95
96
97
Synthesis Report
SCRAMBLER
Selected device:
Logic Utilization
Used
Available
% Utilization
Used
Available
% Utilization
DE SCRAMBLER
Selected device:
Logic Utilization
Result
Thus the logic circuit for Scrambler and De-scrambler is designed using
VHDL and its functionality has been verified.
98
99
100