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Computer as a Hierarchical System History of Computers Designing for performance Computer Components Computer Functions

Computer Organization & Architecture Module 1


Presented by
MANU FRANCIS
Asst. Professor
Dept. of EIE

June 29, 2015

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CONTENTS
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Computer as a Hierarchical System

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History of Computers

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History of Computers
Designing for performance

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History of Computers
Designing for performance
Computer Components

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History of Computers
Designing for performance
Computer Components
Computer Functions

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Computer as a Hierarchical System


History of Computers
Designing for performance
Computer Components
Computer Functions
Interconnection Structures

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Computer as a Hierarchical System


History of Computers
Designing for performance
Computer Components
Computer Functions
Interconnection Structures
BUS Interconnection

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Computer as a Hierarchical System


History of Computers
Designing for performance
Computer Components
Computer Functions
Interconnection Structures
BUS Interconnection
Central Processing Unit

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Computer as a Hierarchical System


History of Computers
Designing for performance
Computer Components
Computer Functions
Interconnection Structures
BUS Interconnection
Central Processing Unit
Computer Arithmetic

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Computer as a Hierarchical System


History of Computers
Designing for performance
Computer Components
Computer Functions
Interconnection Structures
BUS Interconnection
Central Processing Unit
Computer Arithmetic
Instruction Sets

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Computer as a Hierarchical System


History of Computers
Designing for performance
Computer Components
Computer Functions
Interconnection Structures
BUS Interconnection
Central Processing Unit
Computer Arithmetic
Instruction Sets
Instruction Sets : Addressing Modes and Formats

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Computer as a Hierarchical System


History of Computers
Designing for performance
Computer Components
Computer Functions
Interconnection Structures
BUS Interconnection
Central Processing Unit
Computer Arithmetic
Instruction Sets
Instruction Sets : Addressing Modes and Formats
Processor Structure and Function

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Computer as a Hierarchical System


History of Computers
Designing for performance
Computer Components
Computer Functions
Interconnection Structures
BUS Interconnection
Central Processing Unit
Computer Arithmetic
Instruction Sets
Instruction Sets : Addressing Modes and Formats
Processor Structure and Function
REDUCED INSTRUCTION SET COMPUTERS

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Computer as a Hierarchical System

Computer Organization - Operational units and


interconnections.
Computer Architecture - Attributes of system visible to
programmer.
Structure & Function
Structure - way in which the components are interrelated
Function - Operation of each individual component as part of
structure

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Figure : Computer
Figure : Functional View of
Computer.

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History of Computers

First Generation: Vacuum Tubes


ENIAC
Von Neumann Machine

Second Generation : Transistors


IBM 7094

Third Generation: Integrated Circuits


IBM System/360
DEC PDP - 8

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Designing for performance

Driving factors behind the need to design for performance


Microprocessor Speed
Branch Prediction
Data Flow Analysis
Speculative execution

Performance Balance

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Computer Components Computer Functions

von Neumann architecture based on:


Data instructions in single read-write memory
Contents in memory are addressed by location
Execution in sequential fashion

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Computer Components Computer Functions

Hardware and Software Approaches

Figure : Hardware and Software Approaches

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Computer Components Computer Functions

Hardware and Software Approaches

Hardwired Program
Program in the form of hardware
Configuration of particular components for specific
computation
Software
General purpose configuration of arithmetic and logic
functions.
Based on control signal and data, result will be generated.
Unique code for each control signal

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Computer Components Computer Functions

Components of System

Figure : Computer Components: Top Level View

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Computer Components Computer Functions

Components of System

CPU
Instruction interpreter + arithmetic and logic functions.
MAR - address in memory for next read/write
MBR - data to be written or received
I/O Components
Accepting data
Memory
To store instructions and data

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Computer Functions

Instruction Fetch & Execute

Figure : Basic Instruction Cycle

Basic function - Execution of Program


Instruction processing - Fetch and Execute
Instruction cycle - processing for single instruction
Basic instruction cycle constitutes - fetch cycle and execute
cycle
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Computer Functions

Instruction Fetch & Execute

Processor fetches instruction from memory


PC stores address of next instruction
IR loads instructions
Processor takes action based on instructions
Processor Actions
Processor to Memory data transfer
Processor to I/O data transfer
Data Processing
Control

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Computer Functions

Instruction and Integer Format

Figure : Formats

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Computer Functions

Instruction Fetch & Execute - Example

Figure : Example - Program Execution


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Computer Functions

Instruction Cycle State Diagram

Instruction address calculation - next instruction address


Instruction fetch - read from memory to processor
Instruction opcode decoding
Operand address calculation
Operand fetch
Data operation
Operand store
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Computer Functions

Interrupts

Mechanism which interrupts normal processing


Classes of Interrupts
Program - Generated by some conditions
Timer
I/O - Generated by an I/O controller
Hardware failure - By power failure or memory error

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Computer Functions

Program Flow of Control

Figure : Program Flow of Control


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Computer Functions

Program Timing - Short I/O Wait

Figure : Program Timing: Short I/O wait

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Computer Functions

Interrupts and Instruction Cycle


With interrupts - processor can execute other instructions
Interrupt request - signal, when external device is ready to
accept data
Interrupt handler - Execute instructions
Interrupt - Interrupt of normal sequence of execution
Program doesnot need to include special codes for interrupt
If an interrupt is pending:
Suspends execution of current program - save next instruction
address of pc
Sets next address of PC - address of interrupt handler

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Computer Functions

Transfer of Control via Interrupts

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Computer Functions

Instruction Cycle with Interrupts

Figure : Instruction Cycle with Interrupts

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Computer Functions

Instruction Cycle State Diagram with Interrupts

Figure : Instruction Cycle State Diagram with Interrupts

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Computer Functions

Multiple Interrupts

Two approaches
Sequential Interrupt Processing - disable other interrupts
Nested Interrupt Processing (ISR processing) - Priority based
execution of interrupt

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Computer Functions

Multiple Interrupts

Figure : Transfer of Control with


Figure : Transfer of Control with
Multiple Interrupts - Sequential
Multiple Interrupts - Nested
Interrupts
Interrupts

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Computer Functions

I/O Functions

I/O module can exchange data with processor


Designating by address location

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Interconnection Structures
Collection of Paths connecting computer components

Figure : Computer Modules

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Interconnection Structures

Interconnection STructures support:


Memory to Processor
Processor to Memory
I/O to Processor
Processor to I/O
I/O to or from Memory

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BUS Interconnection

BUS is a communication pathway connecting many devices


It is a shared transmission medium
One device can at a time can successfully transmit
Bus consists of multiple pathway, able to transmit 1 or 0
System Bus - Bus connects main components

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Bus Structure

Figure : Bus Interconnection Scheme

Bus lines - Functional Groups


Data lines - Moving data between modules, collectively called
as data bus
Address lines - designate source or destination address
Control Lines - Control the access to and the use of the data
and address lines
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Typical Control Lines


Control Lines
Memory Write
Memory Read
I/O Write
I/O read
Transfer ACk
Bus request
Bus grant
Interrupt request
Interrupt ACK
Clock
Reset
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Multiple-Bus Hierarchies
More devices connected to sinle bus, performance will suffer
Bus length increases, more propagation delay
Data transfer demand approaches capacity of bus

Figure : Bus Configuration

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Elements of Bus Design

Bus Types
Method of Arbitration
Timing
Bus Width
Data Transfer type

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Bus Types
Time Multiplexed
Address and data through same line
Initially address through line
After certain period of time data through line
Advantages - Fewer lines required
Disadvantages - More complex circuity required
Dedicated
Separate address and data lines
Each bus connects only a subset modules
Eg: I/O bus interconnect I/O modules only
Advantage - High throughput
Disadvantage - Increased size
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Method of Arbitration

Centralized
Bus controller or arbiter is responsible for allocating time on
bus
Distributed
No central controller
Each module contains control logic
Master may initiate data transfer

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Timing

Synchronous Timing
Occurrence of events on the bus is determined by a Clock
Clock Cycle - 1 - 0 transmission
All events start at the beginning of clock
Asynchronous Ting
Occurrence of one event depends on previous event

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Synchronous Bus Operations

Figure : Synchronous Bus Configuration

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Asynchronous Bus Operation

Figure : Asynchronous Bus


Configuration - Read

Computer Organization & Architecture - Module 1

Figure : Asynchronous Bus


Configuration - Write

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Bus Width

Wider data bus - greater transfer rate


Width of address bus - greater range of locations

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Data Transfer Type

Figure : Data Transfer Operations

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Data Transfer Operations

Write (multiplexed) Operation


Write (Non multiplexed) Operation
Read (multiplexed) Operation
Read (Non multiplexed) Operation
Block Data transfer

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PCI

Peripheral Component Interconnect


Processor independent bus
PCI delivers better system performance for high speed I/O
devices
PCI is designed to support variety of microprocessor based
configurations
PCI functions use synchronous timing and a centralized
arbitration scheme.

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PCI Configutations

Figure : PCI Configurations

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PCI Bus Structure


PCI is configured as 32 or 64 bit bus.
Fucnctional Groups
System Pins - Clock and Reset
Address and Data Pins - Time multiplexed
Interface control pins - Control timing of transactions
Arbitration pins - Not shared, each PCI has its own arbiter
Error reporting pins
Additional Functional Groups
Interrupt pins
Cache support pins
64 bit bus extension pins
JTAG/Boundary scan pins
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PCI Commands
Bus activity occurs in the form of transactions between master and
target.
Commands are:
Interrupt Acknowledge
Serial Cycle
I/O Read
I/O Write
Memory Read
Memory Write
Memory Read Line
Memory Read Multiple
Memory Write
Memory write and Invalidate
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PCI Data Transfer

Each data transfer - one address phase and more data phase

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Data Transfer - Read

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Figure : PCI Data Transfer
- Read

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PCI Bus Arbitter

Use a centralized, synchronous arbitration scheme


Each master has a unique request (REQ) and grant (GNT)
signal
Simple requestgrant handshake is used to grant access to the
bus
Can use a first-come-first-served approach,
a round-robinVJEC, Chemperi
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PCI Arbitration between two masters - Example

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CPU

Contents
Computer Arithmetic
Instruction Sets: Characteristics and Functions
Instruction Sets: Addressing Modes and Formats
CPU Structure and Function
Reduced Instruction Set Computers
Instruction Level Parallelism

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Arithmetic and Logic Unit

Performs arithmetic and logical operations on data.


Receives and stores data into registers
Also set flags
Flag values stored in registers
Control unit provides signal to control operation, data
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movement

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Integer Representation

If an n-bit sequence of binary digits, an1 an2 ....a1 a0 . Then


integer value is
n1
X
2 i ai

(1)

i=0
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Sign-Magnitude Representation

Sign Magnitude

a=

n2
P i

2 ai if an1 = 0

i=0

n2
P i

2 ai if an1 = 1

(2)

i=0

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Sign Magnitude - Drawbacks

Consideration of both the signs of the numbers and their


relative magnitudes to carry out any operation
There are two representations of 0

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2s Compliment Representation

Uses the most significant bit as a sign bit


Change form sign-magnitude - in the way that the other bits
are interpreted
Focuses on rules for producing negative numbers
Sign Extension

A = 2n1 an1 +

n2
X

2i ai

(3)

i=0

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Integer Arithmetic

Arithmetic operations in 2s compliment form


Negtaion
In 2s compliment form, follow the below rules
Take the Boolean complement of each bit
add 1

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Addition and Subtraction

Addition
Chance of overflow
When overflow occurs if and only if the result has the
opposite sign
If overflow occurs, ALU will not consider result- Overflow Rule
Subtraction
To subtract one number take the twos complement of the
subtrahend and add it to the minuend. - Subtraction Rule

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Block Diagram of Hardware for Addition and Subtraction

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Multiplication

Unsigned Integers
Generation of partial products then summation
Partial product - multiplier bit is 0, the partial product is
0.When the multiplier is 1, the partial product is the
multiplicand
The total product is produced by summing the partial
products
For n bit multiplication, Result will 2n bit length

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Unsigned Multiplication

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Twos Compliment Multiplication

Different Approaches
Covert both multiplier to positive and then take twos if sign of
original numbers differed
Booth Algorithm

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Booth Multiplication

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Unsigned integer division

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Floating Point Representation

Steps for representation


The fractional part can be converted by multiplication
Append x20 to the end of the binary number
Normalize the number
Place the mantissa into the mantissa field of the number
Add the bias to the exponent of two
Set the sign bit
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Floating Point Arithmetic

Addition
Subtraction
Multiplication
Division

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Machine Instruction Characteristics

machine instructions - Determines operation of processor


instruction set. - Collection of instructions
Elements of a Machine Instruction
Operation code - Operation to be performed
Source operand reference - inputs for the operation
Result operand reference:
Next instruction reference

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Elements of a Machine Instruction

Source and result operands can be in one of four areas:


Main or virtual memory
Processor register
Immediate
I/O device

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Instruction Representation

Instruction is represented by a sequence of bits


Instruction is divided into fields
Most instruction sets, more than one format is used
During execution, instruction is loaded into IR
Processor extracts data from instructions and perform
operations
use symbolic representations
Opcodes are represented by abbreviations
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Instruction Types

Categorize instruction types as follows


Data processing
Data storage
Data movement
Control

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Number of Addresses

Maximum number of addresses one might need in an instruction


Arithmetic and logic instructions will require the most operands
Maximum of two addresses to reference source operands
Third address, which defines a destination operand
Address of next instruction

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Number of Addresses

Figure : Program for Y =


Computer Organization & Architecture - Module 1

AB
C +(DxE )

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Number of Addresses

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Instruction Set Design


Fundamental design issues:
Operation repertoire: How many and which operations to
provide
Data types: The various types of data upon which operations
are performed
Instruction format: Instruction length (in bits), number of
addresses, size of various fields, and so on
Registers: Number of processor registers that can be
referenced by instructions, and their use
Addressing:The mode or modes by which the address of an
operand is specified

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Types of Operands

general categories of data are


Address
Numbers
Characters
Logical Data

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Numbers

There is a limit to the magnitude of numbers representable


In the case of floating-point numbers, a limit to their precision
Types of common numerical data in computers:
Binary integer
Binary floating point
Decimal - packed decimal representation for decimal numbers

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Characters

Character code -International Reference Alphabet (IRA)


United States as the American Standard Code for Information
Interchange(ASCII)
Each character code is represented by a unique 7-bit pattern
Some of the patterns represent control characters - controlling
the printing of characters
The eighth bit may be set to 0 or used as a parity bit for error
detection

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Logical Data

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Types of Operations

Data transfer
Move - Transfer word or block from source to destination
Store - Transfer word from processor to memory
Load - Transfer word from memory to processor
Exchange - Swap contents of source and destination
Clear- (reset) Transfer word of 0s to destination
Set - Transfer word of 1s to destination
Push - Transfer word from source to top of stack
Pop - Transfer word from top of stack to destination

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Types of Operations

Arithmetic
Add - Compute sum of two operands
Subtract - Compute difference of two operands
Multiply - Compute product of two operands
Divide - Compute quotient of two operands
Absolute - Replace operand by its absolute value
Negate - Change sign of operand
Increment - Add 1 to operand
Decrement - Subtract 1 from operand

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Types of Operations
Logical
Perform - logical AND
OR - Perform logical OR
NOT - (complement) Perform logical NOT
Exclusive-OR - Perform logical XOR
Test - Test specified condition; set flag(s) based on outcome
Compare - Make logical or arithmetic comparison of two or
more operands; set flag(s) based on outcome
Set Control Variables - Class of instructions to set controls for
protection purposes, interrupt handling, timer control, etc.
Shift Left (right) - shift operand, introducing constants at end
Rotate Left (right) - shift operand, with wraparound end
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Types of Operations
Transfer of Control
Jump (branch) - Unconditional transfer; load PC with
specified address
Jump Conditional - Test specified condition; either load PC
with specified address or do nothing, based on condition
Jump to Subroutine - Place current program control
information in known location; jump to specified address
Return - Replace contents of PC and other register from
known location
Execute - Fetch operand from specified location and execute
as instruction; do not modify PC
Skip - Increment PC to skip next instruction
Skip Conditional - Test specified condition; either skip or do
nothing based on condition
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Types of Operations

Input/Output
Input (read) - Transfer data from specified I/O port or device
to destination (e.g., main memory or processor register)
Output (write) - Transfer data from specified source to I/O
port or device
Start - I/O Transfer instructions to I/O processor to initiate
I/O operation
Test - I/O Transfer status information from I/O system to
specified destination

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Types of Operations
Conversion
Translate - Translate values in a section of memory based on
a table of correspondences
Convert - Convert the contents of a word from one form to
another (e.g., packed decimal to binary)
Data Transfer
Transfer data from one location to another - If memory is
involved: Determine memory address Perform
virtual-to-actual-memory address transformation Check cache
Initiate memory read/write

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Assembly Langage

CPU can execute Machine instructions

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Addressing
To refer a large range of locations in main memory or, for some
systems, virtual memory
Common addressing techniques
Immediate
Direct
Indirect
Register
Register indirect
Displacement
Stack

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Addressing

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Immediate Addressing

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Immediate Addressing

Operand = A

(4)

operand value is present in the instruction


used to define and use constants
Advantage - No memory reference other than the instruction
fetch is required to obtain the operand
Disadvantage - size of the number is restricted

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Direct Addressing

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Direct Addressing

EA = A

(5)

Address field contains the effective address of the operand


requires only one memory reference
Limitation - provides only a limited address space

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Indirect Addressing

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Indirect Addressing

EA = (A)

(6)

Address field refer to the address of a word in memory


Advantage - For a word length of N, an address space of 2N is
now available
Limitation - requires two memory references to fetch the
operand

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Register Addressing

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Register Addressing

EA = R

(7)

Address field refers to a register rather than a main memory


address
Advantage - same as indirect addressing.

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Register Indirect Addressing

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Register Indirect Addressing

EA = (R)

(8)

Analogous to indirect addressing


Address field refers to a memory location or a register.
Overcomes address space limitation
Less memory reference than indirect addressing

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Displacement Addressing

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Displacement Addressing

EA = A + (R)

(9)

combines the capabilities of direct addressing and register


indirect addressing
Displacement addressing requires that the instruction have
two address fields
one is explicit and other is implicit
three of the most common uses: Relative addressing,
Base-register addressing, Indexing

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Displacement Addressing

Relative Addressing
Also called PC-relative addressing
Implicitly referenced register is the program counter (PC).
next instruction address is added to the address field to
produce the EA
three of the most common uses: Relative addressing,
Base-register addressing, Indexing

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Displacement Addressing

Base Register Addressing


Referenced register contains a main memory address
The address field contains a displacement (usually an
unsigned integer representation) from that address.
Register reference may be explicit or implicit

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Indexing

Indexing
address field references a main memory address,
Referenced register contains a positive displacement from that
address
postindexing : EA = (A) + (R)
preindexing : EA = (A + (R))

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Stack Addressing

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Stack Addressing

EA = topofstack

(10)

Referred as last-in-first-out queue


stack is a reserved block of locations
Items are appended to the top of the stack
Stack Pointer - Top address of stack
stack mode of addressing is a form of implied addressing

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Instruction Formats

Layout of the bits of an instruction


Instruction format include opcode and operands
Explicit operands referenced through addressing modes

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Instruction Formats - Design Issues

Instruction Length
Affected by memory size, memory organization, bus structure,
processor speed etc
Trade-off here - Powerful instruction repertoire and a need to
save space
Instruction length should be equal to the memory-transfer
length or multiple.
Processor speed

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Instruction Formats - Design Issues


Allocation Bits
Trade-off between the number of opcodes and the power of
the addressing capability.
More opcodes means more bits, reduces the number of bits
available for addressing
Factors determines use of the addressing bits
Number of addressing modes: explicit addressing, more bits
Number of operands
Register versus memory
Number of register sets
Address range
Address granularity
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Instruction Formats - Design Issues

Variable-Length Instructions
Provide a large repertoire of opcodes, with different opcode
lengths. Addressing can be more flexible
Increase in the complexity of the processor

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Variable-Length Instructions

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Processor Organization

Processor must do
Fetch instruction: Reads an instruction from memory
Interpret instruction: The instruction is decoded to determine
what action is required.
Fetch data: Reading data from memory or an I/O module
Process data: Perform some arithmetic or logical operation on
data.
Write data: Writing data to memory or an I/O module

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Processor - Components

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Processor

Connects rest of system with system bus


Major components - ALU, Control Unit, Register
ALU - actual computation or processing of data
Control unit - controls the movement of data and instructions
into and out of the processor and controls the operation of
the ALU
Registers.- Storage locations
Internal Processor bus

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Internal Structure of the CPU

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Register Organization

Registers performs two roles:


User-visible registers: To minimize main memory references by
optimizing use of registers
Control and status registers: Used by the control unit to
control the operation of the processor

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Register Organization

User-Visible Registers
General purpose - Can contain the operand for any opcode,
may be dedicated registers, can be used for addressing
functions
Data - to hold data
Address - Segment pointers, Index registers, Stack pointer
Condition codes - flags, part of control register

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Control and Status Registers

Essential Registers
Program counter (PC): Contains the address of an instruction
to be fetched
Instruction register (IR): Contains the instruction most
recently fetched
Memory address register (MAR): Contains the address of a
location in memory
Memory buffer register (MBR): Contains a word of data to be
written to memory or the word most recently read

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Control and Status Registers


Program Status Word
Sign: Contains the sign bit of the result of the last arithmetic
operation.
Zero: Set when the result is 0.
Carry: Set if an operation resulted in a carry (addition) into or
borrow (subtraction) out of a high-order bit.
Equal: Set if a logical compare result is equality.
Overflow: Used to indicate arithmetic overflow.
Interrupt Enable/Disable: Used to enable or disable interrupts.
Supervisor: Indicates whether the processor is executing in
supervisor or user mode.
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Register Design Issues

Whether to use completely general-purpose registers or to


specialize their use.
Number of registers, either general purpose or data plus
address, to be provided.
Register length

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Example Microprocessor Register Organizations

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Instruction Cycle

Fetch: Read the next instruction from memory into the


processor
Execute: Interpret the opcode and perform the indicated
operation.
Interrupt: If interrupts are enabled and an interrupt has
occurred, save the current process state and service the
interrupt.

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Instruction Cycle

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Instruction Cycle

Indirect Cycle
indirect addressing is used, then additional memory accesses
After fetching, operands must be identified
Then operand memory will be fetched
Then check for indirect addressing

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Instruction Cycle - Data Flow

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Instruction Cycle - Data Flow Indirect Cycle

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Instruction Cycle
Data Flow
Processor uses a memory address register (MAR), a memory
buffer register (MBR), a program counter (PC), and an
instruction register (IR)
Fetch cycle - an instruction is read from memory
PC - address of the next instruction to be fetched
PC address is moved to the MAR and placed on the address
bus
Control unit requests a memory read, and the result is placed
on the data bus and copied into the MBR and then moved to
the IR.
After fetch - control unit examines the contents of the IR to
determine if it contains an operand specifier using indirect
addressing
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Instruction Cycle
Data Flow - Conti..
The rightmost N bits of the MBR, which contain the address
reference, are transferred to the MAR
Control unit requests a memory read, to get the desired
address of the operand into the MBR
Execute cycle - transferring data among registers, read or
write from memory or I/O, and/or the invocation of the ALU
Interrupt cycle - current contents of the PC must be saved so
that the processor can resume normal activity after the
interrupt
PC are transferred to the MBR to be written into stack

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Instruction Pielining

Pipelining Strategy
Technique used in the design of computers to increase their
instruction throughput
Pipeline - basic instruction cycle is broken up into a series
Processing each instruction sequentially
Different steps can be executed concurrently

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Pipelining
Siplified View

Fetch the next instruction in parallel with the execution of the


current one
First stage fetches an instruction and buffers it
When second stage is free, the first stage passes it the
buffered instruction
Instruction prefetch
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Pipelining
Decomposition of the instruction processing
Fetch instruction (FI): Read the next expected instruction into
a buffer.
Decode instruction (DI): Determine the opcode and the
operand specifiers.
Calculate operands (CO): Calculate the effective address of
each source operand. This may involve displacement, register
indirect, indirect, or other forms of address calculation.
Fetch operands (FO): Fetch each operand from memory.
Operands in registers need not be fetched.
Execute instruction (EI): Perform the indicated operation and
store the result, if any, in the specified destination operand
location.
Write operand (WO): Store the result in memory
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Pipelining

Factors limits performance enhancement


Execution time will generally be longer than the fetch time
Conditional branch instruction makes the address of the next
instruction to be fetched unknown. so need to wait execute
stage for next address
CO stage may depend on the contents of PC that could be
altered by a previous instruction.

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Conditional Branch on Instruction Pipeline Operation

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Pipelining Algorithm

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Pipeline Performance
Measures of pipeline performance
= max[i + d] = m + d1 i k

(11)

Where
i = time delay of the circuitry in the ith stage of the pipeline m
= maximum stage delay (delay through stage which experiences
the largest delay)
k = number of stages in the instruction pipeline
d = time delay of a latch, needed to advance signals and data
from one stage to the next
Total time required for a pipeline with k stages to execute n
instructions
Tk,n = [k + (n 1)]
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(12)
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Pipeline Hazards

A pipeline hazard occurs when the pipeline, or some portion of


the pipeline, must stall because conditions do not permit continued
execution.
Also referred as Pipeline Bubble. Different Types of Hazards
Resource Hazards
Data Hazards
Control Hazards

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Pipeline Hazards

Resource Hazards
Occurs when two (or more) instructions that are already in
the pipeline need the same resource
Result is that the instructions must be executed in serial
rather than parallel
Referred to as a structural hazard
Another example of a resource conflict is a situation in which
multiple instructions are ready to enter the execute instruction
phase and there is a single ALU

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Resource Hazards

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Pipeline Hazards

Data Hazards
When there is a conflict in the access of an operand location
Two instructions in a program are to be executed in sequence
and both access a particular memory or register operand

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Data Hazards

Read after write (RAW)


Read after write (RAW), or true dependency: An instruction
modifies a register or memory location and a succeeding
instruction reads the data in that memory or register location.
Example.
R2 < R1 + R3
R4 < R2 + R3

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Data Hazards

Write after read (RAW)


An instruction reads a register or memory location and a
succeeding instruction writes to the location
R4 < R1 + R3
R3 < R1 + R2

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Data Hazards

write after write (WAW)


Write after write (WAW), or output dependency: Two instructions
both write to the same location.
R2 < R1 + R2
R2 < R4 + R7

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Pipeline Hazards

Control Hazards
known as a branch hazard
Control Hazards arise from the pipelining of branches and
other instructions that change the Program Counter
When a branch is executed it may or may not change the
Program Counter and thus may not change the instruction
that is to be fetched

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Pipelining - Dealing With Branches

Approaches
Multiple streams
Prefetch branch target
Loop buffer
Branch prediction
Delayed branch

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Dealing With Branches

Multiple streams
replicate the initial portions of the pipeline and allow the pipeline
to fetch both instructions Problems with this approach
With multiple pipelines there are contention delays for access
to the registers and to memory
Additional branch instructions may enter the pipeline (either
stream) before the original branch decision is resolved.

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Dealing With Branches

Prefetch branch target


The target of the branch is prefetched, in addition to the
instruction following the branch
This target is then saved until the branch instruction is
executed

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Multiple streams

Loop Buffer
A loop buffer is a small, very-high-speed memory maintained
by the instruction fetch stage of the pipeline and containing
the n most recently fetched instructions, in sequence
If a branch is to be taken, the hardware first checks whether
the branch target is within the buffer
If so, the next instruction is fetched from the buffer
Advantages :- Less memory access time, for dealing with loops

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Dealing With Branches

Branch Prediction
Various Techniques
Predict never taken
Predict always taken
Predict by opcode
Taken/not taken switch
Branch history table

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Branch Prediction

Predict Not Taken


simply allowing the hardware to continue as if the branch were
not executed
Predict always taken
simply allowing the hardware to continue as if the branch were
not executed

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Branch Prediction

Predict by opcode
By reading opcode
Taken/not taken switch
One bit reflects branching history
Branch history table
Two bits or more for branching status. It can store more than two
previous conditions

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Branch Prediction

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Branch Prediction

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Delayed Branch

rearranging instructions within a program


Branch instructions occur later than desired

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Why CISC
larger number of instructions and more complex instructions.
complex machine instructions are often hard to exploit
Compiler Simplification - Optimization more difficult
Program takes up less memory but Memory is now cheap
number of bits of memory occupied may not be noticeably
smaller
Longer opcodes are required, producing longer instructions
More complex control unit
thus simple instructions take longer to execute
It is far from clear that CISC is the appropriate solution

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REDUCED INSTRUCTION SET COMPUTERS

Small, highly optimized set of instructions


Short execution time
Pipelining
Many registers
Uses a load-store architecture

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Characteristics of RISC

One instruction per machine cycle - little or no need for


microcode; the machine instructions can be hardwired
Register-to-register operations - simple LOAD and STORE
operations
Simple addressing modes
Simple instruction formats

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CISC Vs RISC

RISC - Single Instruction Size - 4 byte


Smaller number of addressing modes, less than 5
No indirect addressing
No operations combine with load/store with arithmetic
No more than one memory addressed per instruction
Maximum number of uses for memory management unit
Number of bits for integer register - 5 or more
Number of bits for floating point - 4 or more

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Computer as a Hierarchical System History of Computers Designing for performance Computer Components Computer Functions

RISC Pipelining

Load/Store : 3 stages
I: Instruction fetch
E: Execute : Calculate memory address
D: Memory : Register to memory or memory to register
operation
E1: Register file read
E2: ALU operation and Register write

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VJEC, Chemperi

Computer as a Hierarchical System History of Computers Designing for performance Computer Components Computer Functions

Pipelining

Figure : Sequential Execution

Computer Organization & Architecture - Module 1

155 / 158

VJEC, Chemperi

Computer as a Hierarchical System History of Computers Designing for performance Computer Components Computer Functions

Pipelining

Computer Organization & Architecture - Module 1

156 / 158

VJEC, Chemperi

Computer as a Hierarchical System History of Computers Designing for performance Computer Components Computer Functions

Pipelining

Computer Organization & Architecture - Module 1

157 / 158

VJEC, Chemperi

Computer as a Hierarchical System History of Computers Designing for performance Computer Components Computer Functions

Computer Organization & Architecture - Module 1

158 / 158

VJEC, Chemperi