CMOS Basics

Advanced VLSI Design

CMPE 640

MOS: Metal Oxide Semiconductor

Transistors are built on a Silicon (semiconductor) substrate.
Pure silicon has no free carriers and conducts poorly.
Dopants are added to increase conductivity: extra electrons (n-type) or extra holes (p-type)
MOS structure created by superimposing several layers of conducting, insulating and transistor-forming materials.
Metal gate has been replaced by polysilicon or poly in modern technologies.
There are two types of MOS transistors:
nMOS

: Negatively doped silicon, rich in electrons.

pMOS

: Positively doped silicon, rich in holes.

CMOS: Both type of transistors are used to construct any gate.

CMOS Basics

Advanced VLSI Design

CMPE 640

nMOS and pMOS

Four terminal devices: Source, Gate, Drain, body (substrate, bulk).

Source

Source

Gate

p substrate

Drain
Polysilicon

Thin
Oxide

SiO2

Drain

L
n+

Gate

nMOS

n+

n+
p

n+

Source

Gate

bulk Si

Drain

Polysilicon
SiO2

pMOS
p+

p+
n

bulk Si

CMOS Basics

Advanced VLSI Design

CMPE 640

CMOS Inverter Cross-Section

Cadence Layer's for AMI 0.6mm technology

p-substrate contact (cc)

p-diffusion contact (cc)

(source)
metal1
n-substrate contact (cc)

m1-m2 contact (via)

metal2

n-diffusion contact (cc)

(Out)
(source)
glass(insulator)

VDD

GND

(pactive)

layer #3
layer #2
p+

n+

p+

n+
(drains)

p+

n+

layer #1

n-well (nwell)

(nactive)

p substrate (black background)

n-transistor polysilicon gate (poly )

p-transistor
3

Advanced VLSI Design

CMOS Basics

CMPE 640

CMOS Cadence Layout

Cadence Layout for the inverter on previous slide

CMOS Basics

Advanced VLSI Design

CMPE 640

MOS Transistor Switches

We can treat MOS transistors as simple on-off switches with a source (S), gate (G) (controls the state of the switch) and drain (D).
1 represents high voltage, VDD (5V, 3.3V, 1.8V, 1.2V, <=1.0V today, .....)
0 represent low voltage - GND or VSS. (0V for digital circuits)

d
nMOS

pMOS

g=0

g=1

d
OFF

ON

OFF

ON
s

CMOS Basics

Advanced VLSI Design

CMPE 640

Signal Strengths
Signals such as 1 and 0 have strengths, measures ability to sink or source current
VDD and GND Rails are the strongest 1 and 0
Under the switch abstraction, G has complete control and S and D have no effect.
In reality, the gate can turn the switch on only if a potential difference of at least Vt
exists between the G and S.
We will look at Vt in detail later on in the course.
Thus signal strengths are related to Vt and therefore p and n transistors produce signals with
different strengths
Strong 1: VDD, Strong 0: GND, Weak 1 :(~VDD -Vt) and Weak 0 :(~GND + Vt).

nMOS

G 1
S

0
*** Strong 0***

1
Weak 1

pMOS

G 0

0
Weak 0

1
*** Strong 1***
6

CMOS Basics

Advanced VLSI Design

CMPE 640

CMOS Inverter

Vdd

P1
A

Out
N1

CMOS Inverter
THE CONFIGURATION BELOW FOR A BUFFER IS NOT A GOOD IDEA. WHY?

A
P1

Vdd
N1

BAD IDEA

Out

CMOS Basics

Advanced VLSI Design

CMPE 640

NAND and NOR CMOS Gates

Vdd
A

P1

A
B

P2

Out
N2
N1

Vdd
A

P1
P2
N1

A
B

B
Out

N2

CMOS Basics

Advanced VLSI Design

CMPE 640

Pass Transistor
The off-state of a transistor creates a high impedance condition Z at the drain.
No current flows from source to drain. So transistors can be used as switches.

g=0

g
s

Input g = 1 Output
0
strong 0

g=1
s

d
g=1
s

1
Input

g=0

g
s

g=1

degraded 1
g=0

Output
degraded 0

g=0

strong 1

However, as we previously discussed this will produce degraded outputs, if only one
transistor is used as a switch.
9

CMOS Basics

Advanced VLSI Design

CMPE 640

Transmission Gates

A
P1
N1
A

In

One pMOS and one nMOS in parallel.

Note that neither transistor is connected to VDD or GND.

Out

A and A control the transmission of a signal on In to Out.

Transmission gates act as tristate buffers.

Input
g
a

b
gb

b
gb

g = 0, gb = 1
a
b

g = 1, gb = 0
0
strong 0

g = 1, gb = 0
a
b

g = 1, gb = 0
strong 1
1

g
a

g
b

gb

Output

b
gb
10

CMOS Basics

Advanced VLSI Design

CMPE 640

Transmission Gate Application: Select Mux

Transmission Gate

2-to-1 MUX

Select
A
In

Out

Select

Out

Select

Truth Table for 2-to-1 MUX

Select

Out

VDD
Select

Out = A.S + B.S

How many transistors are required to implement this using CMOS gates?
11

CMOS Basics

Advanced VLSI Design

CMPE 640

D Latch
Positive
level-sensitive
latch

CLK

Latch

CLK

Q
Q

CLK
D

CLK

Q
Q

0
CLK
If CLK is unavailable one extra inverter
needed to generate it using CLK

CLK

CLK
12

CMOS Basics

Advanced VLSI Design

CMPE 640

D Flip-Flop
Positive
edge-triggered
flip-flop
a.k.a
master-slave
flip-flop

CLK

CLK
D

Flop

Q
Q

CLK

CLK
CLK

QM

D
CLK CLK Master
QM

Master

Latch

Latch

CLK

Slave

Q
CLK CLK Slave

Q
CLK

CLK

If CLK is unavailable one extra inverter needed to generate it using CLK

13

CMOS Basics

Advanced VLSI Design

CMPE 640

D Flip-Flop Operation
D

QM

QM follows D, Q is latched
CLK = 0

QM

QM transferred to Q, QM latched
CLK = 1

CLK

Positive
edge-triggered
flip-flop

D
Q

14

CMOS Basics

Advanced VLSI Design

CMPE 640

More CMOS Gates

Vdd
B
P1
Vdd
A

P2

Out

N2

N1

15

CMOS Basics

Advanced VLSI Design

CMPE 640

And More CMOS Gates

A
B

Out

16

CMOS Basics

Advanced VLSI Design

CMPE 640

And More CMOS Gates

Vdd
P2

P1

P3
P4
OAI

N1

B
C

N2

N3 N4

17