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Lecture 01

Fundamentals of
Microcomputers

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Daniel D. DECE

In this Lecture:

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Definitions
A microcomputer system
Evolution of the Microcomputer

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Definitions - basic
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Cycle
-Period of the CPU clock
-The fundamental unit of time for CPU activity

Instruction
A meaningful command to be executed by the CPU along with
the data operands.

Register
The fastest temporary data storage in the memory hierarchy

ALU
A digital logic circuit to process logic and arithemetic

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Definitions - basic
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Memory
-One of the two basic elements of a computer system
(paging, virtual and physical memory, MMU)

Memory hierarchy
Register Cache(levels)RAMDisks

Cache
-fast static memory to hold most frequently used data/instruction
-Multiple levels of cache
- Cache coherency
- Cache flushing
- Cache replacement
- Hit ratio
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Definitions - arch
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CISC
-Complex instructions, Simpler compiler, complex and large
hardware

RISC
-Few and simple instructions, complex compilers, small and
simple hardware

Pipeline
- A structure just like a product assembly line
- Process the next task while the current one is in progress

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Definitions - Arch
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Scalar Vs Superscalar
Executing multiple instruction in a single cycle using a single
CPU by Utilizing computing resources effectively
(SIMD, MIMD, )

In-Order Vs Out-of-order
Instructions can be executed in order sequentially or out of
order depending on the availability of data.

Issue
A term used to describe as to how the instruction execution
should flow determining branch targets
Branch prediction
Dual-issue
Speculative-issue,
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Definitions - Hardware
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Process
Determines the kind of layout used to implement the digital
logic cells. (CMOS, HMOS, LP-CMOS, DMS, )

Process tech/feature size


Usually determined by the gate length of the transistors
(65nm CMOS high K Cu process, 45nm LP-CMOS, )

System on Chip (SoC)


Integration of two or more functional units on a single chip

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Definitions - systems

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Microprocessor
Control only, external memory and I/O required
8086, M68000, MIPS, SPARC, Pentium

Microcontroller
Integrated control, memory and I/O on a single chip
AVR, PIC, 8051, MSP, Coldfire

Microcomputer
Complete systems CPU, Memory, I/O, Storage,
PC, Mac, VAX, PDP, SunSparc
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A Computer system?
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Memory

Input
Microprocessor

Output

Microprocessor(P):
Contains the CPU, System bus, Control unit and
(in latest models) a MMU, low level cache and
several on-chip HW
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a Computer systemcntd

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Memory
A digital data storing element
Temporary(Working) Memory:
usually made of flip-flop latches (SRAM) or
transistor-capacitor combinations(DRAM)
Permanent(storage) memory:
usually made of high capacity magnetic/optical discs
(hard drives) or solid state devices (EEPROM, flash)
Input/output (I/O) devices
A device we use to transfer data to/from the P; an interface
controller is required b/n the P and the I/O device: Keyboard,
mouse, display

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Evolution of the P
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 1958 The first integrated circuit, in Texas USA


(Jack kilby of TI, and Noyce from Fairchild)
 1965 Gordon Moore, cofounder of Intel  Moores Law
(The No of transistors in an IC doubles every two years)
 Intel 4004 the first P
1971, 4-bit
 Intel 8008
1972, 8-bit
Originally designed for Datapoint Corp. as a CRT display controller
 Intel 8080
 1974, April - Altair 8800, 1975, MITS (256 bytes of mem, $395)
 Apple II -- Steve Jobs and Steve Wozniak 1976, Apple inc.
 Bill Gates and Allen Paul: BASIC, 1975 --> Microsoft corp.
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Evolution of the P
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 Intel 8086/8088
 1978, 16 bit: 8088, 1979, 8-bit external bus
 IBM PC; 1981
 29,000 Trs.

 Intel 80286






1982, 16-bit architecture


24-bit addressing, memory protection and virtual memory
16 MB of physical MEM and 1 GB of virtual mem
130,000 Trs. onto a single chip
IBM PC/AT in 1984, IBM PS/2 Model 50 and 60

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History of Intels Pcntd

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 Intel 80386
 1985, 32 bits
 3-5 MIPS (7 MIPS on the 25 MHz chip)
 memory paging and enhanced I/O permission features
 4GB programming model
 Intel 80486
1,200,000 Trs.
386+387+8K data and instruction cache, paging and MMU

 Intel Pentium III


1999; MMX + Internet Streaming SIMD Instructions
0.25 micron, 9.5 million Trs., 600 MHz, Superscalar arch.
32 K(16K/16K) non-blocking level 1 cache
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History of Intels Pcntd


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 Intel Core i7
March 2008, Nehalem micro-architecture, 3.066GHZ
45nm CMOS process, 731 million trs., up to 8cores/chip
Integrated Memory, graphics and direct media interface controller
Simultaneous hyper-treading, turbo-boost technology,
32K instruction & 32K L1 data cache/core, 256K L2 cache/core
8MB L3 cache,
Speculative-issue, out-of-order, superscalar microprocessor
(More on www.intel.com/products/processors/corei7)

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ARM History - ARM Ltd

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 Founded in November 1990


o Spun out of Acorn Computers
 Designs the ARM range of RISC processor cores
 Licenses ARM core designs to semiconductor partners who
fabricate and sell to their customers
o ARM does not fabricate silicon itself
 Also develop technologies to assist with the design-in of the ARM
architecture
o Software tools, boards, debug hardware, application software,
bus architectures, peripherals etc

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ARM History 1985-1995


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 1985
 Acorn Computer Group develops the world's rst commercial RISC processor
 1987
 Acorn's ARM processor debuts as the rst RISC processor for low-cost PCs
 1990
 Advanced RISC Machines (ARM) spins out of Acorn and Apple Computer's
collaboration efforts with a charter to create a new microprocessor standard.
VLSI Technology becomes an investor and the first licensee
 1993
 ARM introduces the ARM7 core
 1994
 Samsung license ARM technology
 1995
 ARM's Thumb architecture extension gives 32-bit RISC performance at 16-bit
system cost and offers industry-leading code density
 ARM extends family with ARM8 high-performance solution
 ARM launches the ARM7100 "PDA-on-a-chip

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ARM History 1996-2002


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 1997
 ARM and MicrosoD work together to extend Windows CE to the ARM architecture
 1998
 ARM Partners ship more than 50 million ARM Powered products
 Intel licensees the ARM X-Scale Architecture
 2000
 ARM introduces Jazelle technology for Java applications
 ARM introduces the ARM926EJ-S soft macrocell with enhanced DSP
 2002
 ARM introduces the SecurCore SC200 and SC210 microprocessor cores
 2003
 ARM partners ships more than 1 billion ARM powered devices!

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ARM History Present


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ARM Cortex
 Cortex A8

 in-order, dual-issue, Superscalar, 13 stage pipeline


 32k/32k instruction/data L1 cache, 256K unified L2 cache
 Neon SIMD Multimedia engine, Vector floating point coprocessor
 Jazzele Java technology
 600MHz 1.2GHz speed, 2.0 instruction/cycle
(Apple A4, Samsung Hamming Bird, TI OMAP3, Motorola Dragon Ball, etc.)
 Cortex A9 and Cortex A15
Out-of-order, predictive-issue, superscalar, 15 stage pipeline
 32k/32k instruction/data L1 cache, up to 4MB unified L2 cache
 Multi-core Architecture (duo and Quad)
 Neon SIMD Multimedia engine, Vector floating point coprocessor
 Jazzele Java technology
1 -2GHz speed, up to 4 instruction/cycle
(Apple A5, Samsung Sirtex, TI OMAP4, Freescale iMX6, Qualcomm, etc.)
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Compare/contrast
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We can classify Ps based on


o Architecture
o Application type
o Performance (in terms of speed, power consumption...)

In modern Ps, the best features from the different types
is taken to achieve the maximum performance.
Based on Architecture/instruction set, the major
categories are RISC and CISC.

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Compare/contrastRISC

Vs CISC
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CISC
 When the 8086 was introduced
Memory expensive; Compilers lousy; VLSI primitive
 Keeping the encodings of common instructions short
helped in two ways.
It made programs shorter, saving precious memory space.
Shorter instructions can also be fetched faster.
Assembly programming is easier

The 8086-based processors are an example of a complex


instruction set computer, or CISC, architecture.
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RISC Vs CISCcntd
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RISC
The idea of simpler instruction formats seemed radical in the 1980s.
RISC-based programs needed more instructions and were harder
to write by hand than CISC-based ones.
This also meant that RISC programs used more memory.
 Many newer processor designs use a reduced instruction set

computer, or RISC, architecture


Memory is faster and cheaper now.
Compilers generate code instead of assembly programmers.
Simpler hardware made advanced implementation techniques like
pipelining easier and more practical.
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Compare/contrastperformance
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The processing speed is directly proportional to the system


clock frequency, the frequency is limited by the voltage
level and dissipated heat.
 Newer processor designs claim higher frequencies at lower

voltage thresholds using new production processes:


->Low power and high speed
 Performance of a P also depends on the No. of cores in the
chip and intelligent HW/SW like, parallelism, pipelining,
on-chip caches, PMU,
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Next Lecture:

Microprocessor Fabrication
Trends and Prospects
Summary

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