VLSI DESIGN PROJECT REPORT

TOPIC FOR DESIGN

REALIZATION OF 3:8 DECODER CIRCUIT
USING CPL LOGIC STYLE WITH RAIL TO RAIL
SWING HAVING MAXIMUM DELAY OF 1ns FOR
LOAD CAPACITANCE OF 500fF
(VLSI DESIGN COURSE - MEL G611)

Submitted bySanchit Agrawal

(2016H140106P)
Dharmendra Sharma
(2016H123145P)

Submitted toMr. Kavindra Kandpal

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Description of the design (Schematic and Simulation)

We have used 20 transistors (count also include

transistors involved in inverters).
W/L of each transistor used for pass transistor is
27u/180nm (For considering the logical effort, a
compromization in area is done for reducing the
delay).

W/L of each nmos in inverter is 420nm/180n, while

for pmos is 840nm/180nm.
Rail to rail delay for this design considering logical
effort is found out to be 0.15ns or 150ps.

Without considering the Path effort, rail to rail

delay was 0.295ns or 295ps.

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LOGICAL EFFORTIn case of CPL,

For the case of 3:8 decoder using CPL, input A, B, C are
going to a single stage only(we can see the inputs arriving at
the gate). Also the symmetry of the figure justifies the
mentioned point. So for 3:8 using CPL we will consider only
one stage.
And if we consider that the inputs are available at true and
the complimented form, than clearly, there is only one stage
and imposing the logical effort is irrelevant.
But, for considering the internal capacitances and resistance
along the path we have to multiply W/L by some factor (say
2.5) so achieve the minimum delay.
Now, considering the single stage for CPL,
Path effort = GBH
G=2 (Considering 4 inp. NAND-INV combination)

B = 1, H = 500/2 = 250 => F = 500

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For each stagef = (F)^1/N

So,
f = (500)^0.5
f = 22.36
So, we get Cin at input of 4-input AND gate asf = Cout/Cin
Cin = 500fF/22.36fF
22.36.
Now,
For inverter,
2/3fF = 420n/180n
So for 22.36fF,
We get,
W ~ 14um (L= 180nm)
For getting more reduced delay,
Taking W=27u, we can get more rail to rail swing and
nearly half delay, so optimized.
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Logical effort for Gate level implementation-

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SCHEMATIC(in white background)

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Schematic in black background

(as the labelling was not visible)

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Cell View of Decoder (Reference figure for connections)

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OUTPUT WAVEFORMS
(waveforms of d0-d7 for input 011)

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Observations from simulation.

As we have given input as 011, the fourth line is becoming high as soon
as the enable is 1.
Delay is observed to be 0.15ns ( rail to rail ) for output voltage swing of
0 to 1.30 volts.
Average Power Calculation

Waveform 1st is vdd, 2nd is current node at vdd, and third is

multiplication of 1st and 2nd .
Average power was found to be = 1.26754e-09
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LAYOUT
DescriptionTwo layouts were made.
In 1st, Layout is designed with W/L=13.5u/180n for pass
transistors and for inverters (W/L)n = 420n/180n and (W/L)p =
840n/180n.
In 2nd, Layout is designed with W/L=27u/180n for pass
transistors and for inverters (W/L)n = 420n/180n and (W/L)p =
840n/180n.
As it a large design (because of CPL), we have used two
substrate to cover the entire design.
Used a constant poly width of 180nm, and it helped in reducing
the area.
Area for layout 1 was 405(um)2.
Area for layout 2 after considering the logical effort is found out
to be 35.4umx17.94um=635(um)2

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Layout 2

Layout of 3:8 Decoder

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After the DRC check only the area and the density errors were
remaining.

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