VLSI Architecture and Design Fundamentals

.
If the declarative part in the architecture of a half adder is as below

component XOR2
port (X,Y:in BIT;z: out BIT);
end component
component AND2
port (L,M:in BIT;z:out BIT);
end component
Then what kind of architecture is it ?
behavourial
structural
dataflow
none of these
2.What is the symbol used for signal assignment?

==
=
:=
<=
3.What cannot be defined within process units?

signal
variables
constants
functions
4. Where should you define the signal clock in a process?

process declaration
list of sequential statement
sensitivity list
nowhere
5.Which of these is an valid identifier

_c1
c_10
process
1d
6.FF_PROCESS: process (CLK, CLEAR)

begin
if (CLEAR = '1') then
Q <= '0';
elsif (CLK'event and CLK = '1') then
Q <= D;
end if;
end process;
The above code is the process for which flip flop?
T-flip flop
D-flip flop
Latch
None of the above
7.Which statement is used to terminate the current loop iteration and proceed on the next
iteration
next
exit
both of these
none of these
8.Which is an invalid form of wait?

wait untill time expression
wait on signal
wait for condition
both a and c
9.How many architectures can be associated with an entity ?

only one
three
more than one
none
10.In vhdl a digital system is modeled as

module
entity
process
all of the above
What is meant by the term VLSI?

A device containing between 103 and 105 transistors.
Which 'law' describes the exponential growth of

integrated circuit complexity?
Nyquist's theorem.
Farday's law.
Lenz's law.
Moore's law.
Which of the following statements is incorrect?

Static RAM stores information by energizing or de-energising inductors.
RAM is volatile.
RAM is can be written and read quickly.
Dynamic RAM stores information by charging or discharging capacitors.

ROM devices are non-volatile.
EEPROMs can be written to (programmed) as well as read from.
EPROMs can be erased using an ultraviolet light source.
ROM devices must be programmed by the chip manufacturer.
How many address lines would be found on a 128kbyte memory device (assuming that this is
arranged as an array of 8-bit registers)?
13
15
17
19
X
Y
Z
The cells in a FPGA may contain registers, look-up

tables and memory.
True
False

Some PLDs are programmed using mechanical switches.
Some PLDs are programmed using electrically operated switches.
Some PLDs are programmed using fuses that are selectively blown.
Some PLDs are programmed using anti-fuses that are selectively joined.
Communications within a microprocessor take

place over a number of serial buses.
True
False
What implementation method would be appropriate

for an application having a complexity equivalent to
about 20 standard logic gates?
A series of standard CMOS or TTL gate devices.
A simple PLD.
A complex PLD or FPGA.
A microprocessor.
A PLC.
1) Basically, an observability of an internal circuit node is a degree to which one can

observe that node at the _______ of an integrated circuit.
a. Inputs
b. Outputs
c. Both a and b
d. None of the above
High observability indicates that ________number of cycles are required to measure the
output node value.
a. More
b. Equal
c. Less
Due to the limitations of the testers, the functional test is usually performed at speed
_______the target speed.
Lower than
b. Equal to
c. Greater than
Which among the following is/are responsible for the occurrence of 'Delay Faults'?
a. Variations in circuit delays & clock skews

b. Improper estimation of on-chip interconnect & routing delays
c. Aging effects & opens in metal lines connecting parallel transistors
d. All of the above
Which among the following serves as an input stage to most of the op-amps due to its
compatibility with IC technology?
Differential amplifier
b. Cascode amplifier
c. Operational transconductance amplifiers (OTAs)
d. Voltage operational amplifier
PSSR can be defined as the product of the ratio of change in supply voltage to change in
output voltage of op-amp caused by the change in power supply & _______ of op-amp.
Open-loop gain
b. Closed-loop gain
c. Both a and b
According to the principle of current mirror, if gate-source potentials of two identical
MOS transistors are equal, then the channel currents should be _______
Equal
b. Different
c. Both a and b
In two-stage op-amp, what is the purpose of compensation circuitry?
a. To provide high gain
b. To lower output resistance & maintain large signal swing
c. To establish proper operating point for each transistor in its quiescent state
d. To achieve stable closed-loop performance
In two-stage op-amp, what is the purpose of compensation circuitry?
a. To provide high gain
b. To lower output resistance & maintain large signal swing
c. To establish proper operating point for each transistor in its quiescent state
d. To achieve stable closed-loop performance
In accordance to the scaling technology, the total delay of the logic circuit depends on
______
a. The capacitor to be charged
b. The voltage through which capacitance must be charged
c. Available current
d. All of the above
10) In CMOS circuits, which type of power dissipation occurs due to switching of
transient current and charging & discharging of load capacitance?
a. Static dissipation
b. Dynamic dissipation
c. Both a and b
11) In high noise margin (NMH), the difference in magnitude between the maximum
HIGH output voltage of driving gate and the maximum HIGH voltage is recognized by the
_________gate.
a. Driven
b. Receiving
c. Both a and b
Answer Explanation Related Ques
12) Which factor/s play/s a crucial role in determining the speed of CMOS logic gate?
a. Load capacitance
b. Supply voltage
c. Gain factor of MOS
d. All of the above
13) The power consumption of static CMOS gates varies with the _____ of power supply
voltage.
square
b. cube
c. fourth power
d. 1/8 th power
14) In a chip, which type/s of pad design/s is/are adopted to solve the problem of pin
count?
a. Input pad design
b. Output pad design
c. Three state pad design
d. All of the above

15) Maze routing is used to determine the _______path for a single wire between a set of
points, if any path exists.
Shortest
b. Average
c. Longest
16) Maze routing is also known as ________
a. Viterbi's algorithm
b. Lee/Moore algorithm
c. Prim's algorithm
d. Quine-McCluskey algorithm
17) Which level of routing resources are supposed to be the dedicated lines allowing
output of each tile to connect directly to every input of eight surrounding tiles?
Ultra-fast local resources
b. Efficient long-line resources
c. High speed, very long-line resources
d. High performance global networks
18) In spartan-3 family architecture, which programmable functional element accepts two
18 bit binary numbers as inputs and computes the product?
a. Configurable Logic Blocks
b. Input Output Blocks
c. Block RAM
d. Multiplier Blocks
19) An antifuse element initial provides ______ between two conductors in absence of the
application of sufficient programming voltage.
a. Conduction
b. Insulation
c. Both a and b
20) Which type of CPLD packaging comprises pins on all four sides that wrap around the
edges of chip?
Plastic-Leaded Chip Carrier (PLCC)
b. Quad Flat Pack (QFP)
c. Ceramic Pin Grid Array (PGA)
d. Ball Grid Array (BGA)
21) In Gray coding, when the state machine changes state, ______ bit/s in the state vector
changes the value.
one
b. two
c. four
d. eight
22) Which UART component/s divide/s the system clock to provide the bit clock with the
period equal to one bit time and Bclock x 8?
Baud Rate Generator
b. Transmitter Section
c. Receiver Section
d. All of the above
23) If a port is declared as buffer, then which problem is generated in hierarchical design
due to mapping with port of buffer mode of other entities only?
Structural Modeling
b. Functional Modeling
c. Behavioral Modeling
d. Data Flow Modeling
24) Why is the use of mode buffer prohibited in the design process of synthesizer?
a. To avoid mixing of clock edges
b. To prevent the occurrence of glitches & metastability
c. Because critical path has preference in placement
d. Because Maximum ASIC vendors fail to support mode buffer in libraries
25) What is/are the necessity/ies of Simulation Process in VHDL?
a. Requirement to test designs before implementation & usage
b. Reduction of development time
c. Decrease the time to market
d. All of the above
26) Timing analysis is more efficient with synchronous systems whose maximum
operating frequency is evaluated by the _________path delay between consecutive flipflops.
a. shortest
b. average
c. longest
d. unpredictable
27) An Assert is ______ command.
a. Sequential
b. Concurrent
c. Both a and b
28) The 'next' statements skip the remaining statement in the ________ iteration of loop
and execution starts from first statement of next iteration of loop.
a. Previous
b. Next
c. Current (present)
29) Which among the following functions are performed by MSI category of IC
technology?
a. Gates, Op-amps
b. Microprocessor/A/D
c. Filters
d. Memory/DSP
30) Which among the following EDA tool is available for design simulation?
a. OrCAD
b. ALDEC
c. Simucad
d. VIVElogic
31) Why is multiple stuck-at fault model preferred for DUT?
a. Because single stuck-at fault model is independent of design style & technology
b. Because single stuck-at tests cover major % of multiple stuck-at faults & unmodeled physical
defects
c. Because complexity of test generation is reduced to greater extent in multiple stuck-at fault
models
d. All of the above
32) Which type/s of stuck at fault model exhibit/s the reduced complexity level of test
generation?
Single
b. Multiple
c. Both a and b
33) Stuck open (off) fault occur/s due to _________
a. An incomplete contact (open) of source to drain node
b. Large separation of drain or source diffusion from the gate
c. Both a and b

34) An ideal op-amp has ________
a. Infinite input resistance
b. Infinite differential voltage gain
c. Zero output resistance
d. All of the above
35) On the basis of an active load, which type of inverting CMOS amplifier represents low
gain with highly predictable small and large signal characteristics?
Active PMOS load inverter
b. Current source load inverter
c. Push-pull inverter
36) In MOS devices, the current at any instant of time is ______of the voltage across their
terminals.
a. constant & dependent
b. constant & independent
c. variable & dependent
d. variable & independent
37) For complex gate design in CMOS, OR function needs to be implemented by _______
connection/s of MOS.
a. Series
b. Parallel
c. Both series and parallel
38) In pull-up network, PMOS transistors of CMOS are connected in parallel with the
provision of conducting path between output node & Vdd yielding _____ output.
1
b. 0
c. Both a and b
39) In CMOS inverter, the propagation delay of a gate is the/an _________ transition
delay time for the signal during propagation from input to output especially when the
signal changes its value.
a. Highest
b. Average
c. Lowest
40) In floorplanning, which phase/s play/s a crucial role in minimizing the ASIC area and
the interconnection density?
Placement
b. Global Routing
c. Detailed Routing
d. All of the above
41) In floorplanning, placement and routing are __________ tools.
a. Front end
b. Back end
c. Both a and b
ANSWER: Back end
Explanation:
No explanation is available for this question!
42) In signal integrity, which noise/s occur/s due to impedance mismatch, stubs, vias and
other interconnection discontinuities?
a. Power/Ground Noise
b. Crosstalk Noise
c. Reflection Noise
d. All of the above

43) Simple Programmable Logic Devices (SPLDs) are also regarded as _____________.
a. Programmable Array Logic (PAL)
b. Generic Array Logic (GAL)
c. Programmable Logic Array (PLA)
d. All of the above
44) Which among the following is/are not suitable for in-system programming?
EPROM
b. EEPROM
c. Flash
d. All of the above
45) The devices which are based on fusible link or antifuse are _________time/s
programmable.
one
b. two
c. four
d. infinite
46) In SM chart for UART transmitter, which state/s indicate/s the waiting of sequential
machine for the rising edge of bit clock and the consequent clearing of low order bit of TSR
in order to transmit logic '0' for one bit time?
a. IDLE State
b. Sync State
c. Transmit_Data_State
d. All of the above
47) Which method/s is/are adopted for acquiring spike-free outputs?
a. Moore machine with clocked outputs
b. Mealy machine with clocked outputs

c. Output-state machine
d. All of the above
48) Which among the following is/are identical in Mealy & Moore machines?
a. Combinational output signal
b. Clocked Process
c. Both a and b
49) Which among the following constraint/s is/are involved in a state-machine
description?
a. State variable & clock
b. State transitions & output specifications
c. Reset condition
d. All of the above
50) If the level of fan-out is beyond a limit in synthesis, it results in an insertion of buffer
by ultimate effect of _____ the speed.
a. Enhancing
b. Reducing
c. Stabilizing

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.

If the declarative part in the architecture of a half adder is as below

2.What is the symbol used for signal assignment?

3.What cannot be defined within process units?

4. Where should you define the signal clock in a process?

5.Which of these is an valid identifier

6.FF_PROCESS: process (CLK, CLEAR)

8.Which is an invalid form of wait?

9.How many architectures can be associated with an entity ?

10.In vhdl a digital system is modeled as

all of the above

What is meant by the term VLSI?

Which 'law' describes the exponential growth of

Which of the following statements is incorrect?

Which of the following statements is incorrect?

The cells in a FPGA may contain registers, look-up

Which of the following statements is incorrect?

Communications within a microprocessor take

What implementation method would be appropriate

1) Basically, an observability of an internal circuit node is a degree to which one can

a. Variations in circuit delays & clock skews

d. All of the above

d. None of the above

d. All of the above

b. Mealy machine with clocked outputs

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