CMR Institute of Technology, Bangalore

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

Semester: 04

FUNDAMENTALS OF HDL (10EC45)

Lectures/week: 05

Course Instructor(s): Mr. Sunil Kumar K H, Pavankumar N.C

Course duration: 29 Jan., 2015 23 May 2015

Unit 1: INTRODUCTION TO HDL

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Explain the behavioural and structural description types of HDL programming, with examples and keywords
used.
Explain the following data types:
i) Physical std_logic and bit_vector in VHDL
ii) Nets, parameters and registers in verilog.
Discuss the needs of HDL. With general syntax and suitable examples, explain the shift operators of verilog.
What is synthesis and simulation? List the general steps involved. Write the syntax in VHDL and verilog for
assigning delay, declaring constant and declaring signals.
Differentiate between an entity and a symbol.
Explain the VHDL scalar data types. Compare VHDL data types with verilog data types.
If A, B and C are three unsigned variables with A = 11110000, B = 01011101 & C = 00000000, find the value
of i) A NAND B, ii) A && C, iii) ~B, iv) A ror 2, v)! B, vi) B << 1.
Mention the different styles of writing the description using HDL. Explain the switch level and mixed type
description by taking example.
Mention different styles of descriptions. Explain mixed type and mixed language description in VHDL and
verilog.
Explain signal declaration and signal assignment statements with relevant examples.
How do you assign a delay time to the signal assignment statement?
Explain the dataflow model of 2x 1 multiplexer in VHDL and verilog
Explain the use of data type vectors with dataflow description of 2 x 2 unsigned combinational array
multiplier in VHDL and verilog.
What is HDL? Why do you need it?
Explain the VHDL scalar data types. Compare the VHDL data types with verilog data types.
Describe different types of HDL Description with suitable example.
Differentiate between signal and variable assignment statement in VHDL.
Write a data flow description (in both VHDL and Verilog) for a full adder with active high enable.
Mention the types of HDL descriptions. Explain dataflow and behavioural descriptions.
Discuss different logical operators used in HDLS.
Compare VHDL and Verilog.
Describe different data types in VHDL and verilog with suitable examples and classification.
Write switch level description in verilog and VHDL for an inverter, with its circuit diagram.
Unit 2: DATA FLOW DESCRIPTIONS
Write the block diagram of a 4 bit ripple carry adder and its Boolean functions. Write dataflow description in
Verilog. Assume 4ns propagation delay for all assignment statements. Draw the simulation waveform.

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How do you assign a delay time to the signal assignment statement? Explain the dataflow model of 2x1
multiplexer in VHDL and verilog.
What do you mean by the data flow style of description? Explain its features with a suitable example.
Write a data flow description VHDL for a system that has three 1-bit inputs a(1), a(2) and a(3); and one 1-bit
output b. the least significant bit is a(1); and b is 1, only when (a(1)a(2)a(3))=1,3,6,7(in decimal). Otherwise b
is 0. Derive a minimized Boolean function of the system and write the dataflow description.
With a suitable example, explain the concept of signal declaration.
With syntax of CASE statement in VHDL and verilog, discuss its facts. Write a behavioral description of a 4bit binary counter, in verilog.
Explain with an example how the execution of the signal assignment statement takes place in HDL.
Write the truth table and derive the Boolean functions after minimization for a full adder with active low
enable i.e. if enable is low the sum and carry are the usual outputs. Then write a dataflow description using
VHDL and include a delay of 2 ns for any gate including XOR.
Obtain the Boolean expressions for a 2-bit comparator. Write the dataflow description in VHDL and verilog.
What is a vector? Give an example for VHDL and verilog vector data types
With the help of a truth table and K- maps write Boolean expression for a 2- bit magnitude comparator.
Write VHDL/verilog code.
Draw the block diagram of a 3- bit carry look ahead adder and write data flow description for its Boolean
Functions in verilog.
Unit 3: BEHAVIORAL DESCRIPTIONS
Differentiate between signal and variable assignment statement in VHDL. Write VHDL programs for
behavioural description of D-latch using signal signal assignment and variable assignment.
Write verilog description for a 4-bit priority encoder.
Explain the formats of for-loop statements in VHDL and verilog.
Write a VHDL code for D-latch using i) signal assignment statements ii) variable assignment statements.
Distinguish between these two types of statements with the help of simulation waveforms.
Explain the general format of various loop statements in HDL, with examples.
Write a verilog code to implement a 3-bit binary counter, with active high synchronous clear u 6 using case
statement.
Explain IF and CASE statements with examples
Explain Booth algorithm with a flow chart. Write VHDL or Verilog description for 4x 4- bit Booth algorithm.
Write VHDL programs for behavioural description of D-latch using signal assignment and variable
assignment.
Explain the formats of while-loop statements in VHDL and verilog.
Explain the general format of various loop statements in VHDL, with examples.
Explain the Booth algorithm. VHDL/Verilog description for 4X4 Booth algorithm.
Write a behavioural description of half adder in VHDL and Verilog with propagation delay of 5 ns. Discuss
the important features of their description in VHDL and Verilog.
Distinguish between (i) VHDL IF and VHDL case, (ii) VHDL Next and Exit, (iii) Verilog repeat and forever.
UNIT 4: STRUCTURAL DESCRIPTION
Explain the binding in the following, with example:
i) Between entity and component in VHDL
ii) Between two modules in Verilog
Write the HDL programs for N+1 bit magnitude comparator using
i) generate and generic in VHDL, ii) generate and parameters in verilog.
Write a VHDL structural description for full adder, using two half adders.

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What is the advantage of structural coding in verilog, compared to structural coding in VHDL?
Define state machine. Using the state machine concept, showing all the details, design a counter, which
counts 0, 2, 3, 5, 7. Write the VHDL code for the same.
Explain with suitable examples, how binding is achieved in the VHDL between i) Entity and Architecture ii)
Entity and Component iii) Library and Module.
Write a structural description using VHDL to implement a 2:1 multiplexer, with active low enable
Explain the use of i) Generic statement ii) Parameter iii) Generate statement.
What is Binding? Discuss the binding between library and components.
Write the HDL description of 2:1 multiplexer with active low enable in VHDL/Verilog, using structural style.
Write VHDL and Verilog program for full adder structural description.
Explain the execution of process statement.
Explain Function mapping with example.
Explain synthesis steps.
Explain the binding in the following, with example: i) Between entity and component in VHDL, ii) Between
two modules in verilog.
UNIT 5: PROCEDURES TASKS AND FUNCTIONS, ADVANCED HDL DESCRIPTIONS
Explain the use of procedure (in VHDL) and task (in verilog) with description of full adder, using half adders.
Explain the file declaration and built in procedures for file handling in VHDL.
With declaration syntax of procedure, explain its facts.
Write a verilog function to find the larger of the two signed numbers.
Give the significance of procedure, task and function. Compare them.
Write a task to multiply two signed numbers, using the Booth algorithm. Use this task to perform signed
vector multiplication, d = a * b, where a is row vector with three elements and b is a column vector with three
elements.
With declaration syntax of procedure, explain its facts.
Write a VHDL code to read a file consisting of four ASCII characters.
With declaration syntax of task, explain its facts.
Write VHDL & Verilog code to convert a fractional Binary to Real Procedures/Tasks.
Write VHDL code to convert unsigned binary vector to integer conversion using Procedure and task.
Write a code to convert the unsigned integer to (N=4) binary using procedure.
Bring out the differences between functions and procedures.
Write a VHDL description of an N bit ripple carry adder using procedure.
UNIT 6: MIXED-TYPE DESCRIPTIONS
How to attach a package to the VHDL module? Explain with example.
What is the need of mixed type description? Write description of 16x8 SRAM in VHDL and verilog.
What do you understand by a file in HDL? List out the VHDL procedures for file processing.
With syntax, explain the package and the package body.
Write VHDL code for the state diagram shown in figure.
Explain the file declaration and built in procedures for file handling in VHDL.
Write a verilog code to find the largest element of an array.
Write a vhdl code for addition of two 5X5 matrices using a package.
What is the need of mixed type descriptions? Write description of 16x8 SRAM in VHDL and verilog.
Write a VHDL code for subtraction of two 5x5matrices using package.

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Write a VHDL code for finding greatest of two 5x5matrices using package.
Explain the fetch and execute cycles of basic computer for the following operations: Halt, Add,Mult,NAND.
Write a block diagram and function table of 128x16 static memory. Write a Verilog code. Verify the code by
simulation waveform by writing data in memory locations 8,18,46,126 and read the contents of two memory
locations 18 and 46.
Write HDL code both VHDL and Verilog for finding the greatest element of an array.
Explain the implementation of single dimensional and two dimensional arrays in VHDL.
UNIT 7: MIXED LANGUAGE DESCRIPTIONS
How to invoke a VHDL entity from a verilog module? Explain with example.
Write a mixed language description of Full adder, explain the invoking of VHDL entity from averilog
module
Describe all file processing tasks in Verilog. What is the necessity of Mixed-type description?
Describe the development of HDL code for VHDL code for an ALU.
Assume the following operations - Addition, Multiplication, Division, No operation. How to invoke a VHDL
entity from a Verilog module.
Explain mixed language description of a JK Flip Flop with a clear pin and write the simulation waveform.
Write a mixed language description of a 9 bit adder consisting of three 3 bit carry look ahead adders to show
how a verilog module invokes VHDL entity.
What are the facts and limitations of mixed language description?
Write a mixed language description of a 3-bit adder with zero flag. If the output of the adder is zero, the zero
flag is set to 1;otherwise it is set to 0.
Write mixed language description of Master Slave D flip flop by invoking VHDL entity from verilog module.
Describe full adder using 2 half adders invoking verilog module from VHDL entity.
Write a mixed language description of an NAND gate invoking a Verilog module from a VHDL entity.
Write a mixed language description of an OR gate invoking a Verilog module from a VHDL entity.
Write a mixed language description of an JK flipflop invoking a Verilog module from a VHDL entity.
Discuss the differences between mixed language descriptions and mixed type descriptions.
UNIT8: SYNTHESIS BASICS
Write a flow diagram of synthesis. Explain its steps.
Write VHDL code for signal assignment statement y = 2*x + 3. Show the synthesized logic symbol and gate
level diagram. Write structural code in verilog using the gate level diagram.
Describe synthesis information extraction from entity and module with examples.
Explain mapping the signal assignment and variable assignment statements to Gate-level with suitable
examples.
What is Synthesis?

Give synthesis information extracted, when the input and output are defined as: i) bit ii) Std_logic_vector.
Write a behavioral code in VHDL and Verilog for the signal assignment statement Y=X. Explain the mapping
to gate level logic diagram.
With an example, explain the mapping the function statement in HDL.
Discuss some important facts related to synthesis basics.
With an example, explain mapping if, if-else, case statements in HDL. Show the synthesized logic symbol and
gate level diagram.
Draw the gate level synthesis information, extracted from the following verilog code.
always@(s,a,b)
begin

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if(s==1b1)
Y=b;
else
Y=a;
end.
Find the gate level mapping for the following verilog code:
Module if_st(a,y)
Input[2:0]a;
Output y;
Reg y;
always@(a)
begin
if(a<3b101)
y= 1b1;
else
y= 1b0;
end
end module.
Design the gate level synthesis and write VHDL description for the information given below:
INPUTS
OUTPUT
a
b
Z
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0-7
z=b
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0-7
Z=b+4
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0-7
Z=b/2
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XX
Z=15
XX
8-15
Z=15
Write a behavioral code in VHDL and Verilog for the signal assignment statement Y=2X. Explain the
mapping to a gate level diagram.