Web Site
https://canvas.stanford.edu/courses/55784
Time:
Location:
Hewlett 102
Credit:
Instructors:
Course Assistant:
Ching-Ying Lu (lu18@stanford.edu)
Office Hours:
Textbooks
Grading
30% Homework*
30% Midterm
40% Final
* Homework is due at Thursdays lecture or at the latest, at 5:00 pm Thursday outside
Allen 329X. No late homeworks are accepted, but your lowest score will be dropped.
Stanford EE 216 Winter 2017
Tentative Schedule
Jan 10:
Introduction
Semiconductors in equilibrium
Semiconductors in non-equilibrium
Feb 7:
Feb 9, Feb. 14
Metal-semiconductor contacts
MOSFET
March 20:
By Kilby,
Nobel Laureate in Physics 2000
and
Robert Noyce
1958
(http://www.bellsystemmemorial.com/belllabs_transistor.html)
(Courtesy of TI and Huff, SEMATECH)
Stanford EE 216 Winter 2017
Chemistry
Material Science
Electrical Engineering
Applied Physics
Mechanical Engineering
Diode: Applications ?
10
HBT: Applications ?
11
Ig
Vg
= VI
g V
I
VT
Vg
Vg
V
12
qV
Gate at Vg
qVb
0
Source
Collector
Distance
- qV
b
# carriers escaping over barrier per unit time x q = I = I0 exp(
)
kT
(approximate)
Stanford EE 216 Winter 2017
13
At best, a change in gate voltage DVg will bring about a change in barrier height
DVb = DVg
In which case
DI
DVg
-qVb
q
q
= g m = - kT I0 exp( kT ) = - kT I
14
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CO
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11
keys to the electronics REVOLUTION
by P
220
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dd
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15
Moores Law
The Chips are Down for Moores Law, Nature 530, 144147 (11 February 2016)
Stanford EE 216 Winter 2017
16
The Chips are Down for Moores Law, Nature 530, 144147 (11 February 2016)
Stanford EE 216 Winter 2017
17
18
2x every 4 years
1000
cost of a modern
wafer fab
100
($ million)
2x every 3 years
10
1960
1970
1980
1990
2000
We need to understand how the devices function to ensure proper performance, reliability
and economic implications. For many generations, scaling was relatively straightforward.
Today, it also involves new materials and increased complexity, greatly increasing cost.
19
EUV Lithography
20
Technology Transitions
The first transistor was a bipolar transistor, as were the first ICs
Initial MOS only had incremental advantages over bipolar until CMOS
III-V technology is largely optoelectronics--a complement to CMOS
Is there anything beyond CMOS?
21
Why Silicon?
Limitations of Si
o
o
22
+4 Elements
+45 Elements
11 Elements
23
Electronics
Si/SiO2/PolySi
Si/SiO2/PolySi
Si/SiO2/PolySi
Si/SiO2/PolySi
Si/SiO2/PolySi
Photonics
24
25
Cross-section
Single transistor
Full wafer (100s of dies)
modern wafers: 300-450 mm
diameter (12-18 inches)
26
27
Pitch
Half-pitch
Contact
LC
Source
Channel
Channel
Thickness
Drain
Gate LG
28
Half-pitch
Contact
today
100
LC
Source
Gate LG
Channel
Channel
Thickness
Drain
LG + LC scaling?
20 nm
10
90 65 45 32 22 16 10 7
5
Tech. Node (nm) LG
Stanford EE 216 Winter 2017
2D materials like
MoS2, WTe2, ZrSe2
carbon
nanotubes (1D)
Stanford EE 216 Winter 2017
<1 nm
Profs. E. Pop and R. T. Howe
30
31
Technology Transitions
Transistors areBeyond
getting very
small ...
CMOS
100 m
conventional devices work
well in classical region
10 m
1 m
0.1 m
transition region
0.01 m
quantum devices
0.001 m
atomic dimensions
1960
1980
2000
2020
2040
32
Communications Challenge
Broadway, New York City, 1887
33
34
35
Direct-write lithography
engine based on 8192 grating
light valve on CMOS
Silicon Light Machines
Profs. E. Pop and R. T. Howe
Nano-CMOS Deficiences
A nano electromechanical switch has several
advantages compared with nanoscale CMOS
transistors:
very high on current
zero leakage
infinite subthreshold slope
high temperature operation
radiation-hard operation
compatible with other substrates glass, plastics
37
The NEMFET
Nano-electromechanical gate
(anchors not shown)
Accumulation-mode design:
> 105 X less gate leakage
p+
Source
n+
n+
Work-function difference:
gate down with Vg = 0V.
Buried Oxide
Si Substrate
H. Kam, D. T. Lee, T.-J. King, and R. T. Howe
IEEE Int. Electron Devices Meeting, Dec. 2005
H. Kam, IEDM 2009 demonstrated!
Stanford EE 216 Winter 2017
38
crystalline silicon
solar cells
39
40