College Of Engineering

Department of Electrical And Computer

Engineering
ECE 2613 Digital Circuit Design Fall 16
Section 002

Submitted By: Muhotasim Ahmed

TUiD: 915445427

Lab 12: Integrating Register Memory with an

Arithmetic Logic Unit
Abstract
This experiment is about integrating a 2-read 1-write random access
memory with an Arithmetic Logic Unit (ALU) to mimic the behavior
of a processor with very basic primitive set of operations.

Introduction
We shall be expanding upon the work done in a previous lab, lab 11.
There we designed a basic three port memory, where we controlled
basic read write functionality and entered input data and addressed
different parts of the memory using the switches and push buttons.
In this lab, using the ALU functionality, we will be able to perform
basic arithmetic operations on the data stored in the different
memory addresses, and thus update them.

Procedure
The top module alu_lab paired up the main module, alu_regs with
a button debounce module called btn_debounce. It used modules
from previous labs to debounce the push button signals.
The alu_regs is the module where the main work happened. It was
formed by renaming and then adding additional combinational logic
and the alu module to the memory_lab module. The alu module
used basic case statements that takes input from a 2-bit control
signal to select either of four arithmetic operations, add, subtract,
increment or decrement.
In order to explain the workings of alu_reg more fully, it is
convenient to refer to its block diagram.

Fig: Block diagram of alu_regs

This is a modified version of memory_module from lab 11, and the
modifications are marked in red. The modifications are to
accommodate the ALU and its operations in the design.
We can see that the w_wr signal is now controlled by an OR
operation between sw[3] and sw[7], which as before is ANDed
with m_write signal. The sw[3] signal basically turns on the
multiplexer that is on the output of the ALU. This enables the ALU to
perform a write operation. So in short, sw[3] enables the ALU to
update (write) the data on an address with a selected arithmetic
operation. The arithmetic operation to be performed can be selected
using the alu_sel signal, which receives inputs from two push
buttons in the board.
The rest of the function is identical to lab11, which are basically the
read write operations we could perform via the two read and one
write ports.
The operations are summarized in the table below.

Table 1: Modes of operation of alu_reg

Results

Fig: Simulation Results

The above signals were produced upon simulating the design. The
signal at the very bottom is sel. This signal is composed of two bits,
{sw[7], sw[3]}. The Boolean value of (sel== 2b01) is a control
signal of the multiplexer on the output of the ALU, which enables it
to write on the memory. When it is high, the ALU can write on the
address w_addr, and update the data w_data.
We can see on the timing diagram that sel is 2b01 at the end. At
that moment, the ALU is activated. Lets see whether the ALU is
working. The alu_sel signal selects either of the four arithmetic
operations that the ALU can perform on the data stored in any two
selected address.
When alu_sel is 2b00, the ALU is adding. We see that the data on
rp_data is hexadecimal f. The data on rq_data is initially
hexadecimal 7. These two data are to be added. We see that the
value on w_data is 6, which is the result of adding 6 to f (the value
cycles back). In the next clock cycle, the data is written on rq_data.
Thus the addition was performed. The design works.
Upon implementation of the design in hardware, it was indeed seen
that the design works. We were able to read data simultaneously
from two address ports, write data on different memory addresses,
and then add, subtract, increment or decrement any two data
values and see the result updated in the two read ports of the
memory.

Conclusion

In this lab we got to see how a basic processor performs basic

arithmetic operations on different data stored in different addresses
in its memory. It was a great learning experience, where we
appreciated the beauty behind the design and function of a
processor.