QSOCS

UVM Based
Verification Of
AXI-TO-AHB Bridge

QSOCs

AXI TO AHB BRIDGE

CONTENTS
INTRODUCTION ................................................................................................................... 2

1.

1.1

AMBA AXI (Advanced eXtensible Interface) ................................................................... 3

1.2

Advanced High-performance Bus (AHB) ......................................................................... 4

2.

AXI TO AHB BRIDGE .......................................................................................................... 5

2.1

AXI TO AHB BRIDGE Micro Architecture............................................................................. 6

2.2

Features and Limitations of the Bridge ............................................................................. 8

3.

TEST BENCH ARCHITECTURE.......................................................................................... 9

5.

STIMULUS DRIVING FROM AXI MASTER .................................................................... 11

6.

STIMULUS DRIVING FROM AHB SLAVE.................................................................................. 12

8.

Functional Coverage ............................................................................................................... 17

9.

STRUCTURE FOR AXI TO AHB BRIDGE PROJECT .................................................................... 20

Page | 1

QSOCs

AXI TO AHB BRIDGE

1. INTRODUCTION
Integrated circuits has entered the era of System -on-a-Chip (SoC), which refers to
integrating all components of a computer or other electronic system into a single
chip. It may contain digital, analog, mixed-signal, and often radio -frequency
functions all on a single chip substrate. With the increasing design size, IP is an
inevitable choice for SoC design. And the widespread use of all kinds of IPs has
changed the nature of the design flow, making On-Chip Buses (OCB) essential to
the design. Of all OCBs existing in the market, the Advanced Microcontroller Bus
Architecture (AMBA) bus system is widely used as the de facto standard SoC bus.
It facilitates development of multi-processor designs with large numbers of controllers
and peripherals. Since its inception, the scope of AMBA has, despite its name, gone far
beyond micro controller devices. Today, AMBA is widely used on a range of ASIC and
SoC parts including applications processors used in modern portable mobile devices like
smartphones. AMBA was introduced by ARM in 1996. The first AMBA buses were
Advanced System Bus (ASB) and Advanced Peripheral Bus. It is very commonly used
bus architecture.
In order to support high-speed pipelined data transfers, AMBA 4.0 supports a rich set of
bus signals, making the analysis of AMBA-based embedded systems a challenging
Proposition.
The goal of this project is to verify a AXI to AHB bridge. The bridge provides interface
between the high performance AXI and high bandwidth peripherals of AHB domain. The
AMBA (Advanced Microcontroller Bus Architecture) AXI (Advanced eXtensible
Interface) to AHB-Lite (Advanced High Performance Bus) Bridge translates AXI4
transactions into AHB-Lite transactions. It has a slave interface which receives the AXI4
master transactions and converts them to AHB master transactions and initiates them on
the AHB bus.

Page | 2

QSOCs

1.1

AXI TO AHB BRIDGE

AMBA AXI (Advanced eXtensible Interface)

The AMBA AXI protocol is targeted at high-performance, high-frequency system

designs and includes a number of features that make it suitable for high-speed submicron
interconnects.
The key features of the AXI protocol are:
Separate address/control and data phases
Support for unaligned data transfers using byte strobes
Burst-based transactions with only start address issued
separate read and write data channels to enable low-cost Direct Memory Access
(DMA)
Ability to issue multiple outstanding addresses
Out-of-order transaction completion
Easy addition of register stages to provide timing closure.
As well as the data transfer protocol, the AXI protocol includes optional extensions that
cover signaling for low-power operation.
The AXI protocol is burst-based. Every transaction has address and control information
on the address channel that describes the nature of the data to be transferred. The data is
transferred between master and slave using 5 channels including Write Address Channel,
Write Data Channel, Write Response Channel, Read Address Channel, Read Data
Channel (Write data channel to the slave or a read data channel to the master).In write
transactions, in which all the data flows from the master to the slave, the AXI protocol
has an additional write response channel to allow the slave to signal to the master the
completion of the write transaction.

Page | 3

QSOCs

AXI TO AHB BRIDGE

1.2

Advanced High-performance Bus (AHB)

AMBA AHB-Lite addresses the requirements of high-performance synthesizable designs.

It is a bus interface that supports a single bus master and provides high-bandwidth
operation. AHB has address and data phase. Pipelining is done by the overlapping both
the phases.
AHB-Lite implements the features required for high-performance, high clock frequency
systems including:
burst transfers
Single-clock edge operation
Non-tristate implementation
Wide data bus configurations, 64, 128, 256, 512, and 1024 bits.
It is highly pipelined. The most common AHB-Lite slaves are internal memory devices,
external memory interfaces, and high bandwidth peripherals. Although low-bandwidth
peripherals can be
Included as AHB-Lite slaves, for system performance reasons they typically reside on the
AMBA Advanced Peripheral Bus (APB). Bridging between this higher level of bus and
APB is done using a AHB-Lite slave, known as an APB bridge

Page | 4

QSOCs

AXI TO AHB BRIDGE

2. AXI TO AHB BRIDGE

The AMBA (Advanced Microcontroller Bus Architecture) AXI (Advanced eXtensible
Interface) to AHB-Lite (Advanced High Performance Bus) Bridge translates AXI4
transactions into AHB-Lite transactions. It has a slave interface which receives the AXI4
master transactions and converts them to AHB master transactions and initiates them on
the AHB bus.
AXI has five channels such as write address channel, Write data channel, write response
channel, Read address channel and Read data channel. AXI clock is Operating
independent of AHB clock. AXI to AHB converts AXI read and write transactions to
corresponding AHB read and write transactions. This bridge provides an interface
between high performance AXI processors and high bandwidth peripherals of AHB
protocol like memory controller, DMA controller, and Touchpad, SD card.
AXI uses hand shake mechanism for data transfer in all the five channels. The VALID
signal is asserted from master when valid address or control and data information is
available. The READY signal is asserted from slave when it can accept address or control
and data information. The AHB Bridge buffers address, control and data from AXI4
drives the AHB peripherals and returns data and response signal to the AXI4. It decodes
the address using an internal address map to select the peripheral. The bridge is designed
to operate when the AHB and AXI4-Lite have independent clock frequency and phase.
For every AXI channel, invalid commands are not forwarded and an error response
generated. That is once a peripheral accessed does not exist, the AHB Bridge will
generate DECERR as response through the response channel (read or write). And if the
target peripheral exists, but asserts ERR, it will give a SLVERR response.
The DUT used to verify in this project is LogiCORE IP AXI to AHB-Lite Bridge
(v1.00a) from Xilinx.

Page | 5

QSOCs

2.1

AXI TO AHB BRIDGE

AXI TO AHB BRIDGE Micro Architecture

Protocols Using: AXI4, AHB Lite (with Data Width 32/64)

AXI SLAVE

AXI

AXI WRITE
STATE
MACHINE

AXI READ
STATE
MACHINE

AHB Lite
Master

AHB
STATE
MACHINE
AHB

TIME OUT
MODULE

AXI TO AHB BRIDGE

1. AXI4 Slave Interface

The AXI4 slave interface module provides a bidirectional slave interface. The AXI4
address width can be configured from 32 to 64 bits. The AXI4 data bus width can either
be 32 or 64. The AXI4 to AHB-Lite Bridge supports the same data width on both the
AXI4 and AHB-Lite interfaces. When both write and read transfers are simultaneously
Page | 6

QSOCs

AXI TO AHB BRIDGE

requested on the AXI4 interface, the read request is given a higher priority than the write
request.
2. AXI4 Write State Machine
The AXI4 write state machine is part of the AXI4 slave interface module and functions
on AXI4 write channels. This module controls AXI4 write accesses and generates the
write response. If a bridge timeout occurs, this module completes the AXI4 write
transaction with a SLVERR response.
3. AXI4 Read State Machine
The AXI4 read state machine is part of the AXI4 slave interface module and functions
on AXI4 read channels. This module controls the AXI4 read accesses and generates the
read response. If a bridge timeout occurs, this module completes the AXI4 read
transaction with a SLVERR response.
4. AHB-Lite Master Interface
The AHB-Lite master interface module provides the AHB-Lite master interface. The
AHB-Lite address width can be configured in the Vivado IDE from values 32 to 64 bits
and the data bus width can either be 32 or 64 bits. The AXI4 to AHB-Lite Bridge
supports the same data width on both the AXI4 and AHB-Lite interfaces.
5. AHB State Machine
The AHB state machine is part of the AHB-Lite master interface module. When the
AXI4 interface initiates a write access, the AHB state machine module receives the
control signals and data from AXI4 slave interface, then transfers the same to the
equivalent AHB-Lite write access. This module also transfers the AHB-Lite write
response to the AXI4 slave interface. When the AXI4 interface initiates a read access, the
AHB state machine module receives the control signals from AXI4 slave interface, then
transfers the same to the equivalent AHB-Lite read access. This module also transfers
AHB-Lite read data and read response to the AXI4 slave interface.
6. Timeout Module
The timeout module generates the timeout when the AHB-Lite slave is not responding to
the AHB transaction. This is parameterized and generates the timeout only when that
parameter value is non-zero. If AHB-Lite slave is not responding, timeout module waits
on the number of AXI4 clocks specified through the timeout parameter for the AHB-Lite
slave response and then generates the timeout.

Page | 7

QSOCs

2.2

AXI TO AHB BRIDGE

Features and Limitations of the Bridge

The Xilinx AXI to AHB-Lite Bridge is a soft IP core with the following features:
AXI4 Slave Interface:
AXI interface is based on the AXI4 specification
Supports 1:1 (AXI to AHB) synchronous clock ratio
Connects as a 32/64-bit slave on 32/64-bit AXI4
Supports incrementing burst transfers (of length 1 to 256)
Supports wrapping burst transfers of length 2, 4, 8, and 16
Supports fixed burst transfers (of length 1 to 16)
Supports narrow transfers (8/16-bit transfers on a 32-bit bus and 8/16/32-bit
transfer on a 64-bit data bus)
Supports limited cache encoding and limited protection unit support
Supports address/data phase time out AHB-Lite Master Interface.
AHB-Lite Master Interface:
Supports AHB-Lite interface
Connects as a 32/64-bit Master on 32/64-bit AHB-Lite
Supports single burst transfers
Supports wrapping burst transfers of length 4, 8 and 16 and undefined burst length
AHB-Lite master does not issue incrementing burst transfers that cross 1 kB
address boundaries
Supports limited protection control
Supports narrow transfers (8/16-bit transfers on a 32-bit data bus and 8/16/32-bit
transfers on a 64-bit data bus)
Not Supported Features/Limitations
AXI4 Slave Interface
Data bus widths greater than 64 are not supported
No registers are implemented because posted writes are not supported
Locked, Barrier, trust zone, and exclusive operations are not supported
Out-of-order read transaction completion
Out-of-order write transaction completion
Unaligned/Sparse transfers (holes in strobes) are not supported
EXOKAY and DECERR responses to AXI4 are not supported
Low-power state is not supported
Secure accesses are not supported
AHB-Lite Master interface
Data bus widths greater than 64 are not supported
No cacheable access support

Page | 8

QSOCs

AXI TO AHB BRIDGE

3. TEST BENCH ARCHITECTURE

axi_ahb_top

axi_ahb_test
Sequence item

axi_sequence
Ahb_Sequence
env
Axi
intf

SQR
SQR
S
C
O
R
E
B
O
A
R
D

Driver
Monitor
monitor

DUT

ahb_agent
AXI
intf
driver
Driver

SQR

Monitor
monitor
axi_agent

axi_seq_item

ahb_sequence
Axi_sequence

Testbench Architecture

Page | 9

AXI TO AHB
BRIDGE

QSOCs

AXI TO AHB BRIDGE

1.) Axi to Ahb Bridge -DUT

The bridge translates AXI4 transactions into AHB lite transactions. Data Bus may
be 32 or 64. Here we are using Xilinx AXI to AHB-Lite Bridge.
2.) Axi_seq_item/ Ahb_seq_item
Is the basic building block for Stimulus generation and Coverage (can be data,
address, delay, constraints, etc), provides lowest level transaction and can be
combined into a sequence. Describes the transaction level items for the Stimulus
Driving. For AXI part it has size, address data like items. We are finding the Length
of transaction from the given data size, starting address and the size of the transfer
For AHB part we have properties like data and address for AHB transactions.
3.) AXI /AHB Sequence
Builds transaction from sequence items, builds higher level transaction from
sequences and coordinates execution of its items/sub-items.
4. Axi /Ahb Sequencer
It selects multiple sequences and serves as an arbiter for controlling transaction flow
of UVM. It uses TLM port for connection (Sequencer Driver) and handshake
(Sequencer Driver) during communication.
4.) Axi/Ahb Driver
It drives the stimulus on to the DUT interface. Requests sequence items from
sequencer and drives sequence items into interface. When operating on RTL model
interface, converts transactions level to signal level and has a virtual interface to
connect to DUT interface
5.) Axi/Ahb Monitor
Gets transactions from collector or TLM interface, provides coverage, checking and
makes transactions available for consumption. It samples the DUT interface and
captures the information there in transactions that are sent out to the scoreboard and
functional coverage monitors for further analysis.
6.) Axi/Ahb Agents
For Axi to Ahb Bridge, we have two different signal interfaces, each of which have
their own protocol. The UVM agent collects together a group of uvm_components
focused around a specific pin-level interface. The purpose of the agent is to provide
a verification component which allows users to generate and monitor pin level
transactions.
7.) Scoreboard
It compares the data coming from axi and ahb interface. Receives transactions from
interface UVCs and checks transactions for expected device behavior. It is likely to
include an abstract reference model and is located inside module UVC.
8.) Environment
The environment, or env, is a container component for grouping together subcomponents orientated around a block, or around a collection of blocks at higher
levels of integration.
Page | 10

QSOCs

AXI TO AHB BRIDGE

5. STIMULUS DRIVING FROM AXI MASTER

Write
Sequence

Write Address
Queue

Write Data
Queue
Read
Sequence

Driving
Logic
Read Address
Queue

Matching Queue
ID of Requests

RESPONSE
HANDLER

AXI SEQUENCE

Write Address
Response
Queue
Write Data
Response
Queue

Stimulus Driving Logic For AXI Master

Page | 11

AXI DRIVER

AXI Interface

QSOCs

AXI TO AHB BRIDGE

6. STIMULUS DRIVING FROM AHB SLAVE

A
H
B

DUT
AHB_DRIVER

S
E

Ahb_Interface

Q
U

AXI To AHB
Bridge

E
N
C
MEMORY

Page | 12

QSOCs

AXI TO AHB BRIDGE

7. AXI TO AHB BRIDGE TEST PLAN

AXI TO AHB BRIDGE TEST PLAN

DUT: AXI to AHB BRIDGE

SL
NO

TEST CASE

DESCRIPTION

FEATURE

STATUS

PASS/FAIL

BASIC TRANSACTIONS

1 reset_check

2 basic_write_transaction

3 basic_read_transaction

4 multiple_read_write

4 fixed_burst_single_beat

multiple_fixed_
5
burst_varying_length
Page | 13

Checking the
functionality of
DUT when it is
in reset condition
by randomly
driving data to
all the inputs

During reset condition the

ouputs of DUT will be some
pre-configured value even if
we toggle the values to the
inputs

Writing to DUT
with a basic
write transfer of
single beat and
size as 4

Driving data and control

information through 2
different channel to a
peripheral and getting
response from another
channel through flow
control signals READY and
VALID

Completed PASS

Writing to DUT
Reading data from a
with a basic
peripheral using two
Read transfer of
different channels using
single beat and
flow control mechanisms
size as 4
Randomly
driving basic
any number of transactions
read and write
is possible in AXI to AHB
transfers for
bridge
multiple times
BURST TRANSACTIONS
Driving data as a
burst with single
beat

Completed PASS

Completed PASS

Completed PASS

Data is written to a fixed or

fifo type memory

Repeated driving
of data as fixed
AXI4 protocol supports
burst with
maximum beats of 256
varying length

Completed PASS

Completed PASS

QSOCs

6 INCR_burst_single_beat

7 INCR_length_check

8 INCR_burst_length_2

9 INCR_burst_length_4

10 INCR_burst_length_8

11 INCR_burst_length_16

12 WRAP_length_check

13 WRAP_burst_length_2

14 WRAP_burst_length_4

15 WRAP_burst_length_8

16 WRAP_burst_length_16

Page | 14

AXI TO AHB BRIDGE

Driving data as
burst of INCR
with length as 1

Data is written as a burst by

giving start address
only.Then address is
incremented w.r.t INCR
parameters

Driving data as
burst of INCR
with varying
Length

AXI4 protocol supports

maximum beats of 256

Driving data as
burst of INCR
with length as 2

AXI to AHB bridge maps

INCR burst with length 2 as
INCR2 in AHB side

Driving data as
burst of INCR
with length as 4

AXI to AHB bridge maps

INCR burst with length 4 as
INCR4 in AHB side

Driving data as
burst of INCR
with length as 8

AXI to AHB bridge maps

INCR burst with length 8 as
INCR8 in AHB side

Driving data as
burst of INCR
with length as 16

AXI to AHB bridge maps

INCR burst with length 16
as INCR16 in AHB side

Driving Data as
a WRAP with
varying Length

There is only of wrap 2,4,8

and 16.All others may throw
an error

Driving data as
burst of WRAP
with length as 2

AXI to AHB bridge maps

WRAP burst with length 2
as WRAP2 in AHB side

Driving data as
burst of WRAP
with length as 4

AXI to AHB bridge maps

WRAP burst with length 4
as WRAP4 in AHB side

Driving data as
burst of with
length as 8

AXI to AHB bridge maps

INCR burst with length 8 as
WRAP8 in AHB side

Driving data as
burst of INCR
with length as 16

AXI to AHB bridge maps

INCR burst with length 2 as
WRAP16 in AHB side

Completed PASS

Completed PASS

Completed PASS

Completed PASS

Completed PASS

Completed PASS

Completed PASS

Completed PASS

Completed PASS

Completed PASS

Completed PASS

QSOCs

AXI TO AHB BRIDGE

Driving random
bursts with
17 burst_beat_size_with_aligned_addr
aligned address
and varying size

AHB protocol supports

aligned transfers only
Completed PASS

UNALIGNED TRANSACTIONS

18 FIXED_unaligned_address

19 INCR_unaligned_address

20 WRAP_unaligned_address

Driving data as a
FIXED burst
with unaligned
address with
different size and
lengths
Driving data as a
INCR burst with
unaligned
address with
different size and
lengths
Driving data as a
WRAP burst
with unaligned
address with
different size and
lengths

DUT converts unaligned

transfers into aligned
address using STROBE
signals.AXI supports
unaligned address,but AHB
not
DUT converts unaligned
transfers into aligned
address using STROBE
signals.AXI supports
unaligned address,but AHB
not
DUT converts unaligned
transfers into aligned
address using STROBE
signals.AXI supports
unaligned address,but AHB
not

ATOMIC ACCESS & OTHER FEATURES

21 protection_check

22 exclusive_access

23 locked_access

Page | 15

Driving random
bursts with
different levels
of Protection
Checking of
Exclusive access
of AXI by using
LOCK signal by
driving random
bursts
Checking of
Locked access
of AXI by using
LOCK signal by
driving random
bursts

AXI protocol supports

NORMAL,PRIVILEGED
and SECURE access.But
DUT doesn't support all the
features.
AXI4 supports
LOCKED,NORMAL and
EXCLUSIVE access to the
slave.But DUT and AHB
doesn't support
AXI4 supports
LOCKED,NORMAL and
EXCLUSIVE access to the
slave.But DUT and AHB
doesn't support

Completed

Completed

Completed

QSOCs

AXI TO AHB BRIDGE

24 normal_access

Checking of
Normal access
of AXI by using
LOCK signal by
driving random
bursts

AXI4 supports
LOCKED,NORMAL and
EXCLUSIVE access to the
slave.But DUT and AHB
doesn't support

25 cache_support_check

Checking the
cache unit of
AXI

Bridge supports only limited

features of Cache

26 out_of_order_txn

Checking out of
Order
Transaction

Bridge doesn't support out

of order transaction.it helps
finishing transfers from fast
devices reather than slower.

27 outsatnding_address_check

Checking
outstanding
addresses
transactions

AXI supports outstanding

address transactions,but
AHB doesn't.

Driving random
burst with out of
boundary
conditions

AXI supports 4KB locations

and AHB supports 1KB
locations

28 data_interleaving_Check

29 boundary_cross_check

ERROR RESPONSES

30 error_response_check

Cheecking for
different errors
responses
associated
withAXI to AHB
bridge

AXI having
OKAY,EXOKAY,DECERR
and AHB having OKAY
and ERROR.

CORNER CASES

31 same_id_check

Page | 16

Giving Same Id's

to different
address for a
transaction

QSOCs

AXI TO AHB BRIDGE

8. Functional Coverage

Functional Coverage
Sl
No
1
2

Cover
group

Cover Point
Access

Description
Write
Read

Fixed

It is writing to the same

address .DUT converts
unaligned transfers into
aligned address using
STROBE signals.AXI
supports unaligned
address,but AHB does
not

Increment

DUT converts unaligned

transfers into aligned
address using STROBE
signals.AXI supports
unaligned address,but
AHB not

Wrap

Here the address will

wrap after the address
boundary(Here its 4)

6
7
8
9
10
11
12
13
14

Protect_NSD
Protect_PSD
Protect_NND
Protect_NSI
Protect_PSI
Protect_NNI
Protect_PNI
Protect_PNI
Cache

Burst
4

CG-AXI

Protect

Cache

15
16
17
18
Page | 17

Okay
Response

EXOKAY
SLVERR
DECERR

Cache

Status

Hit/Fail

QSOCs

19
20
21

AXI TO AHB BRIDGE

Address_type

Addr_align

23

Addr_unalign
0-1000
Divisible by 4
This will transfer single
Single
transfer i,e single beat
Increment

24

Undefined

25

INCR4

26

INCR 8

Address

22

27

Burst

INCR 16

Undefined length burst

that has burst of length
one
The previous address is
increments by 4
The previous address increments
by 8
The previous address is
incremented by 16
Here to single address
the data is written

28
29

Wrap

30

Wrap 4

The address will incrent

with 4 wrap to boundary

31

Wrap 8

The address will

increment by 8 and wrap
to the boundary

32

Wrap 16

The address will

increment by 16 and
wrap to the boundary

33

Idle

Undefined length burst

that has burst of length
one

Busy

Burst is taking place but

transfer cannot take
place immediately ,
Undefined length can
have busy as last
transition

Non
Sequential

It is single or first transfer

of the burst . Single
transfer on the bus are
treated as burst of length
one

34

35

Page | 18

Transaction
Type

QSOCs

AXI TO AHB BRIDGE

36

Sequential

37
38
39
40
41

Byte
Half_word
Word
Double Word

42

Page | 19

Size

If its sequencial address

is related to the previous
transfer , The control
information is same as
previous transfer
When size is byte
When size is half_byte

Address
1000 to 2000

Address lying between 1k

and 2k

QSOCs

AXI TO AHB BRIDGE

9. STRUCTURE FOR AXI TO AHB BRIDGE PROJECT

AXI_TO
AHB Bridge

doc

script

sim

src

testlib

verif

agent

env

Directory Structure

Doc : Keep all the related documents in this file

Script : Keep all the Scripting file like run_test ,regression files
Sim : All the simulations has to done here
Src : keep all the source rtl file in this directory
Testlib : it having all the sequence items,sequences,test files for
verification
Verif :Includes three sub directories agent, env and intf
Intf :Keep all the interface files in here
Env: it consist environment, top, scoreboard and packages.
Agent : it consists sequencer, driver monitor related files

Page | 20

intf

QSOCs

AXI TO AHB BRIDGE

10. References
1. ARM AMBA AXI4-Stream Protocol Specification
www.infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ihi0051a/index.
html
2. UVM User Guide manual
3. www.verificationacademy.com

Page | 21