National Institute of Technology, Delhi

Project Report

Bus Arbiter using FSM and ASM Approach

Submitted to:
Mr. Naman Joshi
Assistant Professor

Submitted by:

Submitted by:

Rohit Tayal

Faiqa Hamdani

141200048

141200049

Abstract
Arbiters are electronic devices that allocate access to shared resources. Arbiters are used in
digital systems to arbitrate requests for shared resources. For example, if n units share a bus
that only one can use at a time, an n-input arbiter is used to determine which gets access to
the bus in a given cycle. An arbiter can be constructed as an iterative circuit. That is, we can
design the logic for one bit of the arbiter and repeat it.
This project focuses on the algorithm of Bus Arbiter using Finite State Machine (FSM) and
Algorithmic State Machine (ASM) methods.

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Index
Title
1.

2.
3.

Page No

Bus Arbiter
1.1. Asynchronous Arbiter
1.2. Synchronous Arbiter
Algorithmic state machine(ASM)
2.1. ASM Chart
Finite state machine(FSM)
3.1. FSM Code
3.2. RTL Schematic
3.3. Output

3
4
4
5
6
7
7
9
9

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Bus Arbiter
An Arbiter is like a traffic officer at an intersection who decides which car may pass
through next. Given only one request, an Arbiter promptly permits the corresponding action,
delaying any second request until the first action is completed. When an Arbiter gets two
requests at once, it must decide which request to grant first. For example, when two
processors request access to a shared memory at approximately the same time, the Arbiter
puts the requests into one order or the other, granting access to only one processor at a time.
The Arbiter guarantees that there are never two actions under way at once, just as the traffic
officer prevents accidents by ensuring that there are never two cars passing through the
intersection on a collision course.
Although Arbiter circuits never grant more than one request at a time, there is no way
to build an Arbiter that will always reach a decision within a fixed time limit. Present-day
Arbiters reach decisions very quickly on average, usually within about a few hundred
picoseconds. When faced with close calls, however, the circuits may occasionally take twice
as long, and in very rare cases the time needed to make a decision may be 10 times as long as
normal.
The Bus Arbiter is a multi-stage system that slightly mimics the process of several
prioritized devices sending information across a bus to their respective memory modules. At
the user end, there are four choices available based on the input. One can read or write to the
memory modules by sending in an address and desired data. Furthermore, the user can copy
and swap data between memory modules by sending in two addresses. An additional feature
in this design is the ability for the top priority device to interrupt the lower priority device. If
the lower priority device is processing information, the higher priority device can interrupt,
complete its process and go back to the lower level device to finish its previous procedure. It
must be noted that the lower priority device cannot be activated while the higher priority
device is busy.
A memory arbiter is a device used in a shared memory system to decide, for each
memory cycle, which CPU will be allowed to access that shared memory. A memory arbiter
is typically integrated into the memory controller/DMA controller.
When every CPU connected to the memory arbiter has synchronized memory access
cycles, the memory arbiter can be designed as a synchronous arbiter. Otherwise the memory
arbiter must be designed as an asynchronous arbiter.

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 Asynchronous Arbiter:
An important form of arbiter is used in asynchronous circuits to select the order of access to a
shared resource among asynchronous requests. Its function is to prevent two operations from
occurring at once when they should not.
For example, in a computer that has multiple CPUs or other devices accessing computer
memory, and has more than one clock, the possibility exists that requests from two
unsynchronized sources could come in at nearly the same time. "Nearly" can be very close in
time, in the sub-femtosecond range. The memory arbiter must then decide which request to
service first.

Synchronous Arbiter:
Arbiters are used in synchronous contexts as well in order to allocate access to a shared
resource.
A wave front arbiter is an example of a synchronous arbiter that is present in one type of
large network switch

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Algorithmic state machines (ASM)

The algorithmic state machine (ASM) method is a method for designing finite state machines.
It is used to represent diagrams of digital integrated circuits. The ASM diagram is like a state
diagram but less formal and thus easier to understand. An ASM chart is a method of
describing the sequential operations of a digital system.
The ASM method is composed of the following steps:
1. Create an algorithm, using pseudocode, to describe the desired operation of the
device.
2. Convert the pseudocode into an ASM chart.
3. Design the datapath based on the ASM chart.
4. Create a detailed ASM chart based on the datapath.
5. Design the control logic based on the detailed ASM chart.
ASM Chart: An ASM chart consists of an interconnection of four types of basic elements:
state names, states, condition checks and conditional outputs. An ASM state, represented as a
rectangle, corresponds to one state of a regular state diagram or finite state machine. The
Moore type outputs are listed inside the box.

State name: The name of the state is indicated inside the circle and the circle is placed
in the top left corner or the name is placed without the circle.
State box: The output of the state is indicated inside the rectangle box
Decision box: A diamond indicates that the stated condition expression is to be tested
and the exit path is to be chosen accordingly. The condition expression contains one or
more inputs to the FSM (Finite State Machine). An ASM condition check, indicated by a
diamond with one input and two outputs (for true and false), is used to conditionally
transfer between two states or between a state and a conditional output. The decision
box contains the stated condition expression to be tested, the expression contains one or
more inputs of the FSM.
Conditional output box: An oval denotes the output signals that are of Mealy type.
These outputs depend not only on the state but also the inputs to the FSM.

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Bus Arbiter using Algorithmic state machines(ASM) Method:

Fig: ASM Chart of Bus Arbiter

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Finite State Machine (FSM)

A finite-state machine (FSM) or finite-state automaton (FSA), or simply a state machine, is a
mathematical model of computation used to design both computer programs and sequential
logic circuits. It is conceived as an abstract machine that can be in one of a finite number of
states. The machine is in only one state at a time; the state it is in at any given time is called
the current state. It can change from one state to another when initiated by a triggering
event or condition; this is called a transition. A particular FSM is defined by a list of its
states, its initial state, and the triggering condition for each transition.
Bus Arbiter using Finite state machine(FSM) Method =>
State Diagram:

Fig: State Diagram of Bus Arbiter using FSM

Code:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity fsm is
port(Ra,Rb,clk:in std_logic;
Ga,Gb: out std_logic:='0');
end fsm;
architecture Behavioral of fsm is
type state_type is (idle,a,b);
signal y:state_type:=idle;
begin
process(clk)
begin

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if(clk'event and clk='1') then

case y is
when idle =>
if(ra='1') then
y<=a;
elsif(rb='1') then
y<=b;
end if;
when b =>
if(ra='1') then
y<=a;
else
if rb='1' then
y<=b;
else
y<=idle;
end if;
end if;
when a =>
if(ra='1') then
y<=a;
else
if rb='1' then
y<=b;
else
y<=idle;
end if;
end if;
end case;
end if;
end process;
process(y)
begin
case y is
when idle =>
ga<='0';
gb<='0';
when a =>
ga<='1';
gb<='0';
when b =>
ga<='0';
gb<='1';
end case;

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end process;
end Behavioral;
RTL Schematic:

Output:

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