Analog and Digital IC Applications Lab Manual

www.jntuworld.com www.jwjobs.
net
Study of OP AMPs - IC 741, IC 555-functioning, parameters and

specifications
IC 741 :
General Description:
The IC 741 is a high performance monolithic operational amplifier constructed using the planer
epitaxial process. High common mode voltage range and absence of latch-up tendencies make the IC 741
ideal for use as voltage follower. The high gain and wide range of operating voltage provide superior
performance in integrator, summing amplifier and general feedback applications.
Block Diagram of Op-Amp:
Pin Configuration:
Prepared By SURESH BABU M

Asst.Prof ,ECE Dept.,AITH, Cont No.+91-80992 28247
www.jntuworld.com
www.jntuworld.com www.jwjobs.net
Features:
1. No frequency compensation required.

2. Short circuit protection
3. Offset voltage null capability
4. Large common mode and differential voltage ranges
5. Low power consumption
6. No latch-up
Specifications:
1. Voltage gain A = typically 2,00,000

2. I/P resistance RL = , practically 2M
3. O/P resistance R =0, practically 75
4. Bandwidth = Hz. It can be operated at any frequency
5. Common mode rejection ratio =
(Ability of op amp to reject noise voltage)
6. Slew rate + V/sec

(Rate of change of O/P voltage)
7. When V1 = V2, VD=0

8. Input offset voltage (Rs 10K) max 6 mv
9. Input offset current = max 200nA
10. Input bias current : 500nA
11. Input capacitance : typical value 1.4pF
12. Offset voltage adjustment range : 15mV
13. Input voltage range : 13V
14. Supply voltage rejection ratio : 150 V/V
15. Output voltage swing: + 13V and 13V for RL > 2K
16. Output short-circuit current: 25mA
17. supply current: 28mA
18. Power consumption: 85mW
19. Transient response: rise time= 0.3 s
Overshoot= 5%

www.jntuworld.com
Applications:
1. AC and DC amplifiers
2. Active filters
3. Oscillators
4. Comparators
5. Regulators
IC 555:
Description:
The operation of SE/NE 555 timer directly depends on its internal function. The three equal
resistors R1, R2, R3 serve as internal voltage divider for the source voltage. Thus one-third of the source
voltage VCC appears across each resistor.
Comparator is basically an Op amp which changes state when one of its inputs exceeds the
reference voltage. The reference voltage for the lower comparator is +1/3 VCC. If a trigger pulse applied
at the negative input of this comparator drops below +1/3 VCC, it causes a change in state. The upper
comparator is referenced at voltage +2/3 VCC. The output of each comparator is fed to the input terminals
of a flip flop.
The flip-flop used in the SE/NE 555 timer IC is a bistable multivibrator. This flip flop changes
states according to the voltage value of its input. Thus if the voltage at the threshold terminal rises above
+2/3 VCC, it causes upper comparator to cause flip-flop to change its states. On the other hand, if the
trigger voltage falls below +1/3 VCC, it causes lower comparator to change its states. Thus the output of
the flip flop is controlled by the voltages of the two comparators. A change in state occurs when the
threshold voltage rises above +2/3 VCC or when the trigger voltage drops below +1/3 Vcc.
The output of the flip-flop is used to drive the discharge transistor and the output stage. A high or
positive flip-flop output turns on both the discharge transistor and the output stage. The discharge
transistor becomes conductive and behaves as a low resistance short circuit to ground. The output stage
behaves similarly. When the flip-flop output assumes the low or zero states reverse action takes place
i.e., the discharge transistor behaves as an open circuit or positive VCC state. Thus the operational state of

www.jntuworld.com
the discharge transistor and the output stage depends on the voltage applied to the threshold and the
trigger input terminals.
Block Diagram of IC 555:
Pin Configuration:

www.jntuworld.com
Function of Various Pins of 555 IC:
Pin (1) of 555 is the ground terminal; all the voltages are measured with respect to this pin.
Pin (2) of 555 is the trigger terminal, If the voltage at this terminal is held greater than one-third of
VCC, the output remains low. A negative going pulse from Vcc to less than Vec/3 triggers the output to go
High. The amplitude of the pulse should be able to make the comparator (inside the IC) change its state.
However the width of the negative going pulse must not be greater than the width of the expected output
pulse.
Pin (3) is the output terminal of IC 555. There are 2 possible output states. In the low output state, the
output resistance appearing at pin (3) is very low (approximately 10 ). As a result the output current
will goes to zero , if the load is connected from Pin (3) to ground , sink a current I Sink (depending upon
load) if the load is connected from Pin (3) to ground, and sinks zero current if the load is connected
between +VCC and Pin (3).
Pin (4) is the Reset terminal. When unused it is connected to +Vcc. Whenever the potential of Pin (4) is
drives below 0.4V, the output is immediately forced to low state. The reset terminal enables the timer
over-ride command signals at Pin (2) of the IC.
Pin (5) is the Control Voltage terminal. This can be used to alter the reference levels at which the time
comparators change state. A resistor connected from Pin (5) to ground can do the job. Normally 0.01F
capacitor is connected from Pin (5) to ground. This capacitor bypasses supply noise and does not allow it
affect the threshold voltages.
Pin (6) is the threshold terminal. In both astable as well as monostable modes, a capacitor is connected
from Pin (6) to ground. Pin (6) monitors the voltage across the capacitor when it charges from the supply
and forces the already high O/p to Low when the capacitor reaches +2/3 VCC.
Pin (7) is the discharge terminal. It presents an almost open circuit when the output is high and allows
the capacitor charge from the supply through an external resistor and presents an almost short circuit
when the output is low.
Pin (8) is the +Vcc terminal. 555 can operate at any supply voltage from +3 to +18V.

www.jntuworld.com
Features of 555 IC
1. The load can be connected to o/p in two ways i.e. between pin 3 & ground 1 or between pin 3 & VCC
(supply)
2. 555 can be reset by applying negative pulse, otherwise reset can be connected to +V cc to avoid false
triggering.
3. An external voltage effects threshold and trigger voltages.
4. Timing from micro seconds through hours.
5. Monostable and bistable operation
6. Adjustable duty cycle
7. Output compatible with CMOS, DTL, TTL
8. High current output sink or source 200mA
9. High temperature stability
10. Trigger and reset inputs are logic compatible.
Specifications:
1. Operating temperature : SE 555-- -55oC to 125oC ,NE555---0 o to 70 o C

2. Supply voltage : +5V to +18V
3. Timing : Sec to Hours
4. Sink current : 200mA
5. Temperature stability : 50 PPM/oC change in temp or 0-005% /oC.
Applications:
Monostable and Astable Multivibrators
1. dc-ac converters
2. Digital logic probes
3. Waveform generators
4. Analog frequency meters
5. Tachometers
6. Temperature measurement and control
7. Infrared transmitters
8. Regulator & Taxi gas alarms etc.

www.jntuworld.com
1. OP AMP APPLICATIONS - ADDER, SUBTRACTOR,

COMPARATOR CIRCUITS
AIM:
To study the applications of IC 741 as adder, sub tractor, comparator.
APPARATUS:
1. IC 741
2. Resistors (1K)4
3. Function generator
4. Regulated power supply
5. IC bread board trainer
6. CRO
7. Patch cards and CRO probes
CIRCUIT DIAGRAM:
Adder:
Subtractor:

www.jntuworld.com
Comparator:
THEORY:
ADDER:
Op-Amp may be used to design a circuit whose output is the sum of several input signals such as
circuit is called a summing amplifier or summer. We can obtain either inverting or non inverting
summer. The circuit diagrams shows a two input inverting summing amplifier. It has two input
voltages V1and V2, two input resistors R1, R2 and a feedback resistor Rf. Assuming that op-amp is
in ideal conditions and input bias current is assumed to be zero, there is no voltage drop across the
resistor Rcomp and hence the non inverting input terminal is at ground potential.
By taking nodal equations.
V1/R1 +V2/R2 +V0/Rf =0
V0 = - [(Rf/R1) V1 +(Rf/R2) V2]
And here R1 = R2 = Rf = 1K
V0 = -(V1 +V2)
Thus output is inverted and sum of input.
SUBTRACTOR:
A basic differential amplifier can be used as a sub tractor. It has two input signals V1 and V2 and
two input resistances R1 and R2 and a feedback resistor Rf. The input signals scaled to the desired
values by selecting appropriate values for the external resistors. From the figure, the output voltage
of the differential amplifier with a gain of 1 is
V0 = -R/Rf(V2-V1)
V0 = V1-V2.
Also R1 =R2 = Rf =1K.

www.jntuworld.com
Thus, the output voltage V0 is equal to the voltage V1 applied to the non inverting terminal minus
voltage V2 applied to inverting terminal.
Hence the circuit is sub tractor.
COMPARATOR:
A comparator is a circuit which compares a signal voltage applied at one input of an op-amp with a
known reference voltage at the other input. It is basically an open loop op-amp with output Vsat as
in the ideal transfer characteristics. It is clear that the change in the output state takes place with an
increment in input Vi of only 2mv. This is the uncertainty region where output cannot be directly
defined There are basically 2 types of comparators.
1. Non inverting comparator and.
2. Inverting comparator.
The applications of comparator are zero crossing detectors, window detector, and time marker
generator and phase meter.
OBSERVATIONS:
ADDER: SUBTRACTOR:
V1(V) V2(V) Vo(V)
V1(V) V2(V) Vo(V)
2.5 2.5 -5.06
2.5 3.3 0.8
3.8 4.0 -8.04
4.1 5.7 1.67
COMPARATOR:
MODEL GRAPH:

www.jntuworld.com
PROCEDURE:
ADDER:
1. Connections are made as per the circuit diagram.
2. Apply input voltage
1) V1= 5v,V2=2v
2) V1= 5v,V2=5v
3) V1= 5v, V2=7v.
3. Using Millimeter measure the dc output voltage at the output terminal.
4. For different values of V1 and V2 measure the output voltage.
SUBTRACTOR:
2. Apply input voltage
1) V1= 5v,V2=2v
2) V1= 5v,V2=5v
3) V1= 5v,V2=7v.
3. Using multi meter measure the dc output voltage at the output terminal.
4. For different values of V1 and V2 measure the output voltage.
COMPARATOR:
2. Select the sine wave of 10V peak to peak, 1K Hz frequency.
3. Apply the reference voltage 2V and trace the input and output wave forms.
4. Superimpose input and output waveforms and measure sine wave amplitude with reference to
Vref.
5. Repeat steps 3 and 4 with reference voltages as 2V, 4V, -2V, -4V and observe the waveforms.
6. Replace sine wave input with 5V dc voltage and Vref= 0V.
7. Observe dc voltage at output using CRO.
8. Slowly increase Vref voltage and observe the change in saturation voltage.
PRECAUTIONS:
1. Make null adjustment before applying the input signal.
2. Maintain proper Vcc levels.
RESULT:
The operation of IC 741 Op-Amp as adder, sub tractor and comparator is studied and values are
noted.

www.jntuworld.com
VIVA QUESTIONS:
1. What is an op-amp?
2. What are ideal characteristics of op amp?
3. What is the function of adder?
4. What is meant by comparator?

www.jntuworld.com
2. ACTIVE FILTER APPLICATIONS - LPF, HPF [ FIRST ORDER ]
AIM:
To study Op-Amp as first order LPF and first order HPF and to obtain frequency response.
APPARATUS:
1. IC 741.
2. Resistors (10K--2, 560, 330
3. Capacitors(0.1)
4. Bread board trainer
5. CRO
6. Function generator
7. connecting wires
8. Patch cards.
CIRCUIT DIAGRAM:
(a) LPF (b) HPF
THEORY:
LOWPASS FILTER:
A LPF allows frequencies from 0 to higher cut of frequency, fH. At fH the gain is 0.707 Amax, and
after fH gain decreases at a constant rate with an increase in frequency. The gain decreases 20dB
each time the frequency is increased by 10. Hence the rate at which the gain rolls off after f H is
20dB/decade or 6 dB/ octave, where octave signifies a two fold increase in frequency. The
frequency f=fH is called the cut off frequency because the gain of the filter at this frequency is down
www.jntuworld.com
by 3 dB from 0 Hz. Other equivalent terms for cut-off frequency are -3dB frequency, break
frequency, or corner frequency.
HIGH PASS FILTER:
The frequency at which the magnitude of the gain is 0.707 times the maximum value of gain is called
low cut off frequency. Obviously, all frequencies higher than f L are pass band frequencies with the
highest frequency determined by the closed loop band width all of the op-amp.
Design:
First Order LPF:
To design a Low Pass Filter for higher cut off frequency f H = 4 KHz and pass band gain of 2
fH = 1/( 2RC )
Assuming C=0.01 F, the value of R is found from
R= 1/(2fHC) =3.97K
The pass band gain of LPF is given by AF = 1+ (RF/R1)= 2
Assuming R1=10 K, the value of RF is found from
RF=( AF-1) R1=10K
First Order HPF: To design a High Pass Filter for lower cut off frequency fL = 4 KHz and pass
band gain of 2
fL = 1/( 2RC )
Assuming C=0.01 F,the value of R is found from
R= 1/(2fLC) =3.97K
The pass band gain of HPF is given by AF = 1+ (RF/R1)= 2
Assuming R1=10 K, the value of RF is found from
RF=( AF-1) R1=10K
Procedure:
First Order LPF
1. Connections are made as per the circuit diagram shown in Fig 1.
2. Apply sinusoidal wave of constant amplitude as the input such that op-amp does not go into
saturation.
3. Vary the input frequency and note down the output amplitude at each step as shown in Table (a).
4. Plot the frequency response as shown in Fig 3.

www.jntuworld.com
First Order HPF

1. Connections are made as per the circuit diagrams shown in Fig 2.
2. Apply sinusoidal wave of constant amplitude as the input such that op-amp does not go into
saturation.
3. Vary the input frequency and note down the output amplitude at each step as shown in Table (b).
4. Plot the frequency response as shown in Fig 4.
OBSERVATIONS:
Tabular Form and Sampled Values:
a)LPF
Input voltage Vin = 0.5V
Frequency O/P Voltage Gain

Voltage(V) Gain indB
Vo/Vi
100Hz 0.9 1.8 5.105
200Hz 0.9 1.8 5.105
300Hz 0.9 1.8 5.105
500Hz 0.9 1.8 5.105
750Hz 0.9 1.8 5.105
900Hz 0.9 1.8 5.105
1KHz 0.9 1.8 5.105
2KHz 0.8 1.6 4.08
3KHz 0.75 1.5 3.52
4KHz 0.7 1.4 2.92
5KHz 0.65 1.3 2.27
6KHz 0.55 1.1 0.82
7KHz 0.5 1.0 0
8KHz 0.45 0.9 -0.91
9KHz 0.4 0.8 -1.94
10KHz 0.35 0.7 -3.09

www.jntuworld.com
b) HPF
Frequency O/P Voltage Gain

Voltage(V) Gain indB
Vo/Vi
500Hz 0.12 0.24 -12.39
700Hz 0.16 0.32 -9.89
800Hz 0.2 0.4 -7.95
1KHz 0.24 0.48 -6.38
2KHz 0.4 0.8 -1.938
3KHz 0.55 1.1 0.83
4KHz 0.7 1.4 2.92
5KHz 0.75 1.5 3.52
6KHz 0.8 1.6 4.08
7KHz 0.85 1.7 4.60
8KHz 0.85 1.7 4.60
9KHz 0.85 1.7 4.60
10KHz 0.85 1.7 4.60
MODEL GRAPH:
High Pass Filter Low Pass Filter

www.jntuworld.com
PRECAUTIONS:
1. Make null adjustment before applying the input signal.
2. Maintain proper Vcc levels.
RESULT:
The frequency response of LPF and HPF is plotted using IC741 Op-Amp.
VIVA QUESTIONS:
1. What is the function of the filter?
2. What are the different types of filters?
3. Define pass band and stop band of filters?
4. Define cut off frequency?
5. What is the difference between HPF&LPF?

www.jntuworld.com
3. Integrator and Differentiator Circuits using IC 741
Aim: To design and verify the operation of an integrator and differentiator for a given input.
Apparatus required:
S.No Equipment/Component name Specifications/Value Quantity

1 741 IC Refer page no 2 1
2 Capacitors 0.1f, 0.01f Each one
3 Resistors 159, 1.5k Each one
4 Regulated Power supply (0 30)V,1A 1
5 Function generator (1Hz 1MHz) 1
6 Cathode Ray Oscilloscope (0 20MHz) 1
Theory
Integrator: In an integrator circuit, the output voltage is integral of the input signal. The output voltage
t
of an integrator is given by Vo = -1/R1Cf Vidt
o
At low frequencies the gain becomes infinite, so the capacitor is fully charged and behaves like an open
circuit. The gain of an integrator at low frequency can be limited by connecting a resistor in shunt with
capacitor.
Differentiator: In the differentiator circuit the output voltage is the differentiation of the input voltage.
dVi
The output voltage of a differentiator is given by Vo = -RfC1 .The input impedance of
dt
this circuit decreases with increase in frequency, thereby making the circuit sensitive to high frequency
noise. At high frequencies circuit may become unstable.

www.jntuworld.com
Circuit Diagrams:
Fig 1: Integrator
Fig 2: Differentiator

www.jntuworld.com
Design equations:
Integrator:
Choose T = 2RfCf
Where T= Time period of the input signal
Assume Cf and find Rf
Select Rf = 10R1
1
T /2
Vo (p-p) =
R1C f V
o
i ( p p) dt
Differentiator
Select given frequency fa = 1/(2RfC1), Assume C1 and find Rf
Select fb = 10 fa = 1/2R1C1 and find R1
From R1C1 = RfCf, find Cf
Procedures:
Integrator
1. Connect the circuit as per the diagram shown in Fig

2. Apply a square wave/sine input of 4V(p-p) at 1KHz
3. Observe the output at pin 6.
4. Draw input and output waveforms as shown in Fig
Differentiator
1. Connect the circuit as per the diagram shown in Fig

2. Apply a square wave/sine input of 4V(p-p) at 1KHz
3. Observe the output at pin 6
4. Draw the input and output waveforms as shown in Fig

www.jntuworld.com
Wave Forms:
Integrator
Fig 3: Input and output waves forms of integrator

www.jntuworld.com
Differentiator
Fig 4 :Input and output waveforms of Differentiator

www.jntuworld.com
Sample readings:
Integrator
Input Square wave Output - Triangular

Amplitude(VP-P) Time period Amplitude (VP-P) Time period
(V) (ms) (V) (ms)
8 1 10 1
Input sine wave Output - cosine

Amplitude(VP-P) Time period Amplitude (VP-P) Time period
(V) (ms) (V) (ms)
8 1 6 1
Differentiator
Input square wave Output - Spikes

Amplitude (VP-P) Time period Amplitude (VP-P) Time period
(V) (ms) (V) (ms)
8 1 28 1
Input sine wave Output - cosine

Amplitude (VP-P) Time period Amplitude (VP-P) Time period
(V) (ms) (V) (ms)
8 1 1.8 1
Model Calculations:
Integrator:
For T= 1 msec
fa= 1/T = 1 KHz

www.jntuworld.com
fa = 1 KHz = 1/(2RfCf)
Assuming Cf= 0.1f, Rf is found from Rf=1/(2faCf)
Rf=1.59 K
Rf = 10 R1
R1= 159
Differentiator
For T = 1 msec
f= 1/T = 1 KHz
fa = 1 KHz = 1/(2RfC1)
Assuming C1= 0.1f, Rf is found from R f=1/(2faC1)
Rf=1.59 K
fb = 10 fa = 1/2R1C1
for C1= 0.1f;
R1 =159
Precautions: Check the connections before giving the power supply.
Readings should be taken carefully.
Result: For a given square wave and sine wave, output waveforms for integrator and differentiator are
observed.
Inferences: Spikes and triangular waveforms can be obtained from a given square waveform by using
differentiator and integrator respectively.

www.jntuworld.com
Questions & Answers:
1. What are the problems of ideal differentiator?

Ans: At high frequencies the differentiator becomes unstable and breaks into oscillation. The
differentiator is sensitive to high frequency noise.
2. What are the problems of ideal integrator?

Ans: The gain of the integrator is infinite at low frequencies.
3. What are the applications of differentiator and integrator?

Ans: The differentiator used in waveshaping circuits to detect high frequency components in an
input signal and also as a rate-of change detector in FM demodulators.
The integrator is used in analog computers and analog to digital converters and signal-wave
shaping circuits.
4. What is the need for Rf in the circuit of integrator?

Ans: The gain of an integrator at low frequencies can be limited to avoid the saturation problem if
the feedback capacitor is shunted by a resistance R f
5. What is the effect of C1 on the output of a differentiator?

Ans: It is used to eliminate the high frequency noise problem.

www.jntuworld.com
4. IC 741 Oscillator Circuits
Phase Shift and Wien Bridge Oscillators
Aim: To design (i) phase shift and (ii) Wien Bridge oscillators for the given frequency of oscillation
and verify it practically.
Apparatus required:

1 IC 741 Refer page no 2 1
2 Resistors 1.3 K,3.18 K Each Three
13K, ,31.8 K Each one
Variable Resistor 500 K pot
1
3 Capacitors 0.1 F 3
0.01 F 2
4 Regulated Power supply (0 30V),1A 1
5 Cathode Ray Oscilloscope (0 -20MHz) 1
Theory:
The A741 is a high performance monolithic operational amplifier constructed using the planar
epitaxial process. High common mode voltage range and absence of latch-up tendencies make the A741
ideal for use as voltage follower. The high gain and wide range of operating voltage provides superior
performance in integrator, summing amplifier and general feedback applications.
In the phase shift oscillator, out of 360o phase shift, 180o phase shift is provided by the op-amp
and another 180o is by 3 RC networks. In the Weinbridge oscillator, the balancing condition of the bridge
provides the total 360o phase shift.

www.jntuworld.com
Circuit Diagrams:
Fig 1 : RC Phase shift oscillator
Fig 2: Wien Bridge oscillator

www.jntuworld.com
Design:
2. Phase shift oscillator

To design a phase shift oscillator with f o =500 Hz
fo = 1/(2RC 6 )
and gain= RF/R1= 29
Assuming C = 0.1 F,the value of R is found from
R = 1/ (2 foC 6 ) = 1.3 K
Take R1 = 10R =13 K
RF = 29R1 (use 500K pot)
2. Wien bridge Oscillator
To design a Wien bridge oscillator with fo =5 KHz
fo = 1/2RC and RF = 2R1
Assuming C = 0.01 F,the value of R is found from
R= 1/2fc= 3.18 K
Take R1 = 10 R=31.8 K
RF = 2R1 (use 100K pot)

www.jntuworld.com
Procedure:
1. Phase shift oscillator
1. Connect the circuit as per the circuit diagram shown in Fig 1

2. Observe the output waveform on the CRO.
3. Vary the potentiometer to get the undistorted waveform as shown Fig a.
4. Measure the time period and amplitude of the output waveform.
5. Plot the waveforms on a graph sheet.
2. Wien bridge Oscillator
1. Connect the circuit as per the circuit diagram shown in Fig 2
2. Observe the output waveform on the CRO.
3. Vary the potentiometer to get the undistorted waveform as shown in Fig b
4. Measure the time period and amplitude of the output waveform.
5. Plot the waveforms on a graph sheet
Waveforms:
Fig (a): RC Phase Shift Oscillator
Fig (b): Wien Bridge Oscillator

www.jntuworld.com
Tabular form:
1. Phase shift oscillator:
S.No Amplitude(VP-P) Time period Practical frequency Theoretical frequency

(ms) (Hz) (Hz)
1 20V 2.2 454 500
2. Wien bridge Oscillator:
S.No Amplitude(VP-P) Time period Practical frequency Theoretical frequency

(ms) (Hz) (Hz)
1 20V 0.22ms 4.545KHz 5KHz
Precautions:
Check the connections before giving the power supply.
Result:
RC phase shift and Wien bridge oscillators are designed and output waveforms are observed as
shown in Fig (a) and (b).
Inferences:
Sinusoidal waveforms can be designed by using RC phase shift and Wien-Bridge oscillators.

www.jntuworld.com
1 What is an oscillator?
Ans: Oscillator is a circuit that generates a repetitive waveform of fixed amplitude and frequency
without any external input signal.
2 How do you change the frequency of oscillation in RC phase shift and Wien bridge oscillators?
Ans: By varying either resistor R or capacitor C values
3 What are the applications of oscillators?

Ans: Oscillators are used in radio, television, computers, and communications
4 What is the advantage of using opamp in the oscillator circuit?

Ans: Opamp is used to generate a variety of output wave forms.
5 How do you achieve fine variations in fo ?

Ans: Fine variations in fo can be achieved by changing C value.
6 How do you achieve coarse variations in fo ?

Ans: Coarse variations in fo can be achieved by changing R value

www.jntuworld.com
5. IC 555 Timer-Monostable Operation Circuit
Aim: To generate a pulse using Monostable Multivibrator by using IC555
Apparatus required:
S.No Equipment/Component Specifications/Value Quantity

name
1 555 IC Refer page no 6 1
2 Capacitors 0.1f,0.01f Each one
3 Resistor 10k 1
4 Regulated Power supply (0 30V),1A 1
5 Function Generator (1HZ 1MHz) 1
6 Cathode ray oscilloscope (0 20MHz) 1
Theory: A Monostable Multivibrator, often called a one-shot Multivibrator, is a pulse-generating

circuit in which the duration of the pulse is determined by the RC network connected externally to the 555
timer. In a stable or stand by mode the output of the circuit is approximately Zero or at logic-low level.
When an external trigger pulse is obtained, the output is forced to go high ( VCC). The time for which
the output remains high is determined by the external RC network connected to the timer. At the end of
the timing interval, the output automatically reverts back to its logic-low stable state. The output stays
low until the trigger pulse is again applied. Then the cycle repeats. The Monostable circuit has only one
stable state (output low), hence the name monostable. Normally the output of the Monostable
Multivibrator is low.
Design:
Consider VCC = 5V, for given tp
Output pulse width tp = 1.1 RA C
Assume C in the order of microfarads & Find R A

www.jntuworld.com
Circuit Diagram:
Fig1: Monostable Circuit using IC555
Typical values:
If C=0.1 F , RA = 10k then tp = 1.1 mSec
Trigger Voltage =4 V
Procedure:
1. Connect the circuit as shown in the circuit diagram.

2. Apply Negative triggering pulses at pin 2 of frequency 1 KHz.
3. Observe the output waveform and measure the pulse duration.
4. Theoretically calculate the pulse duration as T high=1.1. RAC
5. Compare it with experimental values.

www.jntuworld.com
Waveforms:
Fig 2 (a): Trigger signal (b): Output Voltage (c): Capacitor Voltage
Sample Readings:
Trigger Output wave Capacitor output

0 to 5V range 0 to 5V range 0 to 3.33 V range
1)1V,0.09msec 4.6V, 0.5msec 3V, 0.88 msec
Precautions:
Result: The input and output waveforms of 555 timer monostable Multivibrator are observed as shown
in Fig 2(a), (b), (c).
Inferences: Output pulse width depends only on external components RA and C connected to IC555.

www.jntuworld.com
1. Is the triggering given is edge type or level type? If it is edge type, trailing or raising edge?
Ans: Edge type and it is trailing edge
2. What is the effect of amplitude and frequency of trigger on the output?

Ans: Output varies proportionally.
3. How to achieve variation of output pulse width over fine and course ranges?
Ans: One can achieve variation of output pulse width over fine and course ranges by
varying capacitor and resistor values respectively
4. What is the effect of Vcc on output?

Ans: The amplitude of the output signal is directly proportional to Vcc
5. What are the ideal charging and discharging time constants (in terms of R and C) of capacitor
voltage?
Ans: Charging time constant T=1.1RC Sec
Discharging time constant=0 Sec
6. What is the other name of monostable Multivibrator? Why?

Ans: i) Gating circuit .It generates rectangular waveform at a definite time and thus could be used in
gate parts of the system.
ii) One shot circuit. The circuit will remain in the stable state until a trigger pulse is received. The
circuit then changes states for a specified period, but then it returns to the original state.
7. What are the applications of monostable Multivibrator?

Ans: Missing Pulse Detector, Frequency Divider, PWM, Linear Ramp Generator

www.jntuworld.com
6. Schmitt Trigger Circuits- using IC 741 & IC 555
Aim: To design the Schmitt trigger circuit using IC 741 and IC 555
Apparatus required:

1 IC 741 Refer page no 2 1
2 555IC Refer page no 6 1
3 Cathode Ray Oscilloscope (0 20MHz) 1
4 Multimeter 1
5 Resistors 100 2
56 K 1
6 Capacitors 0.1 f, 0.01 f Each one
7 Regulated power supply (0 -30V),1A 1
Theory:
The circuit shows an inverting comparator with positive feed back. This circuit converts orbitrary
wave forms to a square wave or pulse. The circuit is known as the Schmitt trigger (or) squaring circuit.
The input voltage Vin changes the state of the output Vo every time it exceeds certain voltage levels called
the upper threshold voltage Vut and lower threshold voltage Vlt.
When Vo= - Vsat, the voltage across R1 is referred to as lower threshold voltage, Vlt. When
Vo=+Vsat, the voltage across R1 is referred to as upper threshold voltage Vut.
The comparator with positive feed back is said to exhibit hysterisis, a dead band condition.
Circuit Diagrams: Fig 1: Schmitt trigger circuit using IC 741

www.jntuworld.com
Fig 2: Schmitt trigger circuit using IC 555
Design:
Vutp = [R1/(R1+R2 )](+Vsat)
Vltp = [R1/(R1+R2 )](-Vsat)
Vhy = Vutp Vltp
=[R1/(R1+R2)] [+Vsat (-Vsat)]
Procedure:
1. Connect the circuit as shown in Fig 1 and Fig2.

2. Apply an orbitrary waveform (sine/triangular) of peak voltage greater than UTP to the input of a
Schmitt trigger.
3. Observe the output at pin6 of the IC 741 and at pin3 of IC 555 Schmitt trigger circuit by varying the
input and note down the readings as shown in Table 1 and Table 2
4. Find the upper and lower threshold voltages (Vutp, VLtp) from the output wave form.
www.jntuworld.com
Wave forms:
Fig 3: (a) Schmitt trigger input wave form (b) Schmitt trigger output wave form
Sample readings:
Table 1:
Parameter Input Output

741 555 741 555
Voltage( Vp-p) 3.6 4 24.8 4.4
Time period(ms) 0.72 1 0.72 1
Table 2:
Parameter 741 555

Vutp 0.2V 0.4V
Vltp -0.05 -0.4V

www.jntuworld.com
Precautions:
Results:
UTP and LTP of the Schmitt trigger are obtained by using IC 741 and IC 555 as shown in Table 2.
Inferences: Schmitt trigger produces square waveform from a given signal.
1. What is the other name for Schmitt trigger circuit?

Ans: Regenerative comparator
2. In Schmitt trigger which type of feed back is used?

Ans: Positive feedback.
3. What is meant by hysteresis?

Ans: The comparator with positive feedback is said to be exhibit hysteresis, a deadband condition.
When the input of the comparator is exceeds Vutp, its output switches from + Vsat to - Vsat and reverts
back to its original state,+ Vsat ,when the input goes below Vltp
4. What are effects of input signal amplitude and frequency on output?

Ans: The input voltage triggers the output every time it exceeds certain voltage levels (UTP and
LTP). Output signal frequency is same as input signal frequency.

www.jntuworld.com
7. Voltage Regulator using IC723
Aim: To design a low voltage variable regulator of 2 to 7V using IC 723.
Apparatus required:

1 IC 723 Refer appendix A 1
2 Resistors 3.3K,4.7K,100 Each one

3 Variable Resistors 1K, 5.6K Each one
4 Regulated Power supply 0 -30 V,1A 1
5 Multimeter 3 digit display 1
Theory:
A voltage regulator is a circuit that supplies a constant voltage regardless of changes in load
current and input voltage variations. Using IC 723, we can design both low voltage and high voltage
regulators with adjustable voltages.
For a low voltage regulator, the output VO can be varied in the range of voltages Vo < Vref, where
as for high voltage regulator, it is VO > Vref. The voltage Vref is generally about 7.5V. Although voltage
regulators can be designed using Op-amps, it is quicker and easier to use IC voltage Regulators.IC 723 is
a general purpose regulator and is a 14-pin IC with internal short circuit current limiting, thermal
shutdown, current/voltage boosting etc. Furthermore it is an djustable voltage regulator which can be
varied over both positive and negative voltage ranges. By simply varying the connections made
externally, we can operate the IC in the required mode of operation. Typical performance parameters are
line and load regulations which determine the precise characteristics of a regulator. The pin configuration
and specifications are shown in the Appendix-A.

www.jntuworld.com
Circuit
Diagram:
Fig1: Voltage Regulator
Design of Low voltage Regulator :-
Assume Io= 1mA,VR=7.5V
RB = 3.3 K
For given Vo
R1 = ( VR VO ) / Io
R2 = VO / Io
Procedure:
a) Line Regulation:
1. Connect the circuit as shown in Fig 1.
2. Obtain R1 and R2 for Vo=5V

www.jntuworld.com
3. By varying Vn from 2 to 10V, measure the output voltage Vo.
4. Draw the graph between Vn and Vo as shown in model graph (a)
5. Repeat the above steps for Vo=3V
b) Load Regulation: For Vo=5V
1. Set Vi such that VO= 5 V

2. By varying RL, measure IL and Vo
3. Plot the graph between IL and Vo as shown in model graph (b)
4. Repeat above steps 1 to 3 for VO=3V.
Sample Readings:
a) Line Regulation:
Vo set to 5V Vo set to 3V
Vi(V) Vo(V) Vi(V) Vo(V)
0 0 0 0
1 0.65 1 0.65
2 0.66 2 0.69
3 1.23 3 1.05
4 2.68 4 1.42
5 3.40 5 1.80
6 4.13 6 2.19
7 4.90 7 2.57
8 5.33 8 2.81
9 5.33 9 2.81
. 10 5.33 10 2.81

www.jntuworld.com
a) Load Regulation:
Vo set to 5V Vo set to 3V
IL (mA) Vo(V)
IL (mA) Vo(V)
24 2.81
46 5.33
22 2.81
44 5.33
20 2.81
40 5.33
18 2.81
35 5.33
16 2.81
28 5.33
14 2.81
20 5.33
12 2.81
18 5.33 10 2.81
16 5.33 8 2.81
12 5.33 6 2.81
8 5.33 4 2.81
6 5.33 2 2.81
4 5.33
2 5.33
Model graphs:
a) Line Regulation: b) Load Regulation:

www.jntuworld.com
Precautions:
Results:
Low voltage variable Regulator of 2V to 7V using IC 723 is designed. Load and Line Regulation
characteristics are plotted.
Inferences:
Variable voltage regulators can be designed by using IC 723.
1. What is the effect of R1 on the output voltage?

Ans: R1 decreases for an increase in the output voltage.
2. What are the applications of voltage regulators?
Ans: Voltage regulators are used as control circuits in PWM, series type
switch mode supplies, regulated power supplies, voltage stabilizers.
3. What is the effect of Vi on output?
Ans: Output varies linearly with input voltage up to some value (o/p voltage+
dropout voltage) and remains constant.

www.jntuworld.com
8. Three Terminal Voltage Regulators- 7805, 7809, 7912
Aim: To obtain the regulation characteristics of three terminal voltage regulators.
Apparatus required:
S.No Equipment/Component Name Specifications/Values Quantity

1 Bread board 1
2 IC7805 Refer appendix A 1
5 Multimeter 3 digit display 1
6 Milli ammeter 0-150 mA 1
7 Regulated power supply 0-30 V 1
8 Connecting wires
9 Resistors pot 100 ,1k Each one
Theory:
A voltage regulator is a circuit that supplies a constant voltage regardless of changes in load
current and input voltage. IC voltage regulators are versatile, relatively inexpensive and are available with
features such as programmable output, current/voltage boosting, internal short circuit current limiting,
thermal shunt down and floating operation for high voltage applications.
The 78XX series consists of three-terminal positive voltage regulators with seven voltage options.
These ICs are designed as fixed voltage regulators and with adequate heat sinking can deliver output
currents in excess of 1A.

www.jntuworld.com
The 79XX series of fixed output voltage regulators are complements to the 78XX series devices.
These negative regulators are available in same seven voltage options.
Typical performance parameters for voltage regulators are line regulation, load regulation,
temperature stability and ripple rejection. The pin configurations and typical parameters at 250C are
shown in the Appendix-B.
Circuit
Diagrams:
Fig 1: Positive Voltage Regulator
Fig 2: Negative Voltage Regulator

www.jntuworld.com
Procedure:
a) Line Regulation:
1. Connect the circuit as shown in Fig 1 by keeping S open for 7805.

2. Vary the dc input voltage from 0 to 10V in suitable stages and note down the output voltage in
each case as shown in Table1 and plot the graph between input voltage and output voltage.
3. Repeat the above steps for negative voltage regulator as shown in Fig.2 for 7912 for an input of 0
to -15V.
4. Note down the dropout voltage whose typical value = 2V and line regulation typical value = 4mv
for Vin =7V to 25V.
b) Load regulation:
1. Connect the circuit as shown in the Fig 1 by keeping S closed for load regulation.
2. Now vary R1 and measure current IL and note down the output voltage Vo in each case as shown
in Table 2 and plot the graph between current IL and Vo.
3. Repeat the above steps as shown in Fig 2 by keeping switch S closed for
negative voltage regulator 7912.
c) Output Resistance:
Ro= (VNL VFL)
IFL
VNL - load voltage with no load current
VFL - load voltage with full load current
IFL - full load current.

www.jntuworld.com
Sample readings:
a) Line regulation b) Load Regulation
1) IC 7805 1) IC 7805
Input Voltage Output Voltage Load Current Output Voltage

Vi,(V) Vo(V) IL(mA) Vo(V)
0 0 44 5
5 4.05 40 5
6 4.86 30 5
7 5 20 4.98
10 5 16 4.97
8 4.96
2) IC 7809 2) IC 7809
Load Current Output Voltage

Input Voltage Output Voltage IL(mA) Vo(V)
Vi,(V) Vo(V)
56 9
0 0
48 9
5 7.4
33 9
10 8.7
25 8.96
12 9
21 8.82
14 9
15 8.60

www.jntuworld.com
3)7912 3) IC 7912
Load Current Output Voltage

IL(mA) Vo(V)
Input Voltage Output Voltage
Vi,(V) Vo(V) 56 -12.09
0 0 46 -12.09
-10 -9.59 38 -12.07
-12 -11.59 28 -12.06
-14 -12 24 -11.98
-15 -12 20 -11.80
Graphs:
IC 7805

www.jntuworld.com
IC 7809
IC7912
% load regulation = VNL - VFL x 100
VFL
Precautions:
Result:
Line and load regulation characteristics of 7805, 7809 and 7912 are plotted

www.jntuworld.com
Inferences:
Line and load regulation characteristics of fixed positive and negative three terminal voltages are
obtained. These voltage regulators are used in regulated power supplies.
1. Mention the IC number for a negative fixed three terminal voltage regulator of 12V.
Ans: IC 7912
2. Explain the significance of IC regulators in power supply

Ans: To get constant dc voltages.
3. What is drop-out voltage?

Ans: The difference between input and output voltages is called dropout voltage
4. What is the role of C1 and C2?
Ans: C1 is used to cancel the inductive effects.
C2 is used to improve the transient response of regulator.
4. What are C1 and C2 called?

Ans: Bypass capacitors

www.jntuworld.com
APPENDIX-A
IC723
Pin Configuration
Specifications of 723:
Power dissipation : 1W
Input Voltage : 9.5 to 40V
Output Voltage : 2 to 37V
Output Current : 150mA for Vin-Vo = 3V
10mA for Vin-Vo = 38V
Load regulation : 0.6% Vo
Line regulation : 0.5% Vo

www.jntuworld.com
APPENDIX-B
Pin Configurations:
78XX 79XX
Plastic package
Typical parameters at 25oC:
Parameter LM 7805 LM 7809 LM 7912

Vout,V 5 9 -12
Imax,A 1.5 1.5 1.5
Load Reg,mV 10 12 12
Line Reg,mV 3 6 4
Ripple Rej,dB 80 72 72
Dropout 2 2 2
Rout,m 8 16 18
ISL,A 2.1 0.45 1.5

www.jntuworld.com
REFERENCES
1. D.Roy Choudhury and Shail B.Jain, Linear Integrated Circuits, 2 nd edition, New Age
International.
2. James M. Fiore, Operational Amplifiers and Linear Integrated Circuits: Theory and Application,
WEST.
3. Malvino, Electronic Principles, 6th edition, TMH
4. Ramakant A. Gayakwad, Operational and Linear Integrated Circuits,4 th edition, PHI.
5. Roy Mancini, OPAMPs for Everyone, 2nd edition, Newnes.
6. S. Franco, Design with Operational Amplifiers and Analog Integrated Circuits, 3rd edition, TMH.
7. William D. Stanley, Operational Amplifiers with Linear Integrated Circuits, 4 th edition, Pearson.
8. www.analog.com

www.jntuworld.com
www.jntuworld.com
RS, JK , D AND T FLIP FLOP

Aim:
To verify the truth table of
a) RS Flip Flop using Logicgates c) D Flip Flop-IC 7474

b) JK Flip Flop-IC 7476 d) T Flip Flop using JKFlip-Flop.
Apparatus :-
1. RS, JK, D and T flip-flops Trainer Kit.
2. Set of Patch chords.
RS Flip-Flop:
Fig1. RS Flip-Flop
RS Flip-Flop Clocked version:
S
Q
CLK
Truth table 1 for RS Flip Flop
INPUTS OUTPUT COMMENT

R S Q Q
0 0 1 1 Indeterminent
0 1 1 0 Set
1 0 0 1 Reset
1 1 Indeterminate No change
www.jntuworld.com
Procedure:
1. Construct the RS flip flop as shown in figure.
2. Feed the logic signals from the logic input switches observe the logic outputs on the logic level
LED indicators. Verify the truth table of clocked RS flip-flops.
JK Flip Flop:
Truth Table-2 for JK flip-flop:
INPUTS OUTPUTS COMMENT
Set(s) Reset(R) Clock J K Q Q

0 0 X X X 1 1 Indeterminent
0 1 X X X 1 0 Set
1 0 X X X 0 1 Reset
|
1 1 X 0 0 Q0 Q0 Previous
1 1 0 1 0 1 Reset
1 1 1 0 1 0 set
1 1 1 1 Toggle Race around
Procedure:
1. Connect S , R, J and K terminals to the logic input switches.
2. Connect the clock terminals to bounceless pulser high or low.
3. Connect Q and Q terminals to logic output indicators.
4. Set the S, R, J and K Signals by means of the switches as per the truth table2 verify the Q and
Q outputs .
www.jntuworld.com
D-Flip -Flop:
D-flip-flop using Nand gates :
S R CLOCK D Q Q COMMENT
0 0 X X 1 1 Race
0 1 X X 1 0 Set
1 0 X X 0 1 Reset
1 1 1 1 0 Data Transfer
1 1 0 0 1 Data Transfer
Truth Table - 3
www.jntuworld.com
Procedure:
1. Connect S, R and D terminal to the logic input switches.
2. Connect the clock terminals to bounceless pulser high or low.
4. Set the S, R and D signals by means of the switches as per TruthTable3. Verify the Q and Q
outputs.
T Flip Flop:
J& S R CLOCK Q Q COMMENT

K (T)
1 0 0 X 1 1 Race
1 0 1 X 1 0 Set
1 1 0 X 0 1 Reset
1 1 1 Qn-1 Qn-1 Data Transfer
Truth Table - 4
Procedure:
1. Connect S and R Terminals to the logic input switches.

2. Set J and K permanently to high by means of input switches.
3. Connect the clock terminals (T) to the bounceless pulser high or low.
5. Set the S and R signals by means of the switches as per Truth Table 4 verify the Q and Q
outputs.
Result: Verified the truth tables of all Flip-Flops.
www.jntuworld.com
Questions:-
1. What is the difference between Flip-Flop & latch?
2. Give examples for synchronous & asynchronous i/Ps?
3. What are the applications of different Flip-Flops?
4. What is universal flip-flop?
5. What is the advantage of Edge triggering over level triggering?
6. What is the relation between propagation delay & clock frequency of flip-flop?
7. What is race around in flip-flop & how to over come it?
8. What are not allowed inputs for RS flip flop using NAND & NOR gates?
9. Connect the J K Flip-Flop into D flip-flop and T flip-flop?
10. List the functions of asynchronous inputs?
www.jntuworld.com
IC7490 DECADE COUNTER

Aim: To construct and verify the working of a single digit decade counter using IC 7490.
Apparatus: 1) IC7490 Decade counter kit
2) Connecting patch cards.
Circuit Diagram :- OUTPUTS
Procedure: Fig:1
1. Wire the circuit diagram shown in figure 1.
2. Connect the 1Hz clock to pin CPO.(14)
3. Connect the reset terminals (MR1 & MR2) to high and set terminals (MS1 & MS2) to zero and
observe the output.
4. Now connect set and reset inputs to zero and observe the outputs.
5. Record the counter states for each clock pulse.
6. Design mod 6 counter using IC 7490 as shown in fig 2.
7. Record the counter states for each clock pulse.
8. Now Construct decade counter using J K F/Fs and record the counter states.
www.jntuworld.com
MOD 6 COUNTER :
Truth Table:-
A3 Msb A2 A1 A0 Lsb
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0000
0 1 1 0
www.jntuworld.com
Expected Wave Forms:-
Result:- Verified the working of a single digit decade counter using IC 7490.
Questions:-
1. Design Mod 7 and Mod 5 counter using IC 7490?`1`1
2. Design Mod 6 counter using JK F/Fs?
3. What is the modulus counter?
4. How many numbers of flip-flops are there in decade counter?
5. What is up down counter?
6. What is the difference between Register &counter?
7. What is BCD counter?
8. If the counter has n-flip-flops. What is the maximum count?
9. Which flip- flops are used in counter?
10. Design a divide by-96 counter using 7490Ics?
www.jntuworld.com
UNIVERSAL SHIFT REGISTER
Aim :- To study the following applications of the Universal shift register using IC
74194.
a . Shift Right Logic

b . Shift Left Logic
c . Parallel Load
Apparatus :-
1. Universal Shift Register using IC 74194 Trainer boards.
2. 5v fixed DC power supply.
Circuit Diagram:-
www.jntuworld.com
Procedure:-
STEP : 1. MASTER RESET
Set the inputs as below and observe the out puts as per table 1
MR S1 S0 DSR DSL CP P0 P1 P2 P3 Q0 Q1 Q2 Q3
0 X X X X X X X X X 0 0 0 0
Truth table 1
A logic 0 on MR resets all outputs to logic 0 irrespective of other inputs.
STEP :2 PARALLEL LOAD

In this step we load the data parallel. Set the inputs as below and observe the outputs.
MR S1 S0 DSR DSL CP P0 P1 P2 P3 Q0 Q1 Q2 Q3
1 1 1 x x CLK 1 1 1 1 1 1 1 1
Truth Table 2
Here when S1 & S0 are both logic 1 the input data is transferred parallely to output at
the clock positive transition change the input data and observe the change at the output .
STEP : 3 . SHIFT LEFT LOGIC 0 .

Set Q0 , Q1 , Q2 , Q3 to 1 1 1 1 by putting DSL to Logic 1 .
While running the above step, change the logic input DSL to logic 0
And S0 to logic 0 in the same sequence .Observe the following outputs after each clock pulse and verify .
CONDITION n CLOCK
PULSES Q0 Q1 Q2 Q3
MR = 1 0 1 1 1 1
S0 = 0 1 1 1 1 0
S1 = 1 2 1 1 0 0
DSL = 0 3 1 0 0 0
DSR = X 4 0 0 0 0
Truth Table 3
In the sequence 4 clock pulses logic o s are shifted left successively with each clock pulse .
STEP : 4 . SHIFT LEFT LOGIC 1 S
Set the Q0 Q1 Q2 Q3 to 0 0 0 0 by setting DSL input to logic 0 .
Now switch DSL input to logic 1 and observe the shifting of logic 1 s to left as below . Observe the
following outputs after each clock pulse and verify.
www.jntuworld.com
CONDITION n CLOCK
PULSES Q0 Q1 Q2 Q3
MR = 1 0 0 0 0 0
S0 = 0 1 0 0 0 1
S1 = 1 2 0 0 1 1
DSL = 1 3 0 1 1 1
DSR = X 4 1 1 1 1
Truth Table 4
STEP : 5 . SHIFT RIGHT LOGIC 0

Set the Q0 Q1 Q2 Q3 to 1 1 1 1 by setting DSR input to logic 1 .
Repeat step 4 and parallel load logic 1 s in all the 4 outputs .
Change the logic inputs of DSR to logic 0 and then of S1 to logic 0
in the same sequence . Observe the following outpus after each clock pulse and verify .
CONDITION n CLOCK
PULSES Q0 Q1 Q2 Q3
MR = 1 0 1 1 1 1
S0 = 1 1 0 1 1 1
S1 = 0 2 0 0 1 1
DSL = X 3 0 0 0 1
DSR = 0 4 0 0 0 0
Truth Table 5
STEP : 6 SHIFT RIGHT LOGIC 1 s
Now at this condition of all 0 at the outputs switch DSR to logic 1 this will enable all logic as serial data
and logic 1 s will be shifted successively with each clock pulse as shown below .Observe the following table
and verify the outputs .
CONDITION n CLOCK
PULSES Q0 Q1 Q2 Q3
MR = 1 0 0 0 0 0
S0 = 1 1 1 0 0 0
S1 = 0 2 1 1 0 0
DSL = X 3 1 1 1 0
DSR = 1 4 1 1 1 1
STEP : 7 . In the above steps for shift left or shift right operation ,(step 3 4 5 6 ) if both the S0 &S1 switches
are forced to logic 0 , then shifting operation will cease and whatever is the output data it will freeze or hold
. Observe this condition and verify .
www.jntuworld.com
CONDITION n CLOCK PULSES Q0 Q1 Q2 Q3

MR = 1 1 Previous data just before S0 &S1
S0 = 0 1 both switched to logic 0 .
S1 = 0 1
DSL = 0 1
DSR = 0 1
Truth Table 7
Result:- Verified the applications of the Universal shift register using IC 74194
Questions: -
1. What is the universal shift register?
2. In which circuits shifting and rotating circuits are used?
3. Which flip-flops are used in shift registers?
4. Which flip-flop is universal flip-flop?
5. What is the difference between shifting and rotating data?
6. What is register?
7. What is meant by parallel in &parallel out Shift register?
8. State various applications of Shift register?
9. List the basic types of shift register in terms of data movement?
10. Determine the output status of a 4-bit SIPO shift register, after 3 clock pulses if the I/P terminal is held
high?
5. 3 - 8 DECODER- 74138
AIM: To verify the operation of 3 to 8 line decoder using IC 74138.
APPARATUS:
1. IC 74138.
2. Bread board trainer kit
3. Patch cords
4. Connecting wires.
PIN DIAGRAM:
www.jntuworld.com
LOGIC DIAGRAM:
www.jntuworld.com
OBSERVATIONS:
THEORY:
Decoder is the combinational circuit which contains n input lines to 2n output
lines. The decoder is used for converting the binary code into the octal code. The
IC74138 is the 3*8 decoder which contains three inputs and eight outputs and also
three enables out of them two are active low and one is active high. Decoders are used
in the circuit where required to get more outputs than that of the inputs which also used
in the chip designing process for reducing the IC chip area.
PROCEDURE:
1. Connect the circuit as shown in the figure.
2. Apply Vcc=+5v to the Pin-16 of IC 74138.
3. Connect the inputs to Pins-1, 2&3.
4. Pins-4, 5, 6 are the enable inputs.
5. When E11 is high and E21 ,E3 are low then all the outputs are high irrespective
of inputs A0 ,A1 ,A2 .
6. Similarly when E21is high, all the outputs are high irrespective of the inputs.
7. When E3 is low all the outputs are high irrespective of E11 and E21 and high.
8. If E11 and E21 are low and E31 is high, the inputs are low, the outputs O01 will
be low with all the other outputs are low.
9. Similarly by changing the inputs we get (one) 1 output as low and all other
outputs as high.
10. When all inputs are high O71 will be low and all other will be high.
PRECAUTIONS:
1. All the pins should be identified properly.
www.jntuworld.com
2. Supply voltage should not exceed +5v.

3. Avoid loose connections on the bread board.
VIVA QUESTIONS:
1. What is decoder?
2. What is a encoder?
3. For a 2- I/P decoder how many O/Ps are produced
4. A decoder with n input produces max. of __ no.of minterms.
5. The general representation of an encoder is
6. Draw the 2 to 4 line decoder with only nor gates.
7. Difference b/w de multiplexer and decoder
8. The general representation of an encoder is for economical realization, decoder
is used to realize a function which contain ( Less no. of dont cares)
9. A 16 to 64 decoder can be obtained by cascading of
10. Can more than one decoder O/P be activated at one time?
RESULT:
The working of the 3 to 8 decoder is verified using IC 74138.
www.jntuworld.com
6. 4-BIT COMPARATOR- 7485
AIM: To verify the operation of 4-bit magnitude comparator using IC 7485.
APPARATUS:
1. IC 7485.
2. Bread board IC trainer kit.
3. Patch cords.
PIN DIAGRAM:
www.jntuworld.com
LOGIC DIAGRAM:
www.jntuworld.com
FUNCTION TABLE:
THEORY:
Comparing two binary words for equality is a commonly used operation in

computer systems and device interfaces. A circuit that compares two binary words and
indicates whether they are equal is called a comparator. Some comparators interpret
their input words as signed or unsigned numbers and also indicate an arithmetic
relationship (greater or less than) between the words. These devices are often called
magnitude comparators. A 1-bit Comparator is designed using Ex-OR and Ex-NOR
gates. The outputs of 4 XOR gates are ORed to create a 4-bit comparator. The IC 7485
is 4-bit magnitude comparator. With respect to the 8 inputs 3 inputs are cascaded
inputs. After the 8 input operations are performed further the outputs are based on the
cascaded inputs.
www.jntuworld.com
PROCEDURE:
1. Connect the circuit as per Pin diagram.

2. Give the inputs A [A3 ,A2, A1, A0] and B [B3,B2,B1,B0] according to function
table.
3. Give the cascaded inputs IA>B ,IA=B ,IA<B and verify the outputs.
4. Tabulate the inputs and outputs according to function table.
PRECAUTIONS:

VIVA QUESTIONS:
1. What is Magnitude Comparator?
2. To form a 12 bit comparator how many 4-bit comparators are connected in
cascaded form.
3. The IC 7485 is a package and is a ____ comparator.
4. How many cascaded input are there for a 4-bit comparator.
RESULT:
The operation of 4-bit magnitude comparator is verified using IC7485.
www.jntuworld.com
7. 8 x 1 MULTIPLEXER-74150
AIM: To verify the operation of 8*1 multiplexer using IC 74150.
APPARATUS:
1. IC74150.
2. Bread board IC trainer kit.
3. Patch cords.
PIN DIAGRAM:
www.jntuworld.com
LOGIC DIAGRAM:
TRUTH TABLE:
www.jntuworld.com
THEORY:
A multiplexer is a digital switch- it connects data from one of n sources to its

output. An 8*1 is multiplexer consists of 3 input lines as select lines and 8 input lines
and 1 output line. A multiplexer is a unidirectional device which follows the data from
input lines to output lines. Multiplexers are obviously useful device in any application in
which data must be multiple source to destination. A common application in computers
is the mux between the processors registers and its ALU.
PROCEDURE:
1. Connections are made as per logic diagram.

2. Connect the inputs D0 to D7 .
3. Give data select inputs and verify outputs according to truth table.
PRECAUTIONS:

VIVA QUESTIONS:
1. Mux is an implementation of
2. Multiplexer is represented by
3. De multiplexer is represented by
RESULT:
8*1 multiplexer is verified using IC74150.
www.jntuworld.com
8. RAM (164) - IC 7489

Aim: -To study the operation of the RAM Ic7489.
Apparatus: 1. RAM IC 7489 Trainer kits.
Pin Diagram: -
Operation:-
RAM IC 7489 is 16 words x 4-bit Read/WriteMemory.
The Truth Table for the RAM IC 7489 is given below.
www.jntuworld.com
The memory Enable pin is used to select 1- of-n ICs i.e. like a Chip Select signal. For simply
city, the memory enable pin is permanently held low.
The address lines are given through an up /down counter with preset capability.
The set address switch is held high to allow the user choose any location in the RAM, using the
address bits.
The address and data bits are used to set an address and enter the data.
The Read/Write switch is used to write data on to the RAM.
Procedure:
This experiment has 3 stages Clearing the memory, data entry (Write operation) and
data verification (Read operation).
Clearing the Memory: -The RAM IC 7489 is a volatile memory. This means that it will lose the
data stored in it, on loss of power. However, this dose not means that the content of the memory
becomes 0h, but not always. The RAM IC 7489 does not come with a Clear Memory signal.
The memory has to be cleared manually.
1. Position the Stack/Queue switch in the Queue position.
2. Position the Set Address switch in the 1 position.
3. Set the address bits to 0h (first byte in the memory)
4. Position the Set Address switch in the 0 position to disable random access and enable the
counter.
5. Position the Read/Write switch in the Write position to write data on to the memory.
6. Set the data bits to 0h (clearing the content)
7. Observe that the LEDs (D3 to D0) glow. This is to indicate that the content is 0h. Refer the
truth table above and observe that the data outputs of the RAM will be compliments of the data
inputs.
8. Position the Increment/Decrement switch in the Increment position.
9. Press the Clock to increment the counter to the next address. As the Read /Write switch is
already in the Write position, and the data bits are set to the 0h, the content in the new location
is also replaced with 0h.
www.jntuworld.com
Write Operation: -
1. Assume that the following data has to be written on to the RAM. The address and data are
given in the hexadecimal format.
2. Position the Stack/Queue switch in the Queueposition.
3. Position the Read/Write switch in the Write position to enable the entry of data in to the
RAM.
4. Position the Set Address switch in the 1 position to allow random access of memory.
5. Set the desired address (any address at random) using the address bit switches.
6. Set the desired data (refer table for the data to be entered in each location) using the data bit
switches.
7. Observe that the data is indicated by the LEDs (D3 toD0). This is because the data is written
on to the RAM.
8. Also observe that the data is indicated by the data outputs is the compliment of the data input
(refer truth table condition ME =L and WE=L) .
www.jntuworld.com
9. After each data entry, make a note of the location where data is entered. This is to make sure
that we are not re entering data in the same location.
10. Repeat steps 4 and 5 until data has been entered in all the addresses listed in the above table
11. Position the Read/Write switch in the Read position, to disable data entry.
12. This completes data entry.
Read Operation: -
1. Position the Stack/Queue switch in the Queue position.
2. Position the Set Address switch in the 0 position to allow random access of memory.
3. Position Read/Write switches in the Read position, to disable unauthorized entry of data.
4. Set the desired address (any address at random).
5. Observe that the data entered in the location is indicated by the LEDs (D3 toD0). This is
because the data was written during the data entry procedure.
6. Also observe that the data indicated by the data out puts is the compliment of the data input
(refer truth table condition ME=L and WE=H).
Result: - Operation of the RAM Ic7489 has been verified.
www.jntuworld.com

Analog and Digital IC Applications Lab Manual

Diunggah oleh

Informasi Dokumen

Hak Cipta

Format Tersedia

Bagikan dokumen Ini

Bagikan atau Tanam Dokumen

Opsi Berbagi

Apakah menurut Anda dokumen ini bermanfaat?

Apakah konten ini tidak pantas?

Hak Cipta:

Format Tersedia

Analog and Digital IC Applications Lab Manual

Diunggah oleh

Hak Cipta:

Format Tersedia

www.jntuworld.com www.jwjobs.

Study of OP AMPs - IC 741, IC 555-functioning, parameters and

Block Diagram of Op-Amp:

Prepared By SURESH BABU M

1. No frequency compensation required.

1. Voltage gain A = typically 2,00,000

6. Slew rate + V/sec

7. When V1 = V2, VD=0

Prepared By SURESH BABU M

Prepared By SURESH BABU M

Block Diagram of IC 555:

Prepared By SURESH BABU M

Function of Various Pins of 555 IC:

Prepared By SURESH BABU M

1. Operating temperature : SE 555-- -55oC to 125oC ,NE555---0 o to 70 o C

Monostable and Astable Multivibrators

Prepared By SURESH BABU M

1. OP AMP APPLICATIONS - ADDER, SUBTRACTOR,

Prepared By SURESH BABU M

Prepared By SURESH BABU M

Prepared By SURESH BABU M

Prepared By SURESH BABU M

Prepared By SURESH BABU M

2. ACTIVE FILTER APPLICATIONS - LPF, HPF [ FIRST ORDER ]

Prepared By SURESH BABU M

First Order HPF

Frequency O/P Voltage Gain

Prepared By SURESH BABU M

Frequency O/P Voltage Gain

Prepared By SURESH BABU M

Prepared By SURESH BABU M

3. Integrator and Differentiator Circuits using IC 741

S.No Equipment/Component name Specifications/Value Quantity

Prepared By SURESH BABU M

Prepared By SURESH BABU M

Where T= Time period of the input signal

Assume Cf and find Rf

Select given frequency fa = 1/(2RfC1), Assume C1 and find Rf

Select fb = 10 fa = 1/2R1C1 and find R1

From R1C1 = RfCf, find Cf

1. Connect the circuit as per the diagram shown in Fig

1. Connect the circuit as per the diagram shown in Fig

Prepared By SURESH BABU M

Fig 3: Input and output waves forms of integrator

Prepared By SURESH BABU M

Fig 4 :Input and output waveforms of Differentiator

Prepared By SURESH BABU M

Input Square wave Output - Triangular

Input sine wave Output - cosine

Input square wave Output - Spikes

Input sine wave Output - cosine

fa= 1/T = 1 KHz

Prepared By SURESH BABU M

Assuming Cf= 0.1f, Rf is found from Rf=1/(2faCf)

Assuming C1= 0.1f, Rf is found from R f=1/(2faC1)

for C1= 0.1f;

Precautions: Check the connections before giving the power supply.

Readings should be taken carefully.

Prepared By SURESH BABU M

Questions & Answers:

1. What are the problems of ideal differentiator?

2. What are the problems of ideal integrator?

3. What are the applications of differentiator and integrator?

4. What is the need for Rf in the circuit of integrator?