EEE/DSDCA/SV 1

MEMORY ORGANIZATION,
MEMORY HIERARCHY
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Computer
Input
Output
Control unit
Memory
ALU
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Topics :

Introduction
Memory organization
Memory hierarchy
Characteristics of memory systems
Main Memory design

Computer system performance depends on

processor architecture
memory system
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Introduction
Memory Memory system
Integral part of computer Internal memory
system
Main memory
Store information needed by
Secondary memory
the system
Holds program and data

Memory design
Memory system cost
Organization
Storage capacity
Speed of operation
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Memory Hierarchy
Main Memory I/O Processor
CPU

Cache

Magnetic
Disks Magnetic Tapes
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Internal memory
Registers in the CPU
Hold temporary results when computation in progress

Primary memory
Main memory
Storage area in which all programs are executed
CPU can directly access data that are stored in primary memory
Size larger than processor memory
Speed slower than processor memory

Secondary memory
Storage media
Magnetic discs
Used to hold data files and programs which are not frequently used.
Also referred to as backup store
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Design goals of memory system

Adequate storage capacity must be provided

Cost per bit must be low
Programmers must be relieved from performing tedious memory
management functions
Memory management algorithms must be devised in such a way that
it result in efficient space utilization
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Characteristics of memory systems

Important factor of a memory system
o Cost
expressed in dollars per bit
C= P/B C=cost per bit
P=cost P dollars
B=bits
Basic parameters indicates the speed of information transfer
o Access time, tA
Average time taken to read a unit of information from the memory
Read access time
Write access time
o Cycle time, tc
Average time lapse between successive read operations
o Access rate
reciprocal of access time
rA=1/tA : bits per sec(bps)
o Data transfer rate/bandwidth
rc=1/tc : bits per sec(bps) = baud rate
1baud= 1bps
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Characteristics of memory systems

Access modes
(method used to access information from the memory)

Two major access nodes:-

o Random access mode
o Sequential access mode(Serial access memory)

Combine both access modes:-

o Semi random/direct access memory
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Random access mode

Any location of the memory can be accessed at random
Access time tA, independent of location from where the data is read
Eg: Bipolar memory
Faster & more expensive

Sequential access mode

Memory accessed in a sequential manner
Access time, depends on location of data
Serial access memory
Eg: Magnetic tape

Semi random/direct access memory

Combine both access mode
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Characteristics of memory systems

Memory organization
Centralized memory organization
o Processors share one common memory unit
o Tightly coupled system
Features:
Inexpensive
Easy to control
High use of the available space

Distributed memory organization

o Processors share common memory , in addition each processor has
private/local memory attached to it.
o Memory system distributed
o Increases system cost and complexity of controller
o Advantages:
Several memory units can be kept busy at the same time
Processors are able to perform local processing
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centralized memory organization

distributed memory organization

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Passive memory system

no processing activity takes within a memory UNIT
Two operations possible: read from /write into memory
Less expensive

Conventional memory system

Positional addressable memory
Content addressable memory(associative memory)

Tagged memory unit

Untagged memory unit
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Position addressable memory

Stored item is selected by specifying its address
Address of the data must be first known
Data can be accessed by presenting the address to the memory
If the address of the data to be accessed is not available , data must be
searched for.

Content Addressable Memory

Does not require an address to access data.
When the memory unit is presented with a certain attribute of data the
memory responds with a presence flag & the data associated with the key(
if the key is found in the memory)
Key is simultaneously compared with all stored items for a match
Associative memory
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Untagged memory system

Stored items are viewed as a sequence of bits
No semantic details are provided

Tagged memory system

Adds semantic specifications to each stored item by appending
some extra bits(tag bits) to each stored item
Tag may be used to indicate whether a stored item is an instruction,
a data item or an address
Adv:-more protection to stored items against misuse
Elegant error detection mechanism
Minimum programming effort
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Main memory design

SRAM chip
Storage in the order of 210 bits
Designer obtain the needed memory capacity by
interconnecting several available small size memory chips
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Main Memory design

Eg: SRAM chip: 1K x 4
Chip has 210 x 4 = 1024 x 4 = 4096 bits
Organization: 210 = 1024 => words
4 bits per word
Each word has unique address
A9-A0 : 10 address lines
The inputs and outputs routed through 4- bit bidirectional data lines ,D3-
D0
Control inputs :
Write Enable-
Chip select-
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Main memory design

1K x 4 RAM system
high: chip not selected

, low: data on lines D 3-D0 are written into the word addressed by
A9-A0

low , high: contents of memory word will appear on lines D 3-D0

mode

H x Not selected
L L Write
L H read
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1K X 8 RAM
Two RAMs horizontally expanded
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1K X 8 RAM using two 1K x 4 RAMs

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4K x 4 RAM system
Four 1K x 4 RAMs vertically connected to get 4K x 4 RAM
4K x 4 = 4 x 210 x 4 = 212 x 4
Address bus- 12 bits wide
Data 4 bits
A11- A10 : inputs to a 2 to 4 decoder ,
Decoder outputs select the RAM chip
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4K x 4 RAM system using four 1K x 4

RAM
A11 A10 Chip selected

0 0 RAM chip 0
0 1 RAM chip 1
1 0 RAM chip 2
1 1 RAM chip 3
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If the required RAM size is M x N and

If the chip capacity is m x n

the number of chips = k =

where k is rounded up to nearest integer

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