Adiabatic CMOS Circuit Design: Principles and Examples

X. Wu, G. Hang, and M. Pedram

Abstract: In view of changing the type of energy conversion in CMOS circuits and thereby

achieving ultra-low-power design, this paper investigates adiabatic CMOS circuits, which use a

slow-ramping power clock. First, algebraic expressions for and properties of power-clocked signals

are discussed. Then the design of adiabatic gates based on AC power supply and CMOS

transmission gates is analyzed. On this basis, basic rules for the design of adiabatic circuits are

proposed, and a design example of an adiabatic full adder is demonstrated. PSPICE simulations

using a trapezoidal power-clock demonstrate that the designed adiabatic combinational circuits have

a correct logic function and low-power characteristics.

I. Introduction

Power dissipation in CMOS circuits is related to the type of energy conversion that they employ. In static CMOS

circuits, a DC power supply is used, and the signal value is realized by charging (or discharging) the node

capacitance. During this process, the charge is drawn from the power supply Vdd, then transported to node

capacitance and returned to the ground terminal, resulting in an irreversible energy conversion from electric energy

to heat. As a result, when a node capacitance is charged (or discharged), it leads to an energy dissipation of 1/2(CVdd

2
), where C is the node capacitance. Thus, reducing the energy dissipation has been equated with reducing the

switched-capacitance. Low power design that targets minimum switched-capacitance has made significant progress

in recent years [1]. It has been shown to be especially suitable to the design of low power sequential circuits where

significant energy savings have been observed [2-4]. However, the energy savings obtained are still limited.

Researchers and designers, however, remain interested in developing logic elements that operate based on a different

X. Wu is with the Institute of Circuits and Systems, Ningbo University, Ningbo 315211, Peoples Republic of China. Hang is
with the Department of Information and Electronic Engineering, Zhejiang University, Hangzhou 310027, Peoples Republic of
China. M Pedram is with the Department of Electrical Engineering-Systems, University of Southern California, Los Angeles CA
90089, USA.
type of energy conversion, i.e., one that minimizes the conversion of electric energy to heat.

An energy conversion is needed to represent a change in signal value. If energy exists only in one form, i.e.,

electric energy, then there is only one irreversible energy conversion from electric energy to heat. To break this

one-way conversion, researchers have introduced another energy form, i.e., magnetic field energy, into the digital

circuit. If the signal change is related to the conversion of electric energy to magnetic energy, the irreversible

conversion from electric energy to heat caused by dissipative elements, i.e., resistors, is largely avoided. For this

reason, researchers have attempted to make a breakthrough in low-power CMOS circuit design, from basic circuit

unit to microprocessor, by changing the mode of energy conversion.

Energy conversion from electric field to magnetic field and vice versa implies that circuits should be supplied

with AC power. In this case, signals in the circuits should also be alternating quantities. The latter has been

extensively used in dynamic CMOS logic, such as clocked CMOS logic, and domino logic. However, those circuits

still rely on DC power, and the energy conversion remains a conversion from electric energy to heat. Therefore,

circuits supplied with AC power should be studied further [5]. Since the AC power supply controls the working

rhythm of the circuit and acts as the clock, it has been called the power-clock [6].

Previous research shows that if the adopted power clock is gradually changing (rising or falling), less energy is

dissipated when charging and discharging the node capacitance through the conducting MOS transistor. Therefore,

the so-called adiabatic switching operation is realized, by which a new approach to designing ultra-low-power

CMOS circuits is proposed. Adiabatic computation has been widely studied as a low-power design technique. In the

recent years, several adiabatic or energy recovery logic architectures have been proposed [6-18]. They have

achieved significant power savings compared to conventional CMOS circuits. The outputs of these circuits are only

valid during a particular phase of the power clock cycle. Hence, multiple-phase clocking is required to drive a chain

of cascaded adiabatic logic circuits. The need for a multiple-phase power clock not only increases the power

dissipation of the clocking network, but it also results in extra complexity of both the logic and the required power

2
clock generator. An adiabatic logic circuit based on transmission gates was proposed in Ref.[7] and achieves fully

adiabatic computing at the cost of additional complexity in the clock waveforms for proper interfacing between

stages and additional complexity in circuit structure when implementing complex logic function. The proposed

adiabatic circuits in Refs.[8,9] use diodes or diode-like devices for pre-charging (or pre-discharging) that causes

unavoidable energy loss due to the voltage drop across the diodes. Other designs proposed in Ref.[10,11] eliminate

these pre-charge diodes; however, they require four-phase clocking. The number of clock phases is reduced in the

designs proposed in Refs.[12-14]. They require only two-phase clocking, but extra auxiliary timing control clock

signals are needed [13] and clock-powered latches are inserted between the logic gates [14]. Although a single-phase

clocking scheme is used in the designs proposed in Refs.[15,16], the extra demands of two DC reference voltages

and complementary control clock signals need to be met. Finally, it can be seen that the common feature of the

previously proposed circuits is that the input signals and the output signals in a circuit are not in the same

clock-phase [17], which results in the combinational circuits having the characteristics of the sequential circuit.

Furthermore, the non-adiabatic energy dissipation resulting from the loss of the threshold voltage of the MOS

transistor in the circuits proposed in Refs.[8-11,13-16] still exists. Reference [18] proposes that the loss of threshold

voltage can be avoided by using a bootstrapped MOS switch.

The methodology for designing adiabatic circuits in this paper has elements that are different from the previous

studies. First, the algebraic expressions and the corresponding properties of power-clocked signals in adiabatic

circuits are studies that serve as the mathematical basis for designing adiabatic circuits. Then some adiabatic gates

with a physical restoration function are designed by converting the demand of level-restoration in conventional

CMOS gates into the demand of pulse-restoration in adiabatic CMOS gates. All of the adiabatic gates proposed in

this paper do not have cross-coupled structure and the sequential characteristic, that is, the output and the input

signals will appear in the same clock phase. Finally, the design rules of adiabatic combinational circuits are summed

up, and the design procedures are demonstrated by taking the adiabatic full adder as an example. PSPICE

3
simulations adopting a trapezoidal power-clock prove that all the adiabatic circuits proposed in this paper have a

correct logic function and low-power characteristics.

II. Algebraic expressions for clocked signals

For the sake of simplicity, it is assumed that the clock of the CMOS circuit is a symmetric square-wave. When clk =

1, the clocked signal displays its true logic value; when clk = 0, the clocked signal is forced to its base value, 0 or

1. For the pre-charge circuits, the base value is 1, whereas for the pre-discharge circuits, the base value is 0.

Therefore, in every clock cycle, the clocked signal is divided into two stages: set base (B) when clk = 0 and evaluate

(E) when clk=1.

Figure 1 shows a pair of complementary signals x / x and the corresponding clocked signals. The values of

x / x in Fig.1 are (101101)/(010010); they could be regarded as the synchronous outputs of a falling-edge

triggered-flip-flop. x / x are, however, not clocked signals. In Fig.1, x clk , x clk , x +clk , and x + clk are the

four clocked signals derived from x / x . Notice that the superscript i in the expression of x i , i {clk ,+clk} ,

represents the logic relation between the original signals x / x and the clocks clk / clk . That is, x clk is x clk ,

x + clk is x + clk , and so on. Obviously, the function of ( clk ) or ( + clk ) is to set the clocked signal during the B

stage to base 0 or base 1, respectively.

B E B E B E B E B E B E
clk

clk
x

x
1 1 1 1
x clk 0 0
1 1
x clk 0 0 0 0
1 1 1 1
x + clk 0
1
0
1
x + clk 0 0 0 0

Fig.1 Four clocked signals derived from signal x

The following inverting relationships between these clocked signals can be observed (cf. Fig.1):

4
(i) Logical inverse (with the same base), such as x clk and x clk ; x + clk and x + clk .

(ii) Base inverse (with the same logic value), such as x clk and x + clk ; x clk and x + clk .

(iii) Complete inverse, such as x clk and x + clk ; x clk and x + clk .

Figure 1 also shows that:

x clk = x + clk , and x clk = x + clk . (1)

In line with the above-mentioned exponential expressions, the power supply Vdd (1), the ground (0), and the

clock ( clk / clk ) satisfy the following clocked expressions:

1 = 1+ clk , 0 = 0 clk . (2)

clk = 1clk , clk = 0 + clk . (3)

If the exponential operation is regarded as a Boolean operation, then Eq.(2) and Eq.(3) can be easily proved.

Furthermore, the following expressions can also be proven:

( x y ) clk = x clk y clk ,

(4)
( x y ) + clk = x + clk y + clk .

( x + y ) clk = x clk + y clk ,

(5)
( x + y ) + clk = x + clk + y + clk .

The physical meaning of the above Eq.(1) - Eq.(5) can be explained as follows:

(i) Eq.(1) represents De Morgans Law. It shows that the inverter function applied to clocked signals produces the

complete inverse of the original clocked signals (i.e., both the logic value and the base are inverted).

(ii) Eq.(2) shows that Vdd (1) and ground (0) can continually work in the clocked circuits of base 1 and base 0,

respectively.

(iii) Eq.(3) indicates that clk can assume the role of the power supply in the clocked circuit of base 0, whereas clk

can assume the role of the ground in the clocked circuit of base 1.

(iv) Eq.(4) and Eq.(5) suggest that the clocked signals that participate in the AND/OR operations should have the

same base. The result is equal to the AND/OR operation of the original signals and is clocked by the same base. It

5
should be pointed out that result of the NAND and NOR operations inverts the base due to Eq.(1).

III. Adiabatic CMOS gates

Considering that the basic circuits in adiabatic CMOS circuits are the gates, the structure of the adiabatic gates and

[19]
their working principles are investigated first . Similar to the traditional CMOS gates, the power-clocked CMOS

gates should also be of physical-restoration. In traditional CMOS gates, the outputs are always clamped to either the

power supply by a conductive pMOS transistor for the high-level output or the ground by a conductive nMOS

transistor for the low-level output, whereby the level-restoration is realized. Similarly, the outputs of the adiabatic

CMOS gates should also be clamped to the power clock by a conductive MOS switch to obtain pulse-restored

outputs. Because of the alternating feature of the power clock, the MOS switch used should be a complementary

CMOS transmission gate.

From the relationships among the clocked signals as shown in Fig.1, it is seen that a pair of complete inverse

clocked signals, x clk and x + clk , can be used to control the pMOS and nMOS transistors of the transmission gate,

respectively, and then the other pair of complete inverse clocked signals, x clk and x + clk , will be generated when

clk and clk are transmitted. Similarly, the latter pair of clocked signals can be used to control the transmission of

clk and clk to reproduce the original pair of clocked signals. Based on this analysis, the circuit shown in Fig. 2(a)

is derived. The relationships between the input and output in the circuit can be summed up as follows:

(i) The pair of clocked signals that are used to control any transmission gate should be the complete inverse of one

another. Furthermore, the base-0 and the base-1 signals control the pMOS and the nMOS transistors, respectively.

(ii) The output generated from clk is a base-0 signal and the logic inverse of the base-0 input signal acting on the

pMOS transistor. On the other hand, the output obtained from clk is a base-1 signal and the logic inverse of the

base-1 input signal acting on the nMOS transistor.

(iii) Given any four unrestored clocked signals, their four restored clocked signals can be obtained by using two

transmission gates to transmit the power clocks clk and clk .

6
 clk

x clk x clk
x clk
x + clk x + clk
x + clk
clk
a

16
Energy dissipation pj

static CMOS circuit

12

adiabatic CMOS circuit

4

0 10 20 30 40
Time ns
c

Fig. 2 Adiabatic CMOS inverter

a Adiabatic CMOS inverters

b PSPICE simulation result using a trapezoidal power-clock

c Energy dissipation curve

By using a trapezoidal power-clock and the PSPICE program, the circuit shown in Fig. 2(a) is simulated with 2

CMOS technology. The result is given in Fig. 2(b), where it is found that the output signals do not maintain a

flat-high top or flat-low bottom when the transmission gate shuts down. Taking x + clk as an example for explaining,

7
clk does not immediately jump to the high-level when x + clk is dropping. The nMOS transistor in the transmission

gate is still turned on at that moment, so the output tracks clk and rises until the nMOS transistor shuts down

completely. However, the simulation has verified that these un-flat outputs do not affect the next stage. Figure 2(c)

shows the energy dissipation curve of a one-stage circuit with the use of the trapezoidal power-clock with a clocked

input sequence pair (01010) and (10101). The declining part of this curve shows the effect of energy recovery. For

contrast, the energy dissipation curve of the common two-stage inverter using a DC power supply with the same

conditions is also drawn. It is shown that the former circuit has about an 86% energy savings in comparison with the

latter. The power saving is remarkable.

Based on the adiabatic CMOS inverter shown in Fig.2(a), the adiabatic NOR gate and NAND gate can be

designed further by connecting CMOS transmission gates in series and parallel as was done for the conventional

CMOS NOR gate and NAND gate. Take the adiabatic NOR gate shown in Fig.3(a) and (b) as an example. Their

logic functions can be explained as follows. In the base-setting period, clk = 0, all paths in Fig.3(a) and (b) are

conductive, and two outputs are set to 0 and 1 by transmitting clk = 0 and clk = 1 , respectively. Now we think about

the evaluation period: when clk = 1 and clk = 0 . In Fig.3(a) since source 1 (= clk) is transmitted through pMOS

transistors in series, which is like the pMOS part in a conventional CMOS NOR gate, the output will be x + y . If

clk
we consider that the output is a base-0 clocked signal, the output should be rewritten as x + y . On the other

hand, in Fig.3(b) the source 0 (= clk ) is transmitted through nMOS transistors in series, which is like the nMOS

part in a conventional CMOS NAND gate. Thus the output will be x y = x + y . Considering that the output is a

+ clk
base-1 clocked signal the output should be rewritten as ( x + y ) . According to De Morgans Law the signal can

clk
also be expressed as x + y , which is the complement of the output in Fig.3(a). Similarly, a discussion can be

carried out with the adiabatic NAND gate shown in Fig.3(c) and (d).

8
 x clk y clk
clk
a clk x+ y

x clk y clk

x clk y clk
+ clk
b clk xy
x clk y clk

x clk

clk
c clk x clk x y
y clk

y clk

x clk

x clk + clk
d clk x+y
y clk

y clk

Fig. 3 Adiabatic CMOS gates

a Adiabatic CMOS NOR gate with base-0 output

b Adiabatic CMOS OR gate with base-1 output

c Adiabatic CMOS NAND gate with base-0 output

d Adiabatic CMOS AND gate with base-1 output

IV. Adiabatic CMOS Combinational Circuits

The above discussion may be expanded to any adiabatic CMOS transistor network for realizing a more complicated

logic function. As an example, an adiabatic CMOS transistor network used to realize f = x ( y + z ) is given in

Fig.4(a). Its output can also be expressed as x clk + y clk z clk . Its complementary circuit can be easily derived by

simply replacing source clk with source clk . We have verified the adiabatic CMOS circuits by using a trapezoidal

power-clock. The PSPICE simulation results for inputs x (01010101), y (00110011), and z (00001111)are shown in

Fig.4(b). The output f has the correct response: (11101000).

Based on the above discussions of the basic adiabatic gates in Fig.3 and the adiabatic combinational circuit in

Fig.4, the rules for designing a general adiabatic CMOS combinational circuit composed of CMOS transmission

9
gate can be summarized as follows:

(i) First, re-express a logic function to be realized in its complementary form by using De Morgans Law.

(ii) Gate terminals of the pMOS transistor and nMOS transistors are connected to two complete-inverse clocked

input signals (a base-0 signal is connected to the pMOS transistor whereas a base-1 signal is connected to the nMOS

transistor).

x clk

clk
clk y clk x clk z clk x ( y + z)

y clk z clk
a

Fig. 4 Adiabatic CMOS network

a Adiabatic CMOS circuit for realizing f = x ( y + z )

b PSPICE simulation result using a trapezoidal power-clock

(iii) For the circuits with base-0 output signals (i.e., transmitting power clock clk), the OR-operation is realized

by connecting pMOS transistors in series, and the AND-operation is realized by connecting pMOS transistors in

parallel. The output signal is the complement of the logic operation of all base-0 input signals that act on the pMOS

transistors.

(iv) For the circuits with base-1output signals (i.e., transmitting power clock clk ), the AND-operation is realized

10
by connecting nMOS transistors in series, and the OR-operation is realized by connecting nMOS transistors in

parallel. The output signal is the complement of the logic operation of all base-1 input signals act on the nMOS

transistors.

(v) Finally, find the transmission switches that can be shared, in order to simplify the circuit structure.

As an example, we will design an adiabatic full adder by using the above design rules as follows. According to

the truth table of a full adder, the expressions of S and C+ can be derived:

S = ABC + AB C + A BC + A B C = A( BC + B C ) + A ( BC + B C )

6
= [ A + ( B + C ) ( B + C )] [ A + ( B + C ) ( B + C )]

C + = AB + AC + BC = A( B + C ) + BC = ( A + B C ) ( B + C )
7
Based on the above two equations and design rules, we can design a complete adiabatic full adder assembled by

CMOS transmission gates. However, we only discuss the part design for giving base-0 output signals as an example.

The circuit is shown in Fig.5(a), where A clk , B clk , C clk and A + clk , B + clk , C + clk represent base-0 and base-1 input

signals, respectively, S clk is the base-0 sum output signal (notice that the corresponding transmission gates

controlled by signals A and B are shared), and C + clk is the base-0 carry-out signal (the corresponding transmission

gate controlled by signal A is also shared). By using a trapezoidal power clock (frequency is 25MHz, peak-to-peak

supply is 3V) and with a Gray-coded input stream, we have simulated the circuit shown in Fig. 5(a) with the

PSPICE program. The simulation result given in Fig.5(b) proves that the designed circuit has the correct logic

function. The energy dissipation curve is given in Fig.5(c). For contrast, the energy dissipation curve of the static

CMOS full adder [20] realized with transmission gates is also given in Fig. 5(c) under the same simulation

conditions. The curve shows that the energy dissipation of the adiabatic full adder is less than 1pj within 700ns,

whereas the energy dissipation of static full adder exceeds 10pj within 700ns. Obviously, the power saving of the

adiabatic full adder is considerable. Similarly, the part design for giving base-1 output signals can also be derived.

11
 A + clk B + clk C + clk A + clk B + clk

A clk B clk C clk A clk B clk

B + clk C + clk
clk clk
S clk C + clk
B clk C clk
A + clk B + clk
C + clk B + clk C+ clk

Aclk B clk C clk B clk C clk

+ clk
B
a
clk
B

clk
+ clk
A
B + clk
C + clk
Aclk
B clk
C clk
S clk
C + clk
0 100 200 300 400 500 600 700
Time / ns
b
12
Energy Dissipation / pj

8
Static full adder

4
Adiabatic full adder

0
0 100 200 300 400 500 600 700
Time / ns
c

Fig. 5 Adiabatic CMOS full adder

a Adiabatic CMOS full adder with base-0 output signal

b PSPICE simulation result using a trapezoidal power clock

c Energy consumption curve

V. Conclusions

Adiabatic CMOS circuits, which adopt a gradually rising and falling power-clock, can result in a considerable

energy saving. However, the operational constraint that the output signal should track the power-clocks

12
slow-ramping behavior to accomplish the adiabatic charging and discharging processes creates a major difficulty in

the circuit design. In the previous studies of adiabatic circuits, researchers either adopt retractile cascade power

clocks or use multiple phase power clocks with memory schemes in the design [21,22]. Obviously, their

applicability will be limited. The research being performed on the algebraic expression of clocked signals and the

design of basic adiabatic gates with pulse restoration function are two key researches. Therefore, this paper first

presents a systematic study of clocked signals by using appropriate algebraic expressions and fully exploits the four

types of clocked signal. Furthermore, the design of an adiabatic CMOS gate based on AC power supply and CMOS

transmission gates is analyzed. On the above basis, the general rules for designing adiabatic CMOS combinational

circuits are further summarized. According to the proposed design rules, the design of an adiabatic CMOS full adder

composed of CMOS transmission gates is demonstrated. The PSPICE simulations using trapezoidal power clock

prove that the designed circuits have the correct logic function and considerable energy saving. The design principle

can also be used for designing more complicated adiabatic CMOS circuits.

To design an adiabatic digital system, merely researching on adiabatic gates and adiabatic combinational circuits

is insufficient. Following the research in this paper, the design of adiabatic flip-flop and the adiabatic sequential

circuits has been investigated. Corresponding research results will be reported in another paper.

VI. Acknowledgments

This work is supported in part by the NNSF of China (Grant No.69973039) and the NSF of USA (Grant

No.53-4503-2694).

VII. References

1 PEDRAM, M.: Power minimization in IC design: Principles and applications, ACM Transactions on Design Automation,

1996, 1, (1), pp.3-56.

2 WU, Q., PEDRAM, M., and WU, X.: Clock-gating and its application to low power design of sequential circuits, IEEE

Trans. on Circuits and Systems I: Fundamental Theory and Applications, 2000, 47, (3), pp. 415-420.

3 WU, X., and PEDRAM, M.: Low-power design on sequential circuits using T flip-flops, Int. J. Electronics, 2001, 88, (6),

13
 pp.635-643.

4 WU, X., PEDRAM, M., and WANG, L.: Multi-code state assignment for low power circuit design, IEE Proc.- Circuits

Devices Syst., 2000, 147, (5), pp. 271-275.

5 LAU, K., T., and LIU, F.: Four-phase improved adiabatic pseudo-domino logic, Electronics Letters 1998, 34, (4),

pp.343-344.

6 DENKER, J., S.: A review of adiabatic computing. Proceedings of the Symposium on Low Power Electronics, San Diego,

Oct. 1994, pp.94-97.

7 ATHAS, W., C., SVENSSON, L., J., KOLLER, J., G., TZARTZANIS, N., and CHOU, E.: Low-power digital systems

based on adiabatic-switching principles, IEEE Trans. on VLSI Systems, 1994, 2, (4), pp. 398-407.

8 DENKER, J., S., AVERY, S., C., DICKINSON, A., G., KRAMER, A., and WIK, T., R.: Adiabatic computing with the

2N-2N2D Logic family. Proceedings of the Workshop on Low Power Design, Napa Valley, Apr. 1994, pp.183-187.

9 DICKINSON, A., G., and DENKER, J., S.: Adiabatic dynamic logic, IEEE Journal of Solid-State Circuits, 1995, 30, (3),

pp.311-315.

10 KAMER, A., DENKER, J., S., FLOWER, B., and MORONEY, J.: 2ND order adiabatic computation with 2N-2P and

2N-2N2P logic circuits. Proceedings of the International Symposium on Low Power design, Dana Point, Apr. 1995,

pp.191-196.

11 MOON, Y., and JEONG, D., K.: An efficient charge recovery logic circuit, IEEE Journal of Solid-State Circuits, 1996,

SC-31, (4), pp.514-522.

12 OKLOBDZIJA, V., C., MAKSIMOVIC, D., and LIN, F.: Pass-transistor adiabatic logic using single-clock supply, IEEE

Transactions on Circuits and Systems-II: Analog and Digital Signal Processing, 1997, 44, (10), pp.842-846.

13 LIU, F., LAU, K., T., SIEK, L., and CHAN, P., K.: A low-power compact switched output adiabatic logic (CSOAL)

family, Int. J. Electronics, 1999, 86, (3), pp.323-328.

14 LO, C., -K., and CHAN, P., C., H.: An adiabatic differential logic for low-power digital systems, IEEE Transactions on

Circuits and Systems-II: Analog and Digital Signal Processing, 1999, 46, (9), pp.1245-1250.

15 KIM, S., and PAPAEFTHYMIOU, M., C.: True single-phase-recovering logic for low-power, high-speed VLSI.

Proceedings of the International Symposium on Low-Power Electronics and Design, Monterey, Aug. 1998, pp.167-172.

16 MAKSIMOVIC, D., OKLOBDZIJA, V., G., NIKOLIC, B., and CURRENT, K., W.: Clocked CMOS adiabatic logic with

integrated single-phase power-clock supply, IEEE Transactions on VLSI Systems, 2000, 8, (4), pp.460-463.

17 PEDRAM, M., and WU, X.: Analysis of clocked power CMOS gates with application to the design of energy-recovery

14
 circuits. Proceedings of ASP-DAC, Pacifico Yokohama, Jan. 2000, pp.339-344.

18 LIM, J., KIM, D., -G., and CHAE, S., -I.: Reduction in energy consumption by bootstrapped nMOS switches in reversible

adiabatic CMOS circuits, IEE Proceeding-Circuits, Devices and Systems, 1999, 146, (6), pp.327-333.

19 WU, X., and PEDRAM, M.: Low power CMOS circuits with clocked power. Proceedings of IEEE Asia Pacific

Conference on Circuits and Systems, Tianjin, Dec. 2000, pp.513-516.

20 ZHANG, N., and WU, H.: A new design of the CMOS full adder, IEEE J. of Solid-State Circuits, 1992, 27, (5),

pp.840-844.

21 WU, X., and HANG, G.: Principle of adiabatic computing and CMOS circuits with energy recovery, Chinese J. of

Computers, 2000, 23, (7), pp.779-785.

22 WU, X., and HANG, G.: Energy recovery circuits with cross-coupled structure, Journal of Circuits and Systems, 2000, 5,

(2), pp.1-8.

15
Figures

B E B E B E B E B E B E
clk

clk
x

x
1 1 1 1
x clk 0 0
1 1
x clk 0 0 0 0
1 1 1 1
x + clk 0
1
0
1
x + clk 0 0 0 0

Fig.1 Four clocked signals derived from signal x

16
 clk

x clk x clk
x clk
x + clk x + clk
x + clk
clk
a

16
Energy dissipation pj

static CMOS circuit

12

adiabatic CMOS circuit

4

0 10 20 30 40
Time ns
c

Fig. 2 Adiabatic CMOS inverter

a Adiabatic CMOS inverters

b PSPICE simulation result using a trapezoidal power-clock

c Energy dissipation curve

17
 x clk y clk
clk
a clk x+ y

x clk y clk

x clk y clk
+ clk
b clk xy
x clk y clk

x clk

clk
c clk x clk x y
y clk

y clk

x clk

x clk + clk
d clk x+y
y clk

y clk

Fig. 3 Adiabatic CMOS gates

a Adiabatic CMOS NOR gate with base-0 output

b Adiabatic CMOS OR gate with base-1 output

c Adiabatic CMOS NAND gate with base-0 output

d Adiabatic CMOS AND gate with base-1 output

18
 x clk

clk
clk y clk x clk z clk x ( y + z)

y clk z clk
a

Fig. 4 Adiabatic CMOS network

a Adiabatic CMOS circuit for realizing f = x ( y + z )

b PSPICE simulation result using a trapezoidal power-clock

19
 A + clk B + clk C + clk A + clk B + clk

A clk B clk C clk A clk B clk

B + clk C + clk
clk clk
S clk C + clk
B clk C clk
A + clk B + clk
C + clk B + clk C+ clk

Aclk B clk C clk B clk C clk

+ clk
B
a
clk
B

clk
+ clk
A
B + clk
C + clk
Aclk
B clk
C clk
S clk
C + clk
0 100 200 300 400 500 600 700
Time / ns
b
12
Energy Dissipation / pj

8
Static full adder

4
Adiabatic full adder

0
0 100 200 300 400 500 600 700
Time / ns
c

Fig. 5 Adiabatic CMOS full adder

a Adiabatic CMOS full adder with base-0 output signal,

b PSPICE simulation result using a trapezoidal power clock,

c Energy consumption curve

20