ComputerArchitecture:PartII

FirstSemester2013
DepartmentofComputerScience
FacultyofScience
ChiangMaiUniversity
 Outline
CombinationalCircuits
FlipsFlops
Flips Flops
SequentialCircuits

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 Combinational Circuits
CombinationalCircuits
Acombinationalcircuitisaconnected
bi i l i i i d
arrangementoflogicgateswithasetofinputs
andoutputs.
d t t
Thenbinaryinputvariablescomefroman
externalsource,thembinaryoutputvariablesgo
toanexternaldestination,andinbetweenthere
i i
isainterconnectionoflogicgates.
i fl i
Acombinationalcircuittransformsbinary
informationfromthegiveninputdatatothe
requiredoutputdata.
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Blockdiagramofacombinational
circuit

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 HalfAdder
Th
Themostbasicdigitalarithmeticcircuitisthe
t b i di it l ith ti i it i th
additionoftwobinarydigits.
Acombinationalcircuitthatperformsthe
A combinational circuit that performs the
arithmeticadditionoftwobitsiscalledahalf
adder.
adder
Onethatperformstheadditionofthreebits(two
significant its and a previous carry) is called a full
significantitsandapreviouscarry)iscalledafull
adder.
Thenameoftheformerstemsfromthefactthat
twohalfaddersareneededtoimplementafull
adder.

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 Halfadder

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 Halfadder
Weassignsymbolsxandytothetwoinput
( ) ( y)
variables,andS(forsum)andC(forcarry)to
thetwooutputvariables.
TheCoutputis0unlessbothinputsare1.
The C output is 0 unless both inputs are 1
TheSoutputrepresentstheleastsignificant
bitofthesum.
S=x
S = xyy +xy =xy
+ xy =x
C=xy
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 Fulladder
A
Afulladderisacombinationalcircuitthatformsthe
f ll dd i bi ti l i it th t f th
arithmeticsumofthreeinputbits.
Twooftheinputvariables,denotedbxandy,
Two of the input variables denoted b x and y
representthetwosignificantbitstobeadded.
Thethirdinput,z,representsthecarryfromthe
p p y
previouslowersignificantposition.
ThetwooutputsaredesignatedbythesymbolsS(for
sum) and C (for carry)
sum)andC(forcarry).
ThebinaryvariableSgivesthevalueoftheleast
significant bit of the sum
significantbitofthesum.
ThebinaryvariableCgivestheoutputcarry.

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Truth Table for FullAdder
TruthTableforFullAdder

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 Maps for fulladder
Mapsforfulladder

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 Fulladder circuit
Fulladdercircuit

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 FlipFlops
Themostcommontypeofsequentialcircuitis
h f i l i i i
thesynchronoustype.
Synchronizationisachievedbyatimingdevice
p g p
calledaclockpulsegeneratorthatproducesa
periodictrainofclockpulses.
Theclockpulsesaredistributedthroughout
The clock pulses are distributed throughout
thesysteminsuchawaythatstorage
elements are affected only with the arrival of
elementsareaffectedonlywiththearrivalof
thesynchronizationpulse.

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 FlipFlops
Thestorageelementsemployedinclocked
h l l di l k d
sequentialcircuitsarecalledflipflops.
Aflipflopisabinarycellcapableofstoring
onebitofinformation.
Ithastwooutputs,onefornormalvalueand
one for the complement value of the bit
oneforthecomplementvalueofthebit
storedinit.
Aflipflopmaintainsabinarystateuntil
A fli fl i t i bi t t til
directedbyaclockpulsetoswitchstates.
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 SR FlipFlop
SRFlipFlop
Ithasthreeinputs,labeledS(forset),R(for
h h i l b l d S (f ) (f
reset),andC(forclock).
IthasanoutputQandsometimestheflipflop
hasacomplementedoutput,whichisindicated
withasmallcircleattheotheroutputterminal.
Thereisanarrowheadshapedsymbolinfrontof
theletterCtodesignateadynamicinput.
y y
Thedynamicindicatorsymboldenotesthefact
thattheflipfloprespondstoapositivetransition
(from0to1)oftheinputclocksignal.
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 SR FlipFlop
SRFlipFlop
IfthereisnosignalattheclockinputC,the
p
outputofthecircuitcannotchange g
irrespectiveofthevaluesatinputsSandR.
Onlywhentheclocksignalchangesfrom0to
Only when the clock signal changes from 0 to
1cantheoutputbeaffectedaccordingothe
valuesininputsSandR.
l

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 SR flipflop
SRflipflop

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 D FlipFlop
DFlipFlop
Th
ThenextstateQ(t+1)isdeterminedfromtheD
t t t Q(t 1) i d t i df th D
input.
ADflipflophastheadvantageofhavingonlyone
A D flip flop has the advantage of having only one
input(excludingC).
Ithasdisadvantagethatitscharacteristictable
It has disadvantage that its characteristic table
doesnothaveanochangecondition
Q(t 1) O(t).
Q(t+1)=O(t).
Thenochangeconditioncanbeaccomplished
eitherbydisablingtheclocksignalorbyfeeding
y g g y g
theoutputbackintotheinput,sothatclock
pulseskeepthestateoftheflipflopunchanged.

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 D (data) flipflop
D(data)flipflop

Q(t+1)=D
( )

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 JK FlipFlop
JKFlipFlop
InputsJandKbehavelikeinputsSandRtoset
p p p y
andcleartheflipflop,respectively.
WheninputsJandKarebothequalto1,a
clock transition switches the outputs of the
clocktransitionswitchestheoutputsofthe
flipfloptotheircomplementstate.

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 JK flipflop
JKflipflop

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 T (toggle) FlipFlop
T(toggle)FlipFlop
TheTflipflophasonlytwoconditions.
WhenT
When T =0(J
0 (J =K
K =0)aclocktransitiondoes
0) a clock transition does
notchangethestateoftheflipflop.
WhenT=1(J=K=1)aclocktransition
Wh T 1 (J K 1) l k ii
complementsthestateoftheflipflop.

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 T flipflop
Tflipflop

( ) ( )T
Q(t+1)=Q(t)

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 EdgeTriggered FlipFlops
EdgeTriggeredFlipFlops
Inthistypeofflipflop,outputtransitions
p p
occurataspecificleveloftheclockpulse.
Whenthepulseinputlevelexceedsthis
threshold level the inputs are locked out so
thresholdlevel,theinputsarelockedoutso
thattheflipflopisunresponsivetofurther
changesininputsuntiltheclockpulsereturns
h l h l k l
to0andanotherpulseoccurs.

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 Positiveedgetriggered D flipflop
PositiveedgetriggeredDflipflop
ThevalueintheDistransferredtotheQ
p p
outputwhentheclockmakesapositive
transition.
Theoutputcannotchangewhentheclockisin
The output cannot change when the clock is in
the1level,inthe0level,orinatransition
f
fromthe1leveltothe0level.
th 1 l l t th 0 l l

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Negativeedgetriggered D flipflop
NegativeedgetriggeredDflipflop
Thegraphicsymbolincludesanegationsmall
y
circleinfrontofthedynamicindicatorattheC
input.
Thisdenotesanegativeedgetriggered
This denotes a negative edge triggered
behavior.
Inthiscasetheflipfloprespondstoa
transition from the 1 level to the 0 level of the
transitionfromthe1leveltothe0levelofthe
clocksignal.

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Edgetriggered flipflop
Edgetriggeredflipflop

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 Excitation Tables
ExcitationTables
Thecharacteristictablesofflipflopsspecify
p
thenextstatewhentheinputsandthe
presentstateareknown.
Duringthedesignofsequentialcircuitswe
During the design of sequential circuits we
usuallyknowtherequiredtransitionfrom
presentstatetonextdateandwishtofindthe
h f h
flipflopinputconditionsthatwillcausethe
requiredtransition.

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Excitation Table for Four FlipFlops
ExcitationTableforFourFlipFlops

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 Excitation Tables
ExcitationTables
Thesymbolxinthetablesrepresentsadont
carecondition.
Forexample,inaJKflipflop,atransitionfrom
present state of 0 to a next state of 0 can be
presentstateof0toanextstateof0canbe
achievedbyhavinginputsJandKequalto0
(
(toobtainnochange)orbylettingJ=0andK=1
b h ) b l
tocleartheflipflop(althoughitisalready
cleared).

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 Sequential Circuits
SequentialCircuits
Asequentialcircuitisaninterconnectionof
p p g
flipflopandgates.
Itconsistsofacombinationalcircuitanda
number of clocked flip flops
numberofclockedflipflops.
Ingeneral,anynumberortypeofflipflops
maybeincluded.

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 Blockdiagramofaclocked
synchronoussequentialcircuit

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Example of a sequential circuit
Exampleofasequentialcircuit

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 FlipFlop Input Equations
FlipFlopInputEquations
Thepartofthecombinationalcircuitthat
h f h bi i l i i h
generatestheinputstoflipflopsare
describedbyasetofBooleanexpressions
calledflipflopinputequations.
Weadopttheconventionofusingtheflipflop
p y p q
inputsymboltodenotetheinputequation
variablenameandasubscripttodesignate
the symbol chosen for the output of the flip
thesymbolchosenfortheoutputoftheflip
flop.

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 FlipFlop Input Equations
FlipFlopInputEquations
TheoutputoftheORgateisconnectedtotheD
h f h O i d h
inputofflipflopA,wewritethefirstequationas
DA =Ax+Bx
Thesecondinputequationisderivedfromthe
p q
singleANDgatewhoseinputisconnectedtothe
DinputofflipflopB
DB =Ax
Theexternaloutputofasequentialcircuitis
The external output of a sequential circuit is
y=Ax +Bx

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 State Table
StateTable
Asequentialcircuitisspecifiedbyastatetable
p
thatrelatesoutputsandnextstatesasa
functionofinputsandpresentstates.
Thenextstatevalueofaeachflipflopisequal
The next state value of a each flip flop is equal
toitsDinputvalueinthepresentstate.
Theoutputcolumnisderivedfromtheoutput
equation.

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State Table for Sequential Circuit
StateTableforSequentialCircuit

204231:ComputerOrganizationandArchitecture 36
 State Diagram
StateDiagram
IInthistypeofdiagram,astateisrepresentedbya
thi t f di t t i t db
circle,andthetransitionbetweenstatesisindicatedby
directedlinesconnectingthecircles.
g
Thebinarynumberinsideeachcircleidentifiesthe
stateoftheflipflops.
Thedirectedlinesarelabeledwithtwobinarynumbers
separatedbyaslash.
Theinputvalueduringthepresetstateislabeledfirst
The input value during the preset state is labeled first
andthenumberaftertheslashgivestheoutputduring
thepresentstate.
p
Adirectedlineconnectingacirclewithitselfindicates
thatnochangeofstateoccurs.

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State diagrams of sequential circuit
Statediagramsofsequentialcircuit

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 Design Example
DesignExample
Thedesignprocedureconsistsoffirst
g p
translatingthecircuitspecificationsintoa
statediagram.
Thestatediagramisthenconvertedintoa
The state diagram is then converted into a
statetable.
Fromthestatetableweobtainthe
information for obtaining the logic circuit
informationforobtainingthelogiccircuit
diagram.

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 Design Example
DesignExample
Wewishtodesignaclockedsequentialcircuit
thatgoesthroughasequenceofrepeatedbinary
states00,01,10,and11whenaexternalinputx
isequalto1.
q
Thestateofthecircuitremainsunchangedwhen
x=0.
x=0
Thistypeofcircuitiscalleda2bitbinarycounter
b
becausethestatesequenceisidenticaltothe
h i id i l h
countsequenceoftwobinarydigits.

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State diagram for binary counter
Statediagramforbinarycounter

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The excitation table for binary counter
Theexcitationtableforbinarycounter

Theexcitationtableofasequentialcircuitis
anextensionofthestatetable.
Thisexcitationconsistsofalistofflipflop
input excitations that will cause the required
inputexcitationsthatwillcausetherequired
statetransitions.
Theflipflopinputconditionsareafunctionof
thetypeofflipflopused.
yp p p

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The excitation table for binary counter
Theexcitationtableforbinarycounter
IInthefirstrowofbelowtable,wehaveatransitionfor
h fi fb l bl h ii f
flipflopAfrom0inthepresentstateto0inthenext
state.
state
Fromslidenumber28wefindthatatransitionof
states from Q(t)=0 to Q(t+1)=0 in a JK flipflop
statesfromQ(t)=0toQ(t+1)=0inaJKflip floprequires
requires
thatinputJ=0andinputK=x.
So0andxarecopiedinthefirstrowunderJAandKA,
So 0 and x are copied in the first row under JA and KA,
respectively.
SincethefirstrowalsoshowsatransitionforflipflopB
p p
from0inthepresentstateto0inthenextstate,0and
xarecopiedinthefirstrowunderJBandKB.

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Excitation Table for Binary Counter
ExcitationTableforBinaryCounter

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The design of logic circuit diagram
Thedesignoflogiccircuitdiagram.
Theinputstothecombinationalcircuitarethe
p p
externalinputxandthepresentstatevalues
offlipflopsAandB.
Theentriesthatlistthecombinationalcircuit
The entries that list the combinational circuit
inputsarespecifiedunderthepresetstate
andinputcolumnsintheexcitationtable.
l h bl
Thecombinationalcircuitoutputsare
The combinational circuit outputs are
specifiedundertheflipflopinputscolumns.

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Mapsforcombinatorialcircuitof
counter

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Logic diagram of a 2bit binary counter
Logicdiagramofa2bitbinarycounter

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 Reference
M.MorisMano,ComputerSystem
Architecture,3rded.NJ:PrenticeHall,1992.

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